U.S. patent application number 15/368025 was filed with the patent office on 2017-12-14 for fan-out semiconductor package.
The applicant listed for this patent is SAMSUNG ELECTRO-MECHANICS CO., LTD.. Invention is credited to Dae Jung BYUN, Jung Soo KIM, Doo Hwan LEE.
Application Number | 20170358534 15/368025 |
Document ID | / |
Family ID | 60574248 |
Filed Date | 2017-12-14 |
United States Patent
Application |
20170358534 |
Kind Code |
A1 |
KIM; Jung Soo ; et
al. |
December 14, 2017 |
FAN-OUT SEMICONDUCTOR PACKAGE
Abstract
A fan-out semiconductor package includes: a first
interconnection member having a through-hole; a semiconductor chip
disposed in the through-hole; an encapsulant encapsulating at least
portions of the first interconnection member and the semiconductor
chip; a second interconnection member disposed on the first
interconnection member and the semiconductor chip and including
redistribution layers electrically connected to the connection pads
of the semiconductor chip; a passivation layer disposed on the
second interconnection member and having openings exposing at least
portions of the redistribution layer of the second interconnection
member; and an under-bump metal layer disposed on the passivation
layer and filling at least portions of the openings. In the
under-bump metal layer, the number of conductor layers formed on a
surface of the passivation layer is different from that of
conductor layers formed on the exposed redistribution layer and
walls of the openings.
Inventors: |
KIM; Jung Soo; (Suwon-si,
KR) ; BYUN; Dae Jung; (Suwon-si, KR) ; LEE;
Doo Hwan; (Suwon-si, KR) |
|
Applicant: |
Name |
City |
State |
Country |
Type |
SAMSUNG ELECTRO-MECHANICS CO., LTD. |
Suwon-si |
|
KR |
|
|
Family ID: |
60574248 |
Appl. No.: |
15/368025 |
Filed: |
December 2, 2016 |
Current U.S.
Class: |
1/1 |
Current CPC
Class: |
H01L 23/5389 20130101;
H01L 2924/1433 20130101; H01L 23/5383 20130101; H01L 2924/1436
20130101; H01L 2924/00012 20130101; H01L 2924/00012 20130101; H01L
2924/00012 20130101; H01L 2224/13147 20130101; H01L 24/11 20130101;
H01L 2224/11462 20130101; H01L 2924/00 20130101; H01L 2924/00012
20130101; H01L 2924/00014 20130101; H01L 2924/18165 20130101; H01L
24/05 20130101; H01L 24/13 20130101; H01L 2924/3511 20130101; H01L
2224/24155 20130101; H01L 24/20 20130101; H01L 2924/1431 20130101;
H01L 23/49811 20130101; H01L 2924/1434 20130101; H01L 2224/02166
20130101; H01L 2924/1433 20130101; H01L 23/3114 20130101; H01L
2924/1436 20130101; H01L 2924/1431 20130101; H01L 2924/3511
20130101; H01L 23/3128 20130101; H01L 24/19 20130101; H01L
2224/05024 20130101; H01L 24/24 20130101; H01L 2224/0401 20130101;
H01L 2224/05624 20130101; H01L 2224/11464 20130101; H01L 23/5384
20130101; H01L 24/82 20130101; H01L 2224/05624 20130101; H01L
23/5386 20130101; H01L 2924/1434 20130101; H01L 2224/13026
20130101 |
International
Class: |
H01L 23/538 20060101
H01L023/538; H01L 23/31 20060101 H01L023/31; H01L 23/00 20060101
H01L023/00 |
Foreign Application Data
Date |
Code |
Application Number |
Jun 8, 2016 |
KR |
10-2016-0070900 |
Aug 24, 2016 |
KR |
10-2016-0107687 |
Claims
1. A semiconductor package comprising: a first interconnection
member including a redistribution layer; a semiconductor chip
disposed on the first interconnection member and having an active
surface having connection pads disposed thereon and an inactive
surface opposing the active surface, the connection pads of the
semiconductor chip being electrically connected to the
redistribution layer of the first interconnection member; an
encapsulant encapsulating the inactive surface of the semiconductor
chip; a passivation layer including an inner surface in contact
with the first interconnection member and an outer surface opposing
the inner surface, and having an opening exposing a portion of the
redistribution layer of the first interconnection member; and an
under-bump metal layer disposed on the passivation layer and
filling at least a portion of the opening, wherein the under-bump
metal layer includes a first conductor layer disposed only on the
outer surface of the passivation layer.
2. The semiconductor package of claim 1, wherein the number of
conductor layers formed on the outer surface of the passivation
layer is larger than the number of conductor layers formed on the
exposed redistribution layer and a wall of the opening.
3. The semiconductor package of claim 1, wherein the under-bump
metal layer further includes a second conductor layer disposed on
the first conductor layer and extending to contact a wall of the
opening and the exposed redistribution layer, and a third conductor
layer formed on the second conductor layer.
4. The semiconductor package of claim 3, wherein the first
conductor layer includes electrolytic copper (Cu), the second
conductor layer includes electroless copper (Cu), and the third
conductor layer includes electrolytic copper (Cu).
5. The semiconductor package of claim 3, wherein the second
conductor layer has a thickness less than thicknesses of the first
conductor layer and the third conductor layer.
6. The semiconductor package of claim 3, wherein the passivation
layer includes an inorganic filler and an insulating resin.
7. The semiconductor package of claim 6, wherein at least one of
chemical reaction groups included in the insulating resin of the
passivation layer is self-assembled to a metal of the first
conductor layer.
8. The semiconductor package of claim 1, further comprising
connection terminals disposed on the under-bump metal layer and
electrically connected to the connection pads of the semiconductor
chip, wherein at least one of the connection terminals is disposed
in a fan-out region.
9. The fan out semiconductor package of claim 1, further comprising
a second interconnection member having a through-hole in which the
semiconductor chip is disposed, wherein the encapsulant
encapsulates a portion of the second interconnection member, the
second interconnection member includes a first insulating layer, a
first redistribution layer in contact with the first
interconnection member and embedded in the first insulating layer,
and a second redistribution layer disposed on the other surface of
the first insulating layer opposing one surface of the first
insulating layer in which the first redistribution layer is
embedded, and the first and second redistribution layers are
electrically connected to the connection pads.
10. The semiconductor package of claim 9, wherein the second
interconnection member further includes a second insulating layer
disposed on the first insulating layer and covering the second
redistribution layer and a third redistribution layer disposed on
the second insulating layer, and the third redistribution layer is
electrically connected to the connection pads.
11. The semiconductor package of claim 9, wherein a distance
between the redistribution layer of the first interconnection
member and the first redistribution layer is greater than that
between the redistribution layer of the first interconnection
member and the connection pads.
12. The semiconductor package of claim 9, wherein the first
redistribution layer has a thickness greater than that of the
redistribution layer of the first interconnection member.
13. The semiconductor package of claim 9, wherein a lower surface
of the first redistribution layer is disposed on a level above a
lower surface of the connection pads.
14. The semiconductor package of claim 10, wherein the second
redistribution layer is disposed on a level between the active
surface and the inactive surface of the semiconductor chip.
15. The semiconductor package of claim 1, further comprising a
second interconnection member having a through-hole in which the
semiconductor chip is disposed, wherein the encapsulant
encapsulates a portion of the second interconnection member, the
second interconnection member includes a first insulating layer, a
first redistribution layer and a second redistribution layer
disposed on opposite surfaces of the first insulating layer,
respectively, a second insulating layer disposed on the first
insulating layer and covering the first redistribution layer, and a
third redistribution layer disposed on the second insulating layer,
and the first to third redistribution layers are electrically
connected to the connection pads.
16. The semiconductor package of claim 15, wherein the second
interconnection member further includes a third insulating layer
disposed on the first insulating layer and covering the second
redistribution layer and a fourth redistribution layer disposed on
the third insulating layer, and the fourth redistribution layer is
electrically connected to the connection pads.
17. The semiconductor package of claim 15, wherein the first
insulating layer has a thickness greater than that of the second
insulating layer.
18. The semiconductor package of claim 15, wherein the third
redistribution layer has a thickness greater than that of the
redistribution layer of the first interconnection member.
19. The semiconductor package of claim 15, wherein the first
redistribution layer is disposed on a level between the active
surface and the inactive surface of the semiconductor chip.
20. The semiconductor package of claim 15, wherein a lower surface
of the third redistribution layer is disposed on a level below a
lower surface of the connection pads.
21. The semiconductor package of claim 1, further comprising a
rigid member having a through-hole in which the semiconductor chip
is disposed, wherein the encapsulant encapsulates a portion of the
rigid member.
22. The semiconductor package of claim 1, further comprising a
second interconnection member having a through-hole in which the
semiconductor chip is disposed, wherein the encapsulant
encapsulates a portion of the second interconnection member, the
second interconnection member includes a first insulating layer,
and a first redistribution layer and a second redistribution layer
disposed on opposite surfaces of the first insulating layer, and
the first and second redistribution layers are electrically
connected to the connection pads.
Description
CROSS-REFERENCE TO RELATED APPLICATION(S)
[0001] This application claims benefit of priority to Korean Patent
Application Nos. 10-2016-0070900 filed on Jun. 8, 2016 and
10-2016-0107687 filed on Aug. 24, 2016 in the Korean Intellectual
Property Office, the disclosures of which are incorporated herein
by reference in their entirety.
TECHNICAL FIELD
[0002] The present disclosure relates to a semiconductor package,
and more particularly, to a fan-out semiconductor package in which
connection terminals may extend outwardly of a region in which a
semiconductor chip is disposed.
BACKGROUND
[0003] Recently, a significant recent trend in the development of
technology related to semiconductor chips has been to reduce the
size of semiconductor chips. Therefore, in the field of package
technology, in accordance with a rapid increase in demand for
small-sized semiconductor chips, or the like, the implementation of
a semiconductor package having a compact size while including a
plurality of pins has been demanded.
[0004] One type of package technology suggested to satisfy the
technical demand as described above is a fan-out package. Such a
fan-out package has a compact size and may allow a plurality of
pins to be implemented by redistributing connection terminals
outwardly of a region in which a semiconductor chip is
disposed.
SUMMARY
[0005] An aspect of the present disclosure may provide a fan-out
semiconductor package in which sufficient close adhesion of an
under-bump metal layer may be secured.
[0006] According to an aspect of the present disclosure, a fan-out
semiconductor package may be provided, in which an under-bump metal
layer is formed on a surface of a passivation layer using a
laminate to which a conductor layer is attached.
[0007] According to an aspect of the present disclosure, a fan-out
semiconductor package may include: a first interconnection member
having a through-hole; a semiconductor chip disposed in the
through-hole of the first interconnection member and having an
active surface having connection pads disposed thereon and an
inactive surface opposing the active surface; an encapsulant
encapsulating at least portions of the first interconnection member
and the inactive surface of the semiconductor chip; a second
interconnection member disposed on the first interconnection member
and the active surface of the semiconductor chip and including a
redistribution layer electrically connected to the connection pads
of the semiconductor chip; a passivation layer disposed on the
second interconnection member and having openings exposing at least
portions of the redistribution layer of the second interconnection
member; and an under-bump metal layer disposed on the passivation
layer and filling at least portions of the openings. The first
interconnection member includes redistribution layers electrically
connected to the connection pads of the semiconductor chip, and in
the under-bump metal layer, the number of conductor layers formed
on a surface of the passivation layer is different from that of
conductor layers formed on the exposed redistribution layer and
walls of the openings.
BRIEF DESCRIPTION OF DRAWINGS
[0008] The above and other aspects, features, and advantages of the
present disclosure will be more clearly understood from the
following detailed description taken in conjunction with the
accompanying drawings, in which:
[0009] FIG. 1 is a schematic block diagram illustrating an example
of an electronic device system;
[0010] FIG. 2 is a schematic perspective view illustrating an
example of an electronic device;
[0011] FIGS. 3A and 3B are schematic cross-sectional views
illustrating states of a fan-in semiconductor package before and
after being packaged;
[0012] FIG. 4 is schematic cross-sectional views illustrating a
packaging process of a fan-in semiconductor package;
[0013] FIG. 5 is a schematic cross-sectional view illustrating a
case in which a fan-in semiconductor package is mounted on an
interposer substrate and is finally mounted on a main board of an
electronic device;
[0014] FIG. 6 is a schematic cross-sectional view illustrating a
case in which a fan-in semiconductor package is embedded in an
interposer substrate and is finally mounted on a main board of an
electronic device;
[0015] FIG. 7 is a schematic cross-sectional view illustrating a
fan-out semiconductor package;
[0016] FIG. 8 is a schematic cross-sectional view illustrating a
case in which a fan-out semiconductor package is mounted on a main
board of an electronic device;
[0017] FIG. 9 is a schematic cross-sectional view illustrating an
example of a fan-out semiconductor package;
[0018] FIG. 10 is a schematic plan view taken along line I-I' of
the fan-out semiconductor package of FIG. 9;
[0019] FIGS. 11A and 11B are schematic enlarged views illustrating
region A of the fan-out semiconductor package of FIG. 9;
[0020] FIGS. 12A through 12G are schematic views illustrating an
example of processes of manufacturing the fan-out semiconductor
package of FIG. 9;
[0021] FIG. 13 is schematic views illustrating an example of a
process of manufacturing a laminate used in FIGS. 12A through
12G;
[0022] FIG. 14 is a schematic view illustrating self-assembly
between a passivation layer and a metal layer;
[0023] FIG. 15 is a schematic view illustrating a normal cured
state of a passivation layer;
[0024] FIG. 16 is a schematic cross-sectional view illustrating
another example of a fan-out semiconductor package; and
[0025] FIG. 17 is a schematic cross-sectional view illustrating
another example of a fan-out semiconductor package.
DETAILED DESCRIPTION
[0026] Hereinafter, exemplary embodiments in the present disclosure
will be described with reference to the accompanying drawings. In
the accompanying drawings, shapes, sizes, and the like, of
components may be exaggerated or shortened for clarity.
[0027] The term "an exemplary embodiment" used herein does not
refer to the same exemplary embodiment, and is provided to
emphasize a particular feature or characteristic different from
that of another exemplary embodiment. However, exemplary
embodiments provided herein are considered to be able to be
implemented by being combined in whole or in part one with another.
For example, one element described in a particular exemplary
embodiment, even if it is not described in another exemplary
embodiment, may be understood as a description related to another
exemplary embodiment, unless an opposite or contradictory
description is provided therein.
[0028] The meaning of a "connection" of a component to another
component in the description includes an indirect connection
through a third component as well as a direct connection between
two components. In addition, "electrically connected" means the
concept including a physical connection and a physical
disconnection. It can be understood that when an element is
referred to with "first" and "second", the element is not limited
thereby. They may be used only for a purpose of distinguishing the
element from the other elements, and may not limit the sequence or
importance of the elements. In some cases, a first element may be
referred to as a second element without departing from the scope of
the claims set forth herein. Similarly, a second element may also
be referred to as a first element.
[0029] Herein, an upper portion, a lower portion, an upper side, a
lower side, an upper surface, a lower surface, and the like, are
decided in the attached drawings. For example, a first
interconnection member is disposed on a level above a
redistribution layer. However, the claims are not limited thereto.
In addition, a vertical direction refers to the abovementioned
upward and downward directions, and a horizontal direction refers
to a direction perpendicular to the abovementioned upward and
downward directions. In this case, a vertical cross section refers
to a case taken along a plane in the vertical direction, and an
example thereof may be a cross-sectional view illustrated in the
drawings. In addition, a horizontal cross section refers to a case
taken along a plane in the horizontal direction, and an example
thereof may be a plan view illustrated in the drawings.
[0030] Terms used herein are used only in order to describe an
exemplary embodiment rather than limiting the present disclosure.
In this case, singular forms include plural forms unless
interpreted otherwise in a context.
[0031] Electronic Device
[0032] FIG. 1 is a schematic block diagram illustrating an example
of an electronic device system.
[0033] Referring to FIG. 1, an electronic device 1000 may
accommodate amain board 1010 therein. The main board 1010 may
include chip related components 1020, network related components
1030, other components 1040, and the like, physically or
electrically connected thereto. These components may be connected
to others to be described below to form various signal lines
1090.
[0034] The chip related components 1020 may include a memory chip
such as a volatile memory (for example, a dynamic random access
memory (DRAM)), a non-volatile memory (for example, a read only
memory (ROM)), a flash memory, or the like; an application
processor chip such as a central processor (for example, a central
processing unit (CPU)), a graphics processor (for example, a
graphics processing unit (GPU)), a digital signal processor, a
cryptographic processor, a microprocessor, a microcontroller, or
the like; and a logic chip such as an analog-to-digital (ADC)
converter, an application-specific integrated circuit (ASIC), or
the like. However, the chip related components 1020 are not limited
thereto, but may also include other types of chip related
components. In addition, the chip related components 1020 may be
combined with each other.
[0035] The network related components 1030 may include protocols
such as wireless fidelity (Wi-Fi) (Institute of Electrical And
Electronics Engineers (IEEE) 802.11 family, or the like), worldwide
interoperability for microwave access (WiMAX) (IEEE 802.16 family,
or the like), IEEE 802.20, long term evolution (LTE), evolution
data only (Ev-DO), high speed packet access+(HSPA+), high speed
downlink packet access+(HSDPA+), high speed uplink packet
access+(HSUPA+), enhanced data GSM environment (EDGE), global
system for mobile communications (GSM), global positioning system
(GPS), general packet radio service (GPRS), code division multiple
access (CDMA), time division multiple access (TDMA), digital
enhanced cordless telecommunications (DECT), Bluetooth, 3G, 4G, and
5G protocols, and any other wireless and wired protocols designated
after the abovementioned protocols. However, the network related
components 1030 are not limited thereto, but may also include a
variety of other wireless or wired standards or protocols. In
addition, the network related components 1030 may be combined with
each other, together with the chip related components 1020
described above.
[0036] Other components 1040 may include a high frequency inductor,
a ferrite inductor, a power inductor, ferrite beads, a low
temperature co-fired ceramic (LTCC), an electromagnetic
interference (EMI) filter, a multilayer ceramic capacitor (MLCC),
or the like. However, other components 1040 are not limited
thereto, but may also include passive components used for various
other purposes, or the like. In addition, other components 1040 may
be combined with each other, together with the chip related
components 1020 or the network related components 1030 described
above.
[0037] Depending on a type of the electronic device 1000, the
electronic device 1000 may include other components that may or may
not be physically or electrically connected to the main board 1010.
These other components may include, for example, a camera module
1050, an antenna 1060, a display device 1070, a battery 1080, an
audio codec (not illustrated), a video codec (not illustrated), a
power amplifier (not illustrated), a compass (not illustrated), an
accelerometer (not illustrated), a gyroscope (not illustrated), a
speaker (not illustrated), a mass storage unit (for example, a hard
disk drive) (not illustrated), a compact disk (CD) drive (not
illustrated), a digital versatile disk (DVD) drive (not
illustrated), or the like. However, these other components are not
limited thereto, but may also include other components used for
various purposes depending on a type of electronic device 1000, or
the like.
[0038] The electronic device 1000 may be a smartphone, a personal
digital assistant (PDA), a digital video camera, a digital still
camera, a network system, a computer, a monitor, a tablet PC, a
laptop PC, a netbook PC, a television, a video game machine, a
smartwatch, an automotive component, or the like. However, the
electronic device 1000 is not limited thereto, and may be any other
electronic device processing data.
[0039] FIG. 2 is a schematic perspective view illustrating an
example of an electronic device.
[0040] Referring to FIG. 2, a semiconductor package may be used for
various purposes in the various electronic devices 1000 as
described above. For example, a main board 1110 may be accommodated
in a body 1101 of a smartphone 1100, and various electronic
components 1120 may be physically or electrically connected to the
main board 1110. In addition, other components that may or may not
be physically or electrically connected to the main board 1110,
such as the camera module 1130, may be accommodated in the body
1101. Some of the electronic components 1120 may be the chip
related components, and the semiconductor package 100 may be, for
example, an application processor among the chip related
components, but is not limited thereto. The electronic device is
not necessarily limited to the smartphone 1100, but may be other
electronic devices as described above.
[0041] Semiconductor Package
[0042] Generally, numerous fine electrical circuits are integrated
in a semiconductor chip. However, the semiconductor chip may not
serve as a finished semiconductor product in itself, and may be
damaged due to external physical or chemical impacts. Therefore,
the semiconductor chip itself may not be used, but may be packaged
and used in an electronic device, or the like, in a packaged
state.
[0043] Here, semiconductor packaging is required due to the
existence of a difference in a circuit width between the
semiconductor chip and a main board of the electronic device in
terms of electrical connections. In detail, a size of connection
pads of the semiconductor chip and an interval between the
connection pads of the semiconductor chip are very fine, but a size
of component mounting pads of the main board used in the electronic
device and an interval between the component mounting pads of the
main board are significantly larger than those of the semiconductor
chip. Therefore, it may be difficult to directly mount the
semiconductor chip on the main board, and packaging technology for
buffering a difference in a circuit width between the semiconductor
chip and the main board is required.
[0044] A semiconductor package manufactured by the packaging
technology may be classified as a fan-in semiconductor package or a
fan-out semiconductor package depending on a structure and a
purpose thereof.
[0045] The fan-in semiconductor package and the fan-out
semiconductor package will hereinafter be described in more detail
with reference to the drawings.
[0046] Fan-In Semiconductor Package
[0047] FIGS. 3A and 3B are schematic cross-sectional views
illustrating states of a fan-in semiconductor package before and
after being packaged.
[0048] FIG. 4 is schematic cross-sectional views illustrating a
packaging process of a fan-in semiconductor package.
[0049] Referring to the drawings, a semiconductor chip 2220 may be,
for example, an integrated circuit (IC) in a bare state, including
a body 2221 including silicon (Si), germanium (Ge), gallium
arsenide (GaAs), or the like, connection pads 2222 formed on one
surface of the body 2221 and including a conductive material such
as aluminum (Al), or the like, and a passivation layer 2223 such as
an oxide film, a nitride film, or the like, formed on one surface
of the body 2221 and covering at least portions of the connection
pads 2222. In this case, since the connection pads 2222 are
significantly small, it is difficult to mount the integrated
circuit (IC) on an intermediate level printed circuit board (PCB)
as well as on the main board of the electronic device, or the
like.
[0050] Therefore, an interconnection member 2240 may be formed
depending on a size of the semiconductor chip 2220 on the
semiconductor chip 2220 in order to redistribute the connection
pads 2222. The interconnection member 2240 may be formed by forming
an insulating layer 2241 on the semiconductor chip 2220 using an
insulating material such as a photoimagable dielectric (PID) resin,
forming via holes 2243h opening the connection pads 2222, and then
forming wiring patterns 2242 and vias 2243. Then, a passivation
layer 2250 protecting the interconnection member 2240 may be
formed, an opening 2251 may be formed, and an under-bump metal
layer 2260, or the like, may be formed. That is, a fan-in
semiconductor package 2200 including, for example, the
semiconductor chip 2220, the interconnection member 2240, the
passivation layer 2250, and the under-bump metal layer 2260 may be
manufactured through a series of processes.
[0051] As described above, the fan-in semiconductor package may
have a package form in which all of the connection pads, for
example, input/output (I/O) terminals, of the semiconductor chip
are disposed inside the semiconductor chip, and may have excellent
electrical characteristics and be produced at a low cost.
Therefore, many elements mounted in smartphones have been
manufactured in a fan-in semiconductor package form. In detail,
many elements mounted in smartphones have been developed to
implement a rapid signal transfer while having a compact size.
[0052] However, since all I/O terminals need to be disposed inside
the semiconductor chip in the fan-in semiconductor package, the
fan-in semiconductor package has a large spatial limitation.
Therefore, it is difficult to apply this structure to a
semiconductor chip having a large number of I/O terminals or a
semiconductor chip having a compact size. In addition, due to the
disadvantage described above, the fan-in semiconductor package may
not be directly mounted and used on the main board of the
electronic device. The reason is that even in the case that a size
of the I/O terminals of the semiconductor chip and an interval
between the I/O terminals of the semiconductor chip are increased
by a redistribution process, the size of the I/O terminals of the
semiconductor chip and the interval between the I/O terminals of
the semiconductor chip may not be sufficient to directly mount the
fan-in semiconductor package on the main board of the electronic
device.
[0053] FIG. 5 is a schematic cross-sectional view illustrating a
case in which a fan-in semiconductor package is mounted on an
interposer substrate and is finally mounted on a main board of an
electronic device.
[0054] FIG. 6 is a schematic cross-sectional view illustrating a
case in which a fan-in semiconductor package is embedded in an
interposer substrate and is finally mounted on a main board of an
electronic device.
[0055] Referring to the drawings, in a fan-in semiconductor package
2200, connection pads 2222, that is, I/O terminals, of a
semiconductor chip 2220 may be redistributed through an interposer
substrate 2301, and the fan-in semiconductor package 2200 may be
finally mounted on a main board 2500 of an electronic device in a
state in which it is mounted on the interposer substrate 2301. In
this case, solder balls 2270, and the like, may be fixed by an
underfill resin 2280, or the like, and an outer side of the
semiconductor chip 2220 may be covered with a molding material
2290, or the like. Alternatively, a fan-in semiconductor package
2200 may be embedded in a separate interposer substrate 2302,
connection pads 2222, that is, I/O terminals, of the semiconductor
chip 2220 may be redistributed by the interposer substrate 2302 in
a state in which the fan-in semiconductor package 2200 is embedded
in the interposer substrate 2302, and the fan-in semiconductor
package 2200 may be finally mounted on a main board 2500 of an
electronic device.
[0056] As described above, it may be difficult to directly mount
and use the fan-in semiconductor package on the main board of the
electronic device. Therefore, the fan-in semiconductor package may
be mounted on the separate interposer substrate and be then mounted
on the main board of the electronic device through a packaging
process or may be mounted and used on the main board of the
electronic device in a state in which it is embedded in the
interposer substrate.
[0057] Fan-Out Semiconductor Package
[0058] FIG. 7 is a schematic cross-sectional view illustrating a
fan-out semiconductor package.
[0059] Referring to the drawing, in a fan-out semiconductor package
2100, for example, an outer side of a semiconductor chip 2120 may
be protected by an encapsulant 2130, and connection pads 2122 of
the semiconductor chip 2120 may be redistributed outwardly of the
semiconductor chip 2120 by an interconnection member 2140. In this
case, a passivation layer 2150 may be further formed on the
interconnection member 2140, and an under-bump metal layer 2160 may
be further formed in openings of the passivation layer 2150. Solder
balls 2170 may be further formed on the under-bump metal layer
2160. The semiconductor chip 2120 may be an integrated circuit (IC)
including a body 2121, the connection pads 2122, a passivation
layer (not illustrated), and the like. The interconnection member
2140 may include an insulating layer 2141, redistribution layers
2142 formed on the insulating layer 2141, and vias 2143
electrically connecting the connection pads 2122 and the
redistribution layers 2142 to each other.
[0060] As described above, the fan-out semiconductor package may
have a form in which I/O terminals of the semiconductor chip are
redistributed and disposed outwardly of the semiconductor chip
through the interconnection member formed on the semiconductor
chip. As described above, in the fan-in semiconductor package, all
I/O terminals of the semiconductor chip need to be disposed inside
the semiconductor chip. Therefore, when a size of the semiconductor
chip is decreased, a size and a pitch of balls need to be
decreased, such that a standardized ball layout may not be used in
the fan-in semiconductor package. On the other hand, the fan-out
semiconductor package has the form in which the I/O terminals of
the semiconductor chip are redistributed and disposed outwardly of
the semiconductor chip through the interconnection member formed on
the semiconductor chip as described above. Therefore, even in the
case that a size of the semiconductor chip is decreased, a
standardized ball layout may be used in the fan-out semiconductor
package as it is, such that the fan-out semiconductor package may
be mounted on the main board of the electronic device without using
a separate interposer substrate, as described below.
[0061] FIG. 8 is a schematic cross-sectional view illustrating a
case in which a fan-out semiconductor package is mounted on a main
board of an electronic device.
[0062] Referring to the drawing, a fan-out semiconductor package
2100 may be mounted on a main board 2500 of an electronic device
through solder balls 2170, or the like. That is, as described
above, the fan-out semiconductor package 2100 includes the
interconnection member 2140 formed on the semiconductor chip 2120
and capable of redistributing the connection pads 2122 to a fan-out
region that is outside of a size of the semiconductor chip 2120,
such that the standardized ball layout may be used in the fan-out
semiconductor package 2100 as it is. As a result, the fan-out
semiconductor package 2100 may be mounted on the main board 2500 of
the electronic device without using a separate interposer
substrate, or the like.
[0063] As described above, since the fan-out semiconductor package
may be mounted on the main board of the electronic device without
using the separate interposer substrate, the fan-out semiconductor
package may be implemented at a thickness lower than that of the
fan-in semiconductor package using the interposer substrate.
Therefore, the fan-out semiconductor package may be miniaturized
and thinned. In addition, the fan-out semiconductor package has
excellent thermal characteristics and electrical characteristics,
such that it is particularly appropriate for a mobile product.
Therefore, the fan-out semiconductor package may be implemented in
a form more compact than that of a general package-on-package (POP)
type using a printed circuit board (PCB), and may solve a problem
due to occurrence of a warpage phenomenon.
[0064] Meanwhile, the fan-out semiconductor package refers to
package technology for mounting the semiconductor chip on the main
board of the electronic device, or the like, as described above,
and protecting the semiconductor chip from external impacts, and is
a concept different from that of a printed circuit board (PCB) such
as an interposer substrate, or the like, having a scale, a purpose,
and the like, different from those of the fan-out semiconductor
package, and having the fan-in semiconductor package embedded
therein.
[0065] A fan-out semiconductor package in which sufficient close
adhesion of an under-bump metal layer may be secured will
hereinafter be described with reference to the drawings.
[0066] FIG. 9 is a schematic cross-sectional view illustrating an
example of a fan-out semiconductor package.
[0067] FIG. 10 is a schematic plan view taken along line I-I' of
the fan-out semiconductor package of FIG. 9.
[0068] FIGS. 11A and 11B are schematic enlarged views illustrating
region A of the fan-out semiconductor package of FIG. 9.
[0069] Referring to the drawings, the fan-out semiconductor package
100A according to an exemplary embodiment in the present disclosure
may include a first interconnection member 110 having a
through-hole 110H, a semiconductor chip 120 disposed in the
through-hole 110H of the first interconnection member 110 and
having an active surface having connection pads 122 disposed
thereon and an inactive surface opposing the active surface, an
encapsulant 130 encapsulating at least portions of the first
interconnection member 110 and the inactive surface of the
semiconductor chip 120, a second interconnection member 140
disposed on the first interconnection member 110 and the active
surface of the semiconductor chip 120 and including redistribution
layers 142a and 142b electrically connected to the connection pads
122, a passivation layer 202 disposed on the second interconnection
member 140 and having openings 202H exposing at least portions of
the redistribution layer 142b of the second interconnection member
140, an under-bump metal layer 160 disposed on the passivation
layer 202 and filling at least portions of the openings 202H, and
connection terminals 170 disposed on the under-bump metal layer 160
and electrically connected to the connection pads 122. The
under-bump metal layer 160 may include a first conductor layer 303
formed on a surface of the passivation layer 202, a second
conductor layer 161 formed on the exposed redistribution layer 142b
of the second interconnection member 140, walls of the openings
202H, and the first conductor layer 303, and a third conductor
layer 162 formed on the second conductor layer 161. That is, in the
under-bump metal layer 160, the number of conductor layers 303,
161, and 162 formed on the surface of the passivation layer 202 may
be different from that of conductor layers 161 and 162 formed on
the exposed redistribution layer 142b of the second interconnection
member 140 and the walls of the openings 202H. The number of
conductor layers 303, 161, and 162 formed on the surface of the
passivation layer 202 may be larger than that of conductor layers
161 and 162 formed on the exposed redistribution layer 142b of the
second interconnection member 140 and the walls of the openings
202H.
[0070] In this case, when the first conductor layer 303 formed on
the surface of the passivation layer 202 and surrounding edges of
the openings 202H is disposed as in the fan-out semiconductor
package 100A according to the exemplary embodiment, the under-bump
metal layer 160 may be formed using the first conductor layer 303
as a basic seed layer. In this case, the passivation layer 202 and
the first conductor layer 303 may have sufficient close adhesion
therebetween by self-assembly, or the like, as described below.
Therefore, the under-bump metal layer 160 formed using the first
conductor layer 303 as the seed layer may also secure sufficient
close adhesion.
[0071] Meanwhile, in the fan-out semiconductor package 100A
according to the exemplary embodiment, an outermost layer circuit
such as the under-bump metal layer 160, or the like, may be formed
on the surface of the passivation layer 202 using a laminate to
which the first conductor layer 303 is attached. In this case, the
first conductor layer 303 before being patterned may serve as a
protection layer to thus suppress several side effects that may
ensue in a circuit forming process, for example, generation of a
stain on a surface of the outermost layer, difficulty in
implementing a fine circuit due to a high surface roughness, and
the like. In addition, the circuit of the outermost layer such as
the under-bump metal layer formed using laminate may be beneficial
to a process when the connection terminals 170 such as solder balls
are formed. In addition, as described below, the laminate may be
applied to both surfaces of the outermost layer in a process of
manufacturing a fan-out semiconductor package. Therefore, a warpage
problem, or the like, that may occur in the process of
manufacturing a fan-out semiconductor package may be
suppressed.
[0072] The respective components included in the fan-out
semiconductor package 100A according to the exemplary embodiment
will hereinafter be described below in more detail.
[0073] The first interconnection member 110 may include
redistribution layers 112a and 112c redistributing the connection
pads 122 of the semiconductor chip 120 to thus reduce the number of
layers of the second interconnection member 140. If necessary, the
first interconnection member 110 may maintain rigidity of the
fan-out semiconductor package 100A depending on certain materials,
and serve to secure uniformity of a thickness of the encapsulant
130. In some cases, due to the first interconnection member 110,
the fan-out semiconductor package 100A according to the exemplary
embodiment may be used as a portion of a package-on-package. The
first interconnection member 110 may have the through-hole 110H.
The through-hole 110H may have the semiconductor chip 120 disposed
therein to be spaced apart from the first interconnection member
110 by a predetermined distance. Side surfaces of the semiconductor
chip 120 may be surrounded by the first interconnection member 110.
However, such a form is only an example and may be variously
modified to have other forms, and the fan-out semiconductor package
100A may perform another function depending on such a form.
[0074] The first interconnection member 110 may include an
insulating layer 111 in contact with the second interconnection
member 140, a first redistribution layer 112a in contact with the
second interconnection member 140 and embedded in the insulating
layer 111, and a second redistribution layer 112c disposed on the
other surface of the insulating layer 111 opposing one surface of
the insulating layer 111 in which the first redistribution layer
112a is embedded. The first interconnection member 110 may include
vias 113 penetrating through the insulating layer 111 and
electrically connecting the first and second redistribution layers
112a and 112c to each other. The first and second redistribution
layers 112a and 112c may be electrically connected to the
connection pads 122. When the first redistribution layer 112a is
embedded in the insulating layer 111, a step portion generated due
to a thickness of the first redistribution layer 112a may be
significantly reduced, and an insulating distance of the second
interconnection member 140 may thus become constant. That is, a
difference between a distance from the redistribution layer 142a of
the second interconnection member 140 to a lower surface of the
insulating layer 111 and a distance from the redistribution layer
142a of the second interconnection member 140 to the connection
pads 122 may be smaller than a thickness of the first
redistribution layer 112a. Therefore, a high density wiring design
of the second interconnection member 140 may be easy.
[0075] A material of the insulating layer 111 is not particularly
limited. For example, an insulating material may be used as a
material of the insulating layer 111. In this case, the insulating
material may be a thermosetting resin such as an epoxy resin, a
thermoplastic resin such as a polyimide resin, a resin in which the
thermosetting resin or the thermoplastic resin is impregnated
together with an inorganic filler in a core material such as a
glass cloth (or a glass fabric), for example, prepreg, Ajinomoto
Build up Film (ABF), FR-4, Bismaleimide Triazine (BT), or the like.
Alternatively, a photoimagable dielectric (PID) resin may also be
used as the insulating material.
[0076] The redistribution layers 112a and 112c may serve to
redistribute the connection pads 122 of the semiconductor chip 120.
A material of each of the redistribution layers 112a and 112c may
be a conductive material such as copper (Cu), aluminum (Al), silver
(Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti),
or alloys thereof. The redistribution layers 112a and 112c may
perform various functions depending on designs of their
corresponding layers. For example, the redistribution layers 112a
and 112c may include a ground (GND) pattern, a power (PWR) pattern,
a signal (S) pattern, and the like. Here, the signal (S) pattern
may include various signals except for the ground (GND) pattern,
the power (PWR) pattern, and the like, such as data signals, and
the like. In addition, the redistribution layers 112a and 112c may
include a via pad, a connection terminal pad, and the like. As a
non-restrictive example, both of the redistribution layers 112a and
112c may include a ground pattern. In this case, the number of
ground patterns formed on the redistribution layers 142a and 142b
of the second interconnection member 140 may be significantly
reduced, such that a degree of wiring design freedom may be
improved.
[0077] Surface treatment layers (not illustrated) may be further
formed on portions of the redistribution layer 112c exposed through
openings 131 formed in the encapsulant 130, if necessary. The
surface treatment layers (not illustrated) are not particularly
limited as long as they are known in the related art, and may be
formed by, for example, electrolytic gold plating, electroless gold
plating, organic solderability preservative (OSP) or electroless
tin plating, electroless silver plating, electroless nickel
plating/substituted gold plating, direct immersion gold (DIG)
plating, hot air solder leveling (HASL), or the like.
[0078] The vias 113 may electrically connect the redistribution
layers 112a and 112c formed on different layers to each other,
resulting in an electrical path in the first interconnection member
110. Each of the vias 113 may also be formed of a conductive
material. Each of the vias 113 may be completely filled with the
conductive material, as illustrated in FIG. 10, or the conductive
material may also be formed along a wall of each of the vias 113.
In addition, each of the vias 113 may have all shapes known in the
related art, such as a tapered shape, a cylindrical shape, and the
like. Meanwhile, as seen from a process to be described below, when
holes for the vias 113 are formed, some of the pads of the first
redistribution layer 112a may serve as a stopper, and it may be
thus advantageous in a process that each of the vias 113 has the
tapered shape of which a width of an upper surface is greater than
that of a lower surface. In this case, the vias 113 may be
integrated with portions of the second redistribution layer
112c.
[0079] The semiconductor chip 120 may be an integrated circuit (IC)
provided in an amount of several hundreds to several millions of
elements or more integrated in a single chip. The IC may be, for
example, an application processor chip such as a central processor
(for example, a CPU), a graphics processor (for example, a GPU), a
digital signal processor, a cryptographic processor, a
microprocessor, a microcontroller, or the like, but is not limited
thereto. The semiconductor chip 120 may be formed on the basis of
an active wafer. In this case, a base material of a body 121 may be
silicon (Si), germanium (Ge), gallium arsenide (GaAs), or the like.
Various circuits may be formed on the body 121. The connection pads
122 may electrically connect the semiconductor chip 120 to other
components. A material of the connection pads 122 may be a
conductive material such as aluminum (Al), or the like. A
passivation layer 123 exposing the connection pads 122 may be
formed on the body 121, and may be an oxide film, a nitride film,
or the like, or a double layer of an oxide layer and a nitride
layer. A lower surface of the connection pads 122 may have a step
portion with respect to a lower surface of the encapsulant 130
through the passivation layer 123. Resultantly, a phenomenon in
which the encapsulant 130 bleeds into the lower surface of the
connection pads 122 may be prevented to some extent. An insulating
layer (not illustrated), and the like, may also be further disposed
in other required positions.
[0080] The inactive surface of the semiconductor chip 120 may be
disposed on a level below an upper surface of the second
redistribution layer 112c of the first interconnection member 110.
For example, the inactive surface of the semiconductor chip 120 may
be disposed on a level below an upper surface of the insulating
layer 111 of the first interconnection member 110. A height
difference between the inactive surface of the semiconductor chip
120 and the upper surface of the second redistribution layer 112c
of the first interconnection member 110 may be 2 .mu.m or more, for
example, 5 .mu.m or more. In this case, generation of cracks in
corners of the inactive surface of the semiconductor chip 120 may
be effectively prevented. In addition, a deviation of an insulating
distance on the inactive surface of the semiconductor chip 120 in a
case in which the encapsulant 130 is used may be significantly
reduced.
[0081] The encapsulant 130 may protect the first interconnection
member 110 and/or the semiconductor chip 120. An encapsulation form
of the encapsulant 130 is not particularly limited, but may be a
form in which the encapsulant 130 surrounds at least portions of
the first interconnection member 110 and/or the semiconductor chip
120. For example, the encapsulant 130 may cover the first
interconnection member 110 and the inactive surface of the
semiconductor chip 120, and fill spaces between walls of the
through-hole 110H and the side surfaces of the semiconductor chip
120. In addition, the encapsulant 130 may also fill at least a
portion of a space between the passivation layer 123 of the
semiconductor chip 120 and the second interconnection member 140.
Meanwhile, the encapsulant 130 may fill the through-hole 110H to
thus serve as an adhesive and reduce buckling of the semiconductor
chip 120 depending on certain materials.
[0082] The certain materials of the encapsulant 130 are not
particularly limited. For example, an insulating material may be
used as the certain materials of the encapsulant 130. In this case,
the insulating material may be a thermosetting resin such as an
epoxy resin, a thermoplastic resin such as a polyimide resin, a
resin having a reinforcing material such as an inorganic filler
impregnated in the thermosetting resin and the thermoplastic resin,
such as ABF, FR-4, BT, a PID resin, or the like. In addition, the
known molding material such as an EMC, or the like, may also be
used. Alternatively, a resin in which a thermosetting resin or a
thermoplastic resin is impregnated together with an inorganic
filler in a core material such as a glass cloth (or a glass fabric)
may also be used as the insulating material.
[0083] The encapsulant 130 may include a plurality of layers formed
of a plurality of materials. For example, a space within the
through-hole 110H may be filled with a first encapsulant, and the
first interconnection member 110 and the semiconductor chip 120 may
be covered with a second encapsulant. Alternatively, the first
encapsulant may cover the first interconnection member 110 and the
semiconductor chip 120 at a predetermined thickness while filling
the space within the through-hole 110H, and the second encapsulant
may again cover the first encapsulant at a predetermined thickness.
In addition to the form described above, various forms may be
used.
[0084] The encapsulant 130 may include conductive particles in
order to block electromagnetic waves, if necessary. For example,
the conductive particles may be any material that may block
electromagnetic waves, for example, copper (Cu), aluminum (Al),
silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium
(Ti), a solder, or the like. However, this is only an example, and
the conductive particles are not particularly limited thereto.
[0085] The second interconnection member 140 may be configured to
redistribute the connection pads 122 of the semiconductor chip 120.
Several tens to several hundreds of connection pads 122 having
various functions may be redistributed by the second
interconnection member 140, and may be physically or electrically
connected to an external source through connection terminals 170 to
be described below depending on the functions. The second
interconnection member 140 may include insulating layers 141a and
141b, the redistribution layers 142a and 142b disposed on the
insulating layers 141a and 141b, and vias 143a and 143b penetrating
through the insulating layers 141a and 141b and connecting the
redistribution layers 142a and 142b to each other. In the fan-out
semiconductor package 100A according to the exemplary embodiment,
the second interconnection member 140 may include a plurality of
redistribution layers 142a and 142b, but may also include a single
layer. In addition, the second interconnection member 140 may also
include different numbers of layers.
[0086] An insulating material may be used as a material of each of
the insulating layers 141a and 141b. In this case, a photosensitive
insulating material such as a photoimagable dielectric (PID) resin
may also be used as the insulating material. In this case, each of
the insulating layers 141a and 141b may be formed to have a smaller
thickness, and a fine pitch of each of the vias 143a and 143b may
be achieved more easily. Materials of the insulating layers 141a
and 141b may be the same as each other or may be different from
each other, if necessary. The insulating layers 141a and 141b may
be integrated with each other depending on processes, so that a
boundary therebetween may not be readily apparent.
[0087] The redistribution layers 142a and 142b may substantially
serve to redistribute the connection pads 122. A material of each
of the redistribution layers 142a and 142b may be a conductive
material such as copper (Cu), aluminum (Al), silver (Ag), tin (Sn),
gold (Au), nickel (Ni), lead (Pb), titanium (Ti), or alloys
thereof. The redistribution layers 142a and 142b may perform
various functions depending on designs of their corresponding
layers. For example, the redistribution layers 142a and 142b may
include a ground (GND) pattern, a power (PWR) pattern, a signal (S)
pattern, and the like. Here, the signal (S) pattern may include
various signals except for the ground (GND) pattern, the power
(PWR) pattern, and the like, such as data signals, and the like. In
addition, the redistribution layers 142a and 142b may include a via
pad, a connection terminal pad, and the like.
[0088] Surface treatment layers (not illustrated) may be further
formed on portions of the redistribution layer 142b exposed from
the redistribution layers 142a and 142b, if necessary. The surface
treatment layers (not illustrated) are not particularly limited as
long as they are known in the related art, and may be formed by,
for example, electrolytic gold plating, electroless gold plating,
OSP or electroless tin plating, electroless silver plating,
electroless nickel plating/substituted gold plating, DIG plating,
HASL, or the like.
[0089] The vias 143a and 143b may electrically connect the
redistribution layers 142a and 142b, the connection pads 122, or
the like, formed on different layers to each other, resulting in an
electrical path in the fan-out semiconductor package 100A. A
material of each of the vias 143a and 143b may be a conductive
material such as copper (Cu), aluminum (Al), silver (Ag), tin (Sn),
gold (Au), nickel (Ni), lead (Pb), titanium (Ti), or alloys
thereof. Each of the vias 143a and 143b may be completely filled
with the conductive material, or the conductive material may also
be formed along a wall of each of the vias 143a and 143b. In
addition, each of the vias 143a and 143b may have all shapes known
in the related art, such as a tapered shape, a cylindrical shape,
and the like.
[0090] Thicknesses of the redistribution layers 112a and 112c of
the first interconnection member 110 may be greater than those of
the redistribution layers 142a and 142b of the second
interconnection member 140. Since the first interconnection member
110 may have a thickness equal to or greater than that of the
semiconductor chip 120, the redistribution layers 112a and 112c
formed in the first interconnection member 110 may be formed to
have large sizes depending on a scale of the first interconnection
member 110. On the other hand, the redistribution layers 142a and
142b of the second interconnection member 140 may be formed at
sizes relatively smaller than those of the redistribution layers
112a and 112c of the first interconnection member 110 for thinness
of the second interconnection member 140.
[0091] The passivation layer 202 may be configured to protect the
second interconnection member 140 from external physical or
chemical damage. The passivation layer 202 may have the openings
202H exposing at least portions of one 142b of redistribution
layers 142a and 142b of the second interconnection member 140. Each
of the openings 202H may expose the entirety or only a portion of a
surface of the redistribution layer 142b. In some cases, each of
the openings 202H may expose a side surface of the redistribution
layer 142b.
[0092] A material of the passivation layer 202 is not particularly
limited, and may be, for example, a photosensitive insulating
material. Alternatively, a solder resist may also be used as the
material of the passivation layer 202. Alternatively, an insulating
resin that does not include a core material, but includes a filler,
for example, ABF including an inorganic filler and an epoxy resin,
or the like, may be used as the material of the passivation layer
202. A surface roughness of the passivation layer 202 may be lower
as compared to a general case. When the surface roughness is low as
described above, several side effects that may ensue in a circuit
forming process, for example, generation of a stain on a surface,
difficulty in implementing a fine circuit, and the like, may be
suppressed.
[0093] The under-bump metal layer 160 may be additionally
configured to improve connection reliability of the connection
terminals 170 to improve board level reliability. The under-bump
metal layer 160 may include the first conductor layer 303 formed on
the surface of the passivation layer 202, the second conductor
layer 161 formed on the redistribution layer 142b exposed through
the openings 202H, the walls of the openings 202H, and the first
conductor 303, and the third conductor layer 162 formed on the
second conductor layer 161.
[0094] The first conductor layer 303 and the passivation layer 202
may form self-assembly therebetween, as described below, to thus
have sufficient close adhesion therebetween. The first conductor
layer 303 may be used as the basic seed layer for forming the
under-bump metal layer 160. Therefore, the under-bump metal layer
160 may also have sufficient close adhesion. The first conductor
layer 303 may serve as a protection layer of the outermost layer of
the fan-out semiconductor package, before being patterned, to thus
suppress several side effects that may ensue in a circuit forming
process, for example, generation of a stain on a surface of the
outermost layer, difficulty in implementing a fine circuit, and the
like. The first conductor layer 303 may include the known
conductive material, preferably, copper (Cu) such as electrolytic
copper.
[0095] The second conductor layer 161 may serve as a seed layer,
and the third conductor layer 162 may substantially serve as the
under-bump metal layer 160. The second and third conductor layers
161 and 162 may include the known conductive materials, preferably,
electroless copper and electrolytic copper, respectively. In a case
in which the first conductor layer 303 includes electrolytic
copper, the second conductor layer 161 includes electroless copper,
and the third conductor layer 162 includes electrolytic copper, the
first conductor layer 303, the second conductor layer 161, and the
third conductor layer 162 are distinguishable layers, since any
immediately adjacent layers thereof are formed by different
processes. The second conductor layer 161 may serve as the seed
layer to thus have a very thin thickness. That is, the second
conductor layer 161 may have a thickness lower than thicknesses of
the first conductor layer 303 and the third conductor layer 162. A
thickness of the third conductor layer 162 may be thicker than that
of the first conductor layer 303, and a thickness of the first
conductor layer 303 may be thicker than that of the second
conductor layer 161. That is, the thickness of the third conductor
layer 162 may be thickest, and the thickness of the second
conductor layer 161 may be thinnest. However, the thicknesses of
the first to third conductor layers are not necessarily limited
thereto.
[0096] The connection terminals 170 may be additionally configured
to physically or electrically externally connect the fan-out
semiconductor package 100A. For example, the fan-out semiconductor
package 100A may be mounted on the main board of the electronic
device through the connection terminals 170. Each of the connection
terminals 170 may be formed of a conductive material, for example,
a solder, or the like. However, this is only an example, and a
material of each of the connection terminals 170 is not
particularly limited thereto. Each of the connection terminals 170
may be a land, a ball, a pin, or the like. The connection terminals
170 may be formed as a multilayer or single layer structure. When
the connection terminals 170 are formed as a multilayer structure,
the connection terminals 170 may include a copper pillar and a
solder. When the connection terminals 170 are formed as a single
layer structure, the connection terminals 170 may include a
tin-silver solder or copper. However, this is only an example, and
the connection terminals 170 are not limited thereto. The number,
an interval, a disposition, or the like, of the connection
terminals 170 is not particularly limited, and may be sufficiently
modified by a person skilled in the art depending on design
particulars. For example, the connection terminals 170 may be
provided in an amount of several tens to several thousands
according to the number of connection pads 122 of the semiconductor
chip 120, but are not limited thereto, and may also be provided in
an amount of several tens to several thousands or more or several
tens to several thousands or less.
[0097] At least one of the connection terminals 170 may be disposed
in a fan-out region. The fan-out region is a region except for the
region in which the semiconductor chip 120 is disposed. That is,
the fan-out semiconductor package 100A according to the exemplary
embodiment may be a fan-out package. The fan-out package may have
excellent reliability as compared to a fan-in package, may
implement a plurality of input/output (I/O) terminals, and may
facilitate a 3D interconnection. In addition, as compared to a ball
grid array (BGA) package, a land grid array (LGA) package, or the
like, the fan-out package may be mounted on an electronic device
without a separate board. Thus, the fan-out package may be
manufactured to have a small thickness, and may have price
competitiveness.
[0098] Although not illustrated in the drawings, a metal layer may
be further disposed on an inner wall of the through-hole 110H of
the first interconnection member 110, if necessary. That is, the
side surfaces of the semiconductor chip 120 may also be surrounded
by the metal layer. Heat generated by the semiconductor chip 120
may be effectively radiated in an upward or downward direction of
the fan-out semiconductor package 100A through the metal layer, and
electromagnetic waves may be effectively blocked through the metal
layer. In addition, if necessary, a plurality of semiconductor
chips may be disposed in the through-hole 110H of the first
interconnection member 110, and the number of through-holes 110H of
the first interconnection member 110 may be plural and
semiconductor chips may be disposed in the through-holes,
respectively. In addition, separate passive components such as a
condenser, an inductor, and the like, may be disposed together with
the semiconductor chip in the through-hole 110H. In addition, a
surface mounted component may be mounted on the passivation layer
202.
[0099] FIGS. 12A through 12G are schematic views illustrating an
example of processes of manufacturing the fan-out semiconductor
package of FIG. 9.
[0100] Referring to FIG. 12A, a detachable film 401 may be first
prepared. The detachable film 401 may have metal layers 402 and 403
formed on one surface or both surfaces thereof. Surface treatment
may be performed on a bonded surface between the metal layers 402
and 403 in order to facilitate separation in the subsequent
separating process. Alternatively, a release layer may be provided
between the metal layers 402 and 403 to facilitate separation in
the subsequent process. The detachable film 401 may be the known
insulating substrate, and a material of the detachable film 401 may
be any material. The metal layers 402 and 403 may be generally
copper (Cu) foils, but are not limited thereto. That is, the metal
layers 402 and 403 may be thin films formed of other conductive
materials. Next, patterning for forming the first redistribution
layer 112a may be performed using a dry film 404. The first
redistribution layer 112a may be formed using the known
photolithography method. The dry film 404 may be the known dry film
formed of a photosensitive material. Next, a conductive material
may fill a patterned space of the dry film 404 to form the first
redistribution layer 112a. The first redistribution layer 112a may
be formed using a plating process. In this case, the metal film 403
may serve as a seed layer. As the plating process, an
electroplating, an electroless plating, or the like, may be used. A
plating method may be chemical vapor deposition (CVD), physical
vapor deposition (PVD), sputtering, a subtractive process, an
additive process, a semi-additive process (SAP), a modified
semi-additive process (MSAP), or the like, but is not limited
thereto. Next, the dry film 404 may be removed. The dry film 404
may be removed by a known method such as an etching process, or the
like.
[0101] Referring to FIG. 12B, the insulating layer 111 embedding at
least a portion of the first redistribution layer 112a therein may
be formed on the metal layer 403. Then, the vias 113 penetrating
through the insulating layer 111 may be formed. In addition, the
second redistribution layer 112c may be formed on the insulating
layer 111. The insulating layer 111 may be formed by a method of
laminating a precursor of the insulating layer 111 by the known
lamination method and then hardening the precursor, a method of
applying a precursor of the insulating layer 111 by the known
application method and then hardening the precursor, or the like.
The vias 113 (shown in FIG. 10) and the second redistribution layer
112c may be formed by a method of forming via holes using
photolithography, mechanical drilling, laser drilling, or the like,
performing patterning using a dry film, or the like, and filling
the via holes and the patterned space by a plating process, or the
like. Next, the detachable film 401 may be peeled off. In this
case, the peel-off may indicate that the metal layers 402 and 403
are separated. Here, the metal layers 402 and 403 may be separated
using a blade, but are not limited thereto. That is, all known
methods may be used to separate the metal layers 402 and 403.
Meanwhile, an example in which the first interconnection member 110
before formation of the through-hole is formed before the
detachable film 401 is peeled off has been described in a series of
processes, but is not limited thereto. For example, the first
interconnection member 110 may also be formed after the detachable
film 401 is peeled off. That is, a sequence is not necessarily
limited to the abovementioned sequence.
[0102] Referring to FIG. 12C, the remaining metal layer 403 may be
removed by the known etching method, or the like. In this case, a
portion of the first redistribution layer 112a may be removed so
that the first redistribution layer 112a is recessed in an inward
direction of the insulating layer 111. In addition, the
through-hole 110H may be formed in the first interconnection member
110. The through-hole 110H may be formed using mechanical drilling
or laser drilling. However, the through-hole 110H is not limited to
being formed using the mechanical drilling or the laser drilling,
and may also be formed by a sandblasting method using particles for
polishing, a dry etching method using plasma, or the like. In a
case in which the through-hole 110H is formed using the mechanical
drilling or the laser drilling, a resin smear in the through-hole
110H may be removed by performing a desmearing process such as a
permanganate method, or the like. Next, an adhesive film 405 may be
attached to one surface of the first interconnection member 110. In
this case, when the first redistribution layer 112a is recessed,
one surface of the first redistribution layer 112a may have a step
portion with respect to one surface of the adhesive film 405. Any
material that may fix the insulating layer 111 may be used as the
adhesive film 405. As a non-restrictive example of this material, a
known tape, or the like, may be used. An example of a known tape
may include a thermosetting adhesive tape of which adhesion is
weakened by heat treatment, an ultraviolet-curable adhesive tape of
which adhesion is weakened by ultraviolet light irradiation, or the
like. In addition, the semiconductor chip 120 may be disposed in
the through-hole 110H of the insulating layer 111. For example, the
semiconductor chip 120 may be disposed by a method of attaching the
semiconductor chip 120 onto the adhesive film 405 in the
through-hole 110H. The semiconductor chip 120 may be disposed in a
face-down form so that the connection pads 122 are attached to the
adhesive film 405. If necessary, the connection pads 122 may be
attached to the adhesive film 405 so that one surface of the
connection pads 122 has a step portion in relation to an upper
surface of the adhesive film 405, that is, the connection pads 122
are recessed in an inward direction of the semiconductor chip 120
after the connection pads 122 are attached to the adhesive film
405.
[0103] Referring to FIG. 12D, at least portions of the first
interconnection member 110 and the semiconductor chip 120 may be
encapsulated using the encapsulant 130. The encapsulant 130 may
cover the first interconnection member 110 and the inactive surface
of the semiconductor chip 120, and may fill a space within the
through-hole 110H. The encapsulant 130 may be formed by a known
method. For example, the encapsulant 130 may be formed by a method
of laminating a resin for forming the encapsulant 130 in a
non-hardened state and then hardening the resin. Alternatively, the
encapsulant 130 may be formed by a method of applying a resin for
forming the encapsulant 130 in a non-hardened state on the adhesive
film 405 to encapsulate at least portions of the first
interconnection member and the semiconductor chip 120 and then
hardening the resin. The semiconductor chip 120 may be fixed by the
hardening. As the method of laminating the resin, for example, a
method of performing a hot press process of pressing the resin for
a predetermined time at a high temperature, decompressing the
resin, and then cooling the resin to room temperature, cooling the
resin in a cold press process, and then separating a work tool, or
the like, may be used. As the method of applying the resin, for
example, a screen printing method of applying ink with a squeegee,
a spray printing method of applying ink in a mist form, or the
like, may be used. In some cases, one surface of the encapsulant
130 after being hardened may also have a step in relation to one
surface of the first redistribution layer 112a and one surface of
the connection pads 122. Next, the adhesive film 405 may be peeled
off. A method of peeling the adhesive film 405 off is not
particularly limited, but may be a known method. For example, in a
case in which the thermosetting adhesive tape of which adhesion is
weakened by heat treatment, the ultraviolet-curable adhesive tape
of which adhesion is weakened by ultraviolet light irradiation, or
the like, is used as the adhesive film 405, the adhesive film 405
may be peeled off after the adhesion of the adhesive film 405 is
weakened by heat-treating the adhesive film 405 or may be peeled
off after the adhesion of the adhesive film 405 is weakened by
irradiating the adhesive film 405 with an ultraviolet ray. Next,
the second interconnection member 140 may be formed on the first
interconnection member 110 and the active surface of the
semiconductor chip 120 from which the adhesive film 405 is removed.
The second interconnection member 140 may be formed by sequentially
forming the insulating layers 141a and 141b and then forming the
redistribution layers 142a and 142b and the vias 143a and 143b on
and in the insulating layers 141a and 141b, respectively, by the
plating process as described above, or the like.
[0104] Referring to FIG. 12E, a passivation layer 202 and a
laminate 300 including a first conductor layer 303, a release layer
302, and a carrier film 301 sequentially stacked may be attached to
the second interconnection member 140 so that the passivation layer
202 is connected to the second interconnection member 140. In
addition, a passivation layer 202 and a laminate 300 including a
first conductor layer 303, a release layer 302, and a carrier film
301 sequentially stacked may be attached to the encapsulant 130 so
that the passivation layer 202 is connected to the encapsulant 130.
Meanwhile, in a case in which the first conductor layer 303 is
attached to a surface of the passivation layer 202 in a state of
the laminate as described above, self-assembly between the first
conductor layer 303 and the passivation layer 202 may be possible
as described below, such that the first conductor layer 303 and the
passivation layer 202 may have excellent close adhesion
therebetween. Next, the carrier film 301 may be removed from the
laminate attached to one surface of the second interconnection
member 140 and the laminate attached to the encapsulant 130. A
method of removing the carrier films 301 may be a known method, and
is not particularly limited.
[0105] Referring to FIG. 12F, in the laminate attached to the
second interconnection member 140, the openings 202H penetrating
through the passivation layer 202, the first conductor layer 303,
and the release layer 302 of the laminate and exposing at least
portions of the redistribution layer 142b of the second
interconnection member 140 may be formed. The opening 202H may be
formed using mechanical drilling or laser drilling. However, the
opening 202H is not limited to being formed using the mechanical
drilling or the laser drilling, and may also be formed by a
sandblasting method using particles for polishing, a dry etching
method using plasma, or the like. Next, the release layers 302 may
be removed from the laminate attached to the second interconnection
member 140 and the laminate attached to the encapsulant 130. The
release layers 302 may be removed by a desmearing process. In this
case, the first conductor layers 303 in the laminate attached to
the second interconnection member 140 and the laminate attached to
the encapsulant 130 may prevent both surfaces of the passivation
layer 202 from being damaged due to a desmearing solution. Next,
the second conductor layer 161 covering the redistribution layer
142b exposed through the openings 202H, the walls of the openings
202H, and the first conductor layer 303 may be formed. The second
conductor layer 161 may be formed using the first conductor layer
303 having the excellent close adhesion as described above as the
basic seed layer to thus have more excellent close adhesion. The
second conductor layer 161 may be formed by the known plating
process, for example, electroless plating such as sputtering, or
the like. Meanwhile, when the second conductor layer 161 is formed
on the second interconnection member 140, a similar conductor layer
(not illustrated) covering the first conductor layer 303 may also
be formed on the encapsulant 130. However, in some cases, the
conductor layer (not illustrated) may also not be formed on the
other surface.
[0106] Referring to FIG. 12G, the third conductor layer 162 may be
formed on the second conductor layer 161 on the second
interconnection member 140. In addition, the first conductor layer
303 and the second conductor layer 161 may be patterned. This
process may be performed by a subtractive method, an additive
method, a semi-additive method, a modified semi-additive method, or
the like, using a known method such as electroplating. Resultantly,
the under-bump metal layer 160 may be formed. Meanwhile, although
not illustrated, a third conductor layer (not illustrated) may be
formed on the encapsulant 130 when the third conductor layer 162 is
formed on the second interconnection member 140, and the first
conductor layer 303, the second conductor layer 161, and the third
conductor layer (not illustrated) formed on the encapsulant 130 may
be removed by the known etching method, or the like. In addition,
the openings 131 penetrating through the passivation layer 202
attached to the encapsulant 130 and exposing at least portions of
the redistribution layer 112c formed on the other surface of the
first interconnection member 110 may be formed. The openings 131
may be used as markings, or the like. In some cases, the openings
131 may be used as spaces in which connection terminals, surface
mounted components, or the like, are to be formed. In a case in
which the passivation layer 202 is attached to the encapsulant 130
as described above, the openings 131 may be more easily formed. In
addition, in a case in which the passivation layer 202 is attached
in an approximately symmetrical shape onto both sides of the
fan-out semiconductor package as described above, warpage generated
in a manufacturing process may be controlled. The passivation layer
202 attached to the encapsulant 130 may be removed as illustrated
in the drawing, but may also be used in a state in which the
passivation layer 202 is attached to the encapsulant 130, if
necessary. Next, the connection terminals 170 may be formed on the
under-bump metal layer 160 by a known method. A method of forming
the connection terminals 170 is not particularly limited. That is,
the connection terminals 170 may be formed by the method well-known
in the related art depending on a structure or a form thereof. The
connection terminals 170 may be fixed by reflow, and portions of
the connection terminals 170 may be embedded in the passivation
layer 202 in order to enhance fixing force, and the remaining
portions of the connection terminals 170 may be externally exposed,
whereby reliability may be improved.
[0107] Meanwhile, a series of processes may be processes of
preparing the detachable film 401 having a large size,
manufacturing a plurality of fan-out semiconductor packages 100A
through the abovementioned process, and then singulating the
plurality of fan-out semiconductor packages into individual fan-out
semiconductor packages 100A through cutting in order to facilitate
mass production. In this case, productivity may be excellent.
[0108] FIG. 13 is schematic views illustrating an example of a
process of manufacturing a laminate used in FIGS. 12A through
12G.
[0109] Referring to the drawing, a process of manufacturing the
laminate may include preparing a first laminate film 200 including
a release film 201 and a passivation layer 202 attached to the
release film 201, preparing a second laminate film 300 including a
carrier film 301 and a first conductor layer 303 attached to the
carrier film 301 through a release layer 302, and attaching the
first laminate film 200 and the second laminate film 300 to each
other so that the first conductor layer 303 is attached to a
surface of the passivation layer 202. The attaching of the first
and second laminate films 200 and 300 to each other may be
performed using the known rollers 501 and 502, but is not limited
thereto.
[0110] The release film 201 may be, for example, a
polyethyleneterephthalate (PET) film, and the passivation layer 202
may be, for example, ABF including the filler and the resin as
described above, but the release film 201 and the passivation layer
202 are not limited thereto. The carrier film 301 may be, for
example, a PET film, but is not limited thereto. The release layer
302 may be, for example, an alkaline-soluble resin layer, but is
not limited thereto. The first conductor layer 303 may be, for
example, an electrolytic copper layer, but is not limited
thereto.
[0111] FIG. 14 is a schematic view illustrating self-assembly
between a passivation layer and a metal layer.
[0112] Referring to the drawing, the passivation layer 202 may be
cured in a state in which the first conductor layer 303 is attached
to the surface of the passivation layer 202. In this case, when the
passivation layer 202 is cured, at least one of chemical reaction
groups 202P included in the insulating resin constituting the
passivation layer 202 may be self-assembled to metals 303P of the
first conductor layer 303 attached to the surface of the
passivation layer 202. Therefore, the passivation layer 202 and the
first conductor layer 303 may have excellent close adhesion
therebetween. In more detail, the chemical reaction groups 202P
included in the insulating resin of the passivation layer 202 may
become rich toward the surface of the passivation layer 202 to
which the first conductor layer 303 is attached in a curing
process, and may form coordination bonds or covalent bonds with the
metals 303P of the first conductor layer 303. Therefore, the
passivation layer 202 and the first conductor layer 303 may have
excellent close adhesion therebetween through the self-assembly by
the bonds described above. The chemical reaction groups 202P may be
coordinate compounds such as aromatic compounds having a long tail,
but are not limited thereto.
[0113] FIG. 15 is a schematic view illustrating a normal cured
state of a passivation layer.
[0114] Referring to the drawing, in a case in which a passivation
layer 202' is simply cured in a state in which it is attached to a
release film 201', chemical reaction groups 202'P included in a
resin of the passivation layer 202' may be randomly arranged, such
that excellent close adhesion through the self-assembly as
described above may not be implemented.
[0115] FIG. 16 is a schematic cross-sectional view illustrating
another example of a fan-out semiconductor package.
[0116] Referring to the drawing, in a fan-out semiconductor package
100B according to another exemplary embodiment in the present
disclosure, a first interconnection member 110 may include a first
insulating layer 111a in contact with a second interconnection
member 140, a first redistribution layer 112a in contact with the
second interconnection member 140 and embedded in the first
insulating layer 111a, a second redistribution layer 112b disposed
on the other surface of the first insulating layer 111a opposing
one surface of the first insulating layer 111a in which the first
redistribution layer 112a is embedded, a second insulating layer
111b disposed on the first insulating layer 111a and covering the
second redistribution layer 112b, and a third redistribution layer
112c disposed on the second insulating layer 111b. The first to
third redistribution layers 112a, 112b, and 112c may be
electrically connected to connection pads 122. Meanwhile, although
not illustrated in the drawing, the first and second redistribution
layers 112a and 112b and the second and third redistribution layers
112b and 112c may be electrically connected to each other through
first and second vias penetrating through the first and second
insulating layers 111a and 111b, respectively.
[0117] Since the first redistribution layer 112a is embedded, an
insulating distance of an insulating layer 141a of the second
interconnection member 140 may be substantially constant, as
described above. Since the first interconnection member 110 may
include a large number of redistribution layers 112a, 112b, and
112c, the second interconnection member 140 may be further
simplified. Therefore, a decrease in a yield depending on a defect
occurring in a process of forming the second interconnection member
140 may be suppressed. The first redistribution layer 112a may be
recessed into the first insulating layer 111a, such that a lower
surface of the first insulating layer 111a and a lower surface of
the first redistribution layer 112a have a step therebetween.
Resultantly, when an encapsulant 130 is formed, a phenomenon in
which a material of the encapsulant 130 bleeds to pollute the first
redistribution layer 112a may be prevented.
[0118] The lower surface of the first redistribution layer 112a of
the first interconnection member 110 may be disposed on a level
above a lower surface of the connection pads 122 of the
semiconductor chip 120. In addition, a distance between a
redistribution layer 142a of the second interconnection member 140
and the first redistribution layer 112a of the first
interconnection member 110 may be greater than that between the
redistribution layer 142a of the second interconnection member 140
and the connection pads 122 of the semiconductor chip 120. The
reason is that the first redistribution layer 112a may be recessed
into the insulating layer 111. The second redistribution layer 112b
of the first interconnection member 110 may be disposed on a level
between an active surface and an inactive surface of the
semiconductor chip 120. The first interconnection member 110 may be
formed at a thickness corresponding to that of the semiconductor
chip 120. Therefore, the second redistribution layer 112b formed in
the first interconnection member 110 may be disposed on a level
between the active surface and the inactive surface of the
semiconductor chip 120.
[0119] Thicknesses of the redistribution layers 112a, 112b, and
112c of the first interconnection member 110 may be greater than
those of the redistribution layers 142a and 142b of the second
interconnection member 140. Since the first interconnection member
110 may have a thickness equal to or greater than that of the
semiconductor chip 120, the redistribution layers 112a, 112b, and
112c may be formed to have large sizes depending on a scale of the
first interconnection member 110. On the other hand, the
redistribution layers 142a and 142b of the second interconnection
member 140 may be formed at a relatively small size for
thinness.
[0120] A description, or the like, of other configurations and a
manufacturing method except for the abovementioned configuration
overlaps that described above, and is thus omitted.
[0121] FIG. 17 is a schematic cross-sectional view illustrating
another example of a fan-out semiconductor package.
[0122] Referring to the drawing, in a fan-out semiconductor package
100C according to another exemplary embodiment in the present
disclosure, a first interconnection member 110 may include a first
insulating layer 111a, a first redistribution layer 112a and a
second redistribution layer 112b disposed on both surfaces of the
first insulating layer 111a, respectively, a second insulating
layer 111b disposed on the first insulating layer 111a and covering
the first redistribution layer 112a, a third redistribution layer
112c disposed on the second insulating layer 111b, a third
insulating layer 111c disposed on the first insulating layer 111a
and covering the second redistribution layer 112b, and a fourth
redistribution layer 112d disposed on the third insulating layer
111c. The first to fourth redistribution layers 112a, 112b, 112c,
and 112d may be electrically connected to connection pads 122.
Since the first interconnection member 110 may include a larger
number of redistribution layers 112a, 112b, 112c, and 112d, the
second interconnection member 140 may be further simplified.
Therefore, a decrease in a yield depending on a defect occurring in
a process of forming the second interconnection member 140 may be
suppressed. Meanwhile, although not illustrated in the drawing, the
first to fourth redistribution layers 112a, 112b, 112c, and 112d
may be electrically connected to each other through first to third
vias penetrating through the first to third insulating layers 111a,
111b, and 111c, respectively.
[0123] The first insulating layer 111a may have a thickness greater
than those of the second insulating layer 111b and the third
insulating layer 111c. The first insulating layer 111a may be
relatively thick in order to maintain rigidity, and the second
insulating layer 111b and the third insulating layer 111c may be
introduced in order to form a larger number of redistribution
layers 112c and 112d. The first insulating layer 111a may include
an insulating material different from those of the second
insulating layer 111b and the third insulating layer 111c. For
example, the first insulating layer 111a may be, for example,
prepreg including a core material, an inorganic filler, and an
insulating resin, and the second insulating layer 111b and the
third insulating layer 111c may be an ABF or a photosensitive
insulating film including an inorganic filler and an insulating
resin. However, the materials of the first insulating layer 111a
and the second and third insulating layers 111b and 111c are not
limited thereto.
[0124] A lower surface of the third redistribution layer 112c of
the first interconnection member 110 may be disposed on a level
below a lower surface of the connection pads 122 of the
semiconductor chip 120. In addition, a distance between a
redistribution layer 142a of the second interconnection member 140
and the third redistribution layer 112c of the first
interconnection member 110 may be smaller than that between the
redistribution layer 142a of the second interconnection member 140
and the connection pads 122 of the semiconductor chip 120. The
reason is that the third redistribution layer 112c may be disposed
in a protruding form on the second insulating layer 111b, resulting
in contact with the second interconnection member 140. The first
redistribution layer 112a and the second redistribution layer 112b
of the first interconnection member 110 may be disposed on a level
between an active surface and an inactive surface of the
semiconductor chip 120. The first interconnection member 110 may be
formed at a thickness corresponding to that of the semiconductor
chip 120. Therefore, the first redistribution layer 112a and the
second redistribution layer 112b formed in the first
interconnection member 110 may be disposed on a level between the
active surface and the inactive surface of the semiconductor chip
120.
[0125] Thicknesses of the redistribution layers 112a, 112b, 112c,
and 112d of the first interconnection member 110 may be greater
than those of the redistribution layers 142a and 142b of the second
interconnection member 140. Since the first interconnection member
110 may have a thickness equal to or greater than that of the
semiconductor chip 120, the redistribution layers 112a, 112b, 112c,
and 112d may also be formed to have large sizes. On the other hand,
the redistribution layers 142a and 142b of the second
interconnection member 140 may be formed at a relatively small size
for thinness.
[0126] A description, or the like, of other configurations and a
manufacturing method except for the abovementioned configuration
overlaps that described above, and is thus omitted.
[0127] As set forth above, according to the exemplary embodiment in
the present disclosure, a fan-out semiconductor package in which
sufficient close adhesion of an under-bump metal layer may be
secured may be provided.
[0128] While exemplary embodiments have been shown and described
above, it will be apparent to those skilled in the art that
modifications and variations could be made without departing from
the scope of the present invention as defined by the appended
claims.
* * * * *