U.S. patent application number 15/435951 was filed with the patent office on 2017-12-07 for semiconductor packages including heat spreaders and methods of manufacturing the same.
This patent application is currently assigned to SK hynix Inc.. The applicant listed for this patent is SK hynix Inc.. Invention is credited to Han Jun BAE, Jong Hoon KIM, Ki Jun SUNG.
Application Number | 20170352612 15/435951 |
Document ID | / |
Family ID | 60483873 |
Filed Date | 2017-12-07 |
United States Patent
Application |
20170352612 |
Kind Code |
A1 |
SUNG; Ki Jun ; et
al. |
December 7, 2017 |
SEMICONDUCTOR PACKAGES INCLUDING HEAT SPREADERS AND METHODS OF
MANUFACTURING THE SAME
Abstract
There may be provided a method of manufacturing a semiconductor
package. The method may include disposing a first semiconductor
device and through mold ball connectors (TMBCs) on a first surface
of an interconnection structure layer, forming a molding layer on
the first surface of the interconnection structure layer to expose
a portion of each of the TMBCs, attaching outer connectors to the
exposed portions of the TMBCs, mounting a second semiconductor
device on a second surface of the interconnection structure layer
opposite to the molding layer, and attaching a heat spreader to the
second surface of the interconnection structure layer to overlap
with a portion of the first semiconductor device.
Inventors: |
SUNG; Ki Jun; (Cheongju-si
Chungcheongbuk-do, KR) ; KIM; Jong Hoon; (Suwon-si
Gyeonggi-do, KR) ; BAE; Han Jun; (Seongnam-si
Gyeonggi-do, KR) |
|
Applicant: |
Name |
City |
State |
Country |
Type |
SK hynix Inc. |
Icheon-si Gyeonggi-do |
|
KR |
|
|
Assignee: |
SK hynix Inc.
Icheon-si Gyeonggi-do
KR
|
Family ID: |
60483873 |
Appl. No.: |
15/435951 |
Filed: |
February 17, 2017 |
Current U.S.
Class: |
1/1 |
Current CPC
Class: |
H01L 24/16 20130101;
H01L 2924/00014 20130101; H01L 21/6835 20130101; H01L 2924/15321
20130101; H01L 23/3128 20130101; H01L 24/92 20130101; H01L
2224/81801 20130101; H01L 2924/00014 20130101; H01L 2924/181
20130101; H01L 21/4857 20130101; H01L 2924/15747 20130101; H01L
2224/29099 20130101; H01L 2924/00012 20130101; H01L 2924/014
20130101; H01L 2924/00014 20130101; H01L 2924/00012 20130101; H01L
2924/00012 20130101; H01L 2924/00014 20130101; H01L 21/486
20130101; H01L 23/5389 20130101; H01L 2224/81447 20130101; H01L
2224/92225 20130101; H01L 2224/13101 20130101; H01L 21/561
20130101; H01L 23/367 20130101; H01L 23/3677 20130101; H01L
2224/32245 20130101; H01L 2924/1434 20130101; H01L 24/81 20130101;
H01L 2224/13101 20130101; H01L 2224/16225 20130101; H01L 2924/15311
20130101; H01L 21/568 20130101; H01L 23/15 20130101; H01L
2224/16145 20130101; H01L 2224/81801 20130101; H01L 2924/01029
20130101; H01L 2221/68345 20130101; H01L 2924/1434 20130101; H01L
24/32 20130101; H01L 2224/13025 20130101; H01L 2924/18161 20130101;
H01L 2224/83447 20130101; H01L 24/17 20130101; H01L 2224/81001
20130101; H01L 2924/00014 20130101; H01L 2224/81447 20130101; H01L
23/49811 20130101; H01L 24/73 20130101; H01L 2924/1433 20130101;
H01L 24/13 20130101; H01L 23/147 20130101; H01L 2924/1433 20130101;
H01L 23/5383 20130101; H01L 23/5384 20130101; H01L 23/49816
20130101; H01L 25/18 20130101; H01L 2224/73253 20130101; H01L
2924/181 20130101 |
International
Class: |
H01L 23/498 20060101
H01L023/498; H01L 23/00 20060101 H01L023/00; H01L 23/31 20060101
H01L023/31; H01L 23/367 20060101 H01L023/367 |
Foreign Application Data
Date |
Code |
Application Number |
Jun 2, 2016 |
KR |
1020160069107 |
Claims
1. A semiconductor package comprising: a first semiconductor device
disposed on a first surface of an interconnection structure layer;
through mold ball connectors (TMBCs) disposed on the first surface
of the interconnection structure layer to be adjacent to the first
semiconductor device; a molding layer disposed on the first surface
of the interconnection structure layer to expose a portion of each
of the TMBCs; outer connectors respectively attached to the TMBCs;
and a second semiconductor device and a first heat spreader
disposed on a second surface of the interconnection structure layer
opposite to the molding layer, wherein the first heat spreader is
disposed to be spaced apart from the second semiconductor device
and to vertically overlap with a portion of the first semiconductor
device.
2. The semiconductor package of claim 1, wherein the TMBCs comprise
a material having a melting point greater than a molding
temperature of the molding layer.
3. The semiconductor package of claim 1, wherein the TMBCs comprise
a material having a melting point greater than a curing temperature
used for a post mold curing process of the molding layer.
4. The semiconductor package of claim 1, wherein the TMBCs comprise
copper.
5. The semiconductor package of claim 1, wherein the TMBCs comprise
a material having a melting point which is greater than a melting
point of tin.
6. The semiconductor package of claim 1, wherein the TMBCs comprise
a material having a melting point which is at least twice more than
the melting point of the tin.
7. The semiconductor package of claim 1, further comprising:
bonding pads disposed on the second surface of the interconnection
structure layer and bonded to the first heat spreader; and
conductive trace patterns disposed in the interconnection structure
layer and connected to the bonding pads to constitute a heat
emission path.
8. The semiconductor package of claim 7, further comprising first
bump pads disposed on the second surface of the interconnection
structure layer to connect the second semiconductor device to the
interconnection structure layer, wherein the bonding pads have a
thickness which is greater than a thickness of the first bump
pads.
9. The semiconductor package of claim 1, wherein the
interconnection structure layer includes: a dielectric body; first
vertical interconnection portions disposed in the dielectric body
to electrically connect the first semiconductor device to the
second semiconductor device; second vertical interconnection
portions disposed in the dielectric body to electrically connect
the second semiconductor device to some of the outer connectors;
and horizontal interconnection portions disposed in the dielectric
body to electrically connect the first semiconductor device to some
others of the outer connectors.
10. The semiconductor package of claim 1, wherein the outer
connectors connected to the second vertical interconnection
portions are disposed to vertically overlap with the second
semiconductor device.
11. The semiconductor package of claim 1, wherein the first heat
spreader have a closed loop shape in a plan view to provide a
through hole in which the second semiconductor device is
disposed.
12. The semiconductor package of claim 1, wherein the first heat
spreader is attached to the second surface of the interconnection
structure layer using a thermal interface material layer.
13. The semiconductor package of claim 1, further comprising: a
package substrate attached to the outer connectors; and a second
heat spreader attached to the second semiconductor device and the
first heat spreader using a thermal interface material layer,
wherein the second heat spreader extends to be attached to the
package substrate.
14. A semiconductor package comprising: first semiconductor devices
disposed on a first surface of an interconnection structure layer;
a molding layer disposed on the first surface of the
interconnection structure layer to protect the first semiconductor
devices; a second semiconductor device disposed on a second surface
of the interconnection structure layer opposite to the molding
layer; a first heat spreader disposed on the second surface of the
interconnection structure layer to be spaced apart from the second
semiconductor device and to overlap with a portion of each of the
first semiconductor devices; a package substrate disposed on
surfaces of the first semiconductor devices and the molding layer
opposite to the interconnection structure layer; outer connectors
disposed between the package substrate and the molding layer; and a
second heat spreader attached to the second semiconductor device
and the first heat spreader using a thermal interface material
layer, wherein the second heat spreader extends to be attached to
the package substrate.
Description
CROSS-REFERENCE TO RELATED APPLICATIONS
[0001] The present application claims priority under 35 U.S.C
119(a) to Korean Patent Application No. 10-2016-0069107, filed on
Jun. 2, 2016, which is incorporated herein by reference in its
entirety.
BACKGROUND
1. Technical Field
[0002] Embodiments of the present disclosure may generally relate
to semiconductor packages and, more particularly, to semiconductor
packages relating to heat spreaders and through mold ball
connectors and methods of manufacturing the same.
2. Related Art
[0003] In the electronics industry, a single unified package
including a plurality of semiconductor devices is increasingly in
demand with the development of multi-functional products.
Additionally, there is an increasing demand for the single unified
packages to have a larger storage capacity along with smaller
electronic systems or products. The single unified package may be
designed to reduce a total size thereof and to have various
functions. The single unified package may be realized to include a
plurality of semiconductor chips having different functions. This
is for processing a large amount of data within a small amount of
time. A system-in-package (SIP) has been proposed for providing the
single unified package. A lot of focus has been on integrating at
least one microprocessor and at least one memory chip in a single
system-in-package.
SUMMARY
[0004] According to an embodiment, there may be provided a method
of manufacturing a semiconductor package. The method may include
forming an interconnection structure layer including conductive
trace patterns and a dielectric layer on a dummy wafer, attaching a
carrier wafer to a second surface of the interconnection structure
layer opposite to the dummy wafer, recessing the dummy wafer to
expose a first surface of the interconnection structure layer
opposite to the carrier wafer, mounting at least one first
semiconductor device and through mold ball connectors on the first
surface of the interconnection structure layer, forming a molding
layer on the first surface of the interconnection structure layer
to expose a portion of each of the through mold ball connectors,
respectively attaching outer connectors to the exposed portions of
the through mold ball connectors, removing the carrier wafer to
expose the second surface of the interconnection structure layer,
and mounting a second semiconductor device and a first heat
spreader on the second surface of the interconnection structure
layer. The first heat spreader may be mounted to be spaced apart
from the second semiconductor device and to vertically overlap with
a portion of the first semiconductor device.
[0005] According to an embodiment, there may be provided a method
of manufacturing a semiconductor package. The method may include
mounting first semiconductor devices on a first surface of an
interconnection structure layer, forming a molding layer on the
first surface of the interconnection structure layer to protect the
first semiconductor devices, and attaching a second semiconductor
device and a first heat spreader to a second surface of the
interconnection structure layer opposite to the molding layer. The
first heat spreader may be mounted to be spaced apart from the
second semiconductor device and to vertically overlap with a
portion of the first semiconductor device.
[0006] According to an embodiment, a semiconductor package may be
provided. The semiconductor package may include a first
semiconductor device disposed on a first surface of an
interconnection structure layer, through mold ball connectors
(TMBCs) disposed on the first surface of the interconnection
structure layer to be adjacent to the first semiconductor device, a
molding layer disposed on the first surface of the interconnection
structure layer to expose a portion of each of the TMBCs, outer
connectors respectively attached to the TMBCs, and a second
semiconductor device and a first heat spreader disposed on a second
surface of the interconnection structure layer opposite to the
molding layer. The first heat spreader may be disposed to be spaced
apart from the second semiconductor device and to vertically
overlap with a portion of the first semiconductor device.
[0007] According to an embodiment, a semiconductor package may be
provided. The semiconductor package may include a first
semiconductor devices disposed on a first surface of an
interconnection structure layer, a molding layer disposed on the
first surface of the interconnection structure layer to protect the
first semiconductor devices, a second semiconductor device disposed
on a second surface of the interconnection structure layer opposite
to the molding layer, a first heat spreader disposed on the second
surface of the interconnection structure layer to be spaced apart
from the second semiconductor device and to overlap with a portion
of each of the first semiconductor devices, a package substrate
disposed on surfaces of the first semiconductor devices and the
molding layer opposite to the interconnection structure layer,
outer connectors disposed between the package substrate and the
molding layer, and a second heat spreader attached to the second
semiconductor device and the first heat spreader using a thermal
interface material layer. The second heat spreader may extend to be
attached to the package substrate.
[0008] According to an embodiment, there may be provided a memory
card including a semiconductor package. The semiconductor package
may include a first semiconductor device disposed on a first
surface of an interconnection structure layer, through mold ball
connectors (TMBCs) disposed on the first surface of the
interconnection structure layer to be adjacent to the first
semiconductor device, a molding layer disposed on the first surface
of the interconnection structure layer to expose a portion of each
of the TMBCs, outer connectors respectively attached to the TMBCs,
and a second semiconductor device and a first heat spreader
disposed on a second surface of the interconnection structure layer
opposite to the molding layer. The first heat spreader may be
disposed to be spaced apart from the second semiconductor device
and to vertically overlap with a portion of the first semiconductor
device.
[0009] According to an embodiment, there may be provided a memory
card including a semiconductor package. The semiconductor package
may include first semiconductor devices disposed on a first surface
of an interconnection structure layer, a molding layer disposed on
the first surface of the interconnection structure layer to protect
the first semiconductor devices, a second semiconductor device
disposed on a second surface of the interconnection structure layer
opposite to the molding layer, a first heat spreader disposed on
the second surface of the interconnection structure layer to be
spaced apart from the second semiconductor device and to overlap
with a portion of each of the first semiconductor devices, a
package substrate disposed on surfaces of the first semiconductor
devices and the molding layer opposite to the interconnection
structure layer, outer connectors disposed between the package
substrate and the molding layer, and a second heat spreader
attached to the second semiconductor device and the first heat
spreader using a thermal interface material layer. The second heat
spreader may extend to be attached to the package substrate.
[0010] According to an embodiment, there may be provided an
electronic system including a semiconductor package. The
semiconductor package may include a first semiconductor device
disposed on a first surface of an interconnection structure layer,
through mold ball connectors (TMBCs) disposed on the first surface
of the interconnection structure layer to be adjacent to the first
semiconductor device, a molding layer disposed on the first surface
of the interconnection structure layer to expose a portion of each
of the TMBCs, outer connectors respectively attached to the TMBCs,
and a second semiconductor device and a first heat spreader
disposed on a second surface of the interconnection structure layer
opposite to the molding layer. The first heat spreader may be
disposed to be spaced apart from the second semiconductor device
and to vertically overlap with a portion of the first semiconductor
device.
[0011] According to an embodiment, there may be provided an
electronic system including a semiconductor package. The
semiconductor package may include first semiconductor devices
disposed on a first surface of an interconnection structure layer,
a molding layer disposed on the first surface of the
interconnection structure layer to protect the first semiconductor
devices, a second semiconductor device disposed on a second surface
of the interconnection structure layer opposite to the molding
layer, a first heat spreader disposed on the second surface of the
interconnection structure layer to be spaced apart from the second
semiconductor device and to overlap with a portion of each of the
first semiconductor devices, a package substrate disposed on
surfaces of the first semiconductor devices and the molding layer
opposite to the interconnection structure layer, outer connectors
disposed between the package substrate and the molding layer, and a
second heat spreader attached to the second semiconductor device
and the first heat spreader using a thermal interface material
layer. The second heat spreader may extend to be attached to the
package substrate.
BRIEF DESCRIPTION OF THE DRAWINGS
[0012] FIGS. 1 to 27 illustrate a method of manufacturing a
semiconductor package according to an embodiment.
[0013] FIGS. 28 and 29 are cross-sectional views illustrating a
structure of a semiconductor package according to an
embodiment.
[0014] FIG. 30 is a cross-sectional view illustrating a
semiconductor device included in a semiconductor package according
to an embodiment.
[0015] FIG. 31 is a cross-sectional view illustrating a defect of a
semiconductor package according to an embodiment.
[0016] FIG. 32 is a cross-sectional view illustrating a
semiconductor package according to an embodiment;
[0017] FIG. 33 is a cross-sectional view illustrating a
semiconductor package according to an embodiment.
[0018] FIG. 34 is a block diagram illustrating an electronic system
employing a memory card including at least one of packages
according to some embodiments.
[0019] FIG. 35 is a block diagram illustrating an electronic system
including at least one of packages according to some
embodiments.
DETAILED DESCRIPTION
[0020] The terms used herein may correspond to words selected in
consideration of their functions in the embodiments, and the
meanings of the terms may be construed to be different according to
ordinary skill in the art to which the embodiments belong. If
defined in detail, the terms may be construed according to the
definitions. Unless otherwise defined, the terms (including
technical and scientific terms) used herein have the same meaning
as commonly understood by one of ordinary skill in the art to which
the embodiments belong. It will be understood that although the
terms first, second, third etc. may be used herein to describe
various elements, these elements should not be limited by these
terms. These terms are only used to distinguish one element from
another element, but not used to define only the element itself or
to mean a particular sequence.
[0021] Semiconductor packages according to the following
embodiments may correspond to system-in-packages (SIPs). Each of
the semiconductor packages may be realized to include a plurality
of semiconductor devices, at least two of which are designed to
have different functions. The semiconductor devices may be obtained
by separating a semiconductor substrate such as a wafer including
electronic circuits into a plurality of pieces (having
semiconductor die shapes or semiconductor chip shapes) using a die
sawing process. Alternatively, each of the semiconductor devices
may have a package form including a package substrate and a
semiconductor die mounted on the package substrate. Each of the
semiconductor devices may include a plurality of semiconductor dice
which are vertically stacked to have a three-dimensional structure,
and the plurality of semiconductor dice may be electrically
connected to each other by silicon through vias (TSVs) penetrating
the plurality of semiconductor dice. The semiconductor dice may
correspond to memory chips including dynamic random access memory
(DRAM) circuits, static random access memory (SRAM) circuits, flash
circuits, magnetic random access memory (MRAM) circuits, resistive
random access memory (ReRAM) circuits, ferroelectric random access
memory (FeRAM) circuits or phase change random access memory
(PcRAM) circuits which are integrated on the semiconductor
substrate. The semiconductor chips or the semiconductor packages
may be employed in communication systems such as mobile phones,
electronic systems associated with biotechnology or health care, or
wearable electronic systems.
[0022] In some embodiments, the semiconductor chip may corresponds
to a logic chip having a system-on-chip (SoC) form. The SoC may be
an application specific integrated circuit (ASIC) chip including a
microprocessor, a microcontroller, a digital signal processing core
or an interface. The SoC may include a central processing unit
(CPU) or a graphics processing unit (GPU). In order that the SoC
operates at a high speed, the SoC has to communicate with a memory
chip storing data at a high speed. That is, a short interface path
and a high signal bandwidth may be required to improve an operation
speed of the SoC. For example, if a GPU chip and a high bandwidth
memory (HBM) chip are vertically stacked in a single SIP, an
interface path between the GPU chip and the HBM chip may be reduced
to improve an operation speed of the GPU chip.
[0023] In an electronic system, a bottleneck phenomenon in
communication between a memory chip and a processor chip may
degrade the performance of the electronic system. Accordingly, high
performance memory chips such as HBM chips may be employed as
memory chips of the electronic systems. The HBM chip may be
configured to include a plurality of memory dice which are
vertically stacked using a TSV technique to obtain a high bandwidth
thereof. The HBM chip may include a plurality of TSVs connected to
each of the memory dice to independently control the respective
memory dice which are vertically stacked. Each of the memory dice
may be configured to include two memory channels, and a plurality
of TSVs, for example, one hundred and twenty eight TSVs acting as
input/output (I/O) pins may be required for operation of each
memory channel. Accordingly, an HBM chip comprised of four stacked
memory dice may include one thousand and twenty four TSVs to
independently control eight memory channels. In such a case, one of
the eight memory channels may independently communicate with
another one of the eight memory channels through the TSVs. Thus, a
signal bandwidth of the HBM chip may be broadened because each
memory channel independently and directly receives or outputs
signals through the TSVs.
[0024] However, if the number of the TSVs increases to improve the
bandwidth of the HBM chip, a pitch size of interconnection lines or
pads included in the HBM chip may be reduced. Therefore, the
following embodiments provide various SIPs having a configuration
that electrically connects the memory chip to the ASIC chip using
an interconnection structure layer realized with a wafer processing
technique which is capable of forming fine patterns.
[0025] The same reference numerals refer to the same elements
throughout the specification. Thus, even though a reference numeral
is not mentioned or described with reference to a drawing, the
reference numeral may be mentioned or described with reference to
another drawing. In addition, even though a reference numeral is
not illustrated in a drawing, it may be mentioned or described with
reference to another drawing.
[0026] FIGS. 1 to 27 illustrate a method of manufacturing a
semiconductor package according to an embodiment and a
configuration of the semiconductor package manufactured
thereby.
[0027] FIG. 1 illustrates a step of forming an interconnection
structure layer 100 on a dummy wafer 900. The dummy wafer 900 may
be a wafer having a first surface 901 and a second surface 902
which are opposite to each other. The interconnection structure
layer 100 may be formed on the first surface 901 of the dummy wafer
900. The interconnection structure layer 100 may be formed using a
silicon processing technique or a semiconductor processing
technique. The interconnection structure layer 100 may be formed by
sequentially or alternately stacking a plurality of dielectric
layers and a plurality of conductive layers. In such a case, each
of the conductive layers included in the interconnection structure
layer 100 may be patterned after it is stacked. The interconnection
structure layer 100 may be formed to have a first surface 101 that
faces and contacts the first surface 901 of the dummy wafer 900 and
to have a second surface 102 which is opposite to the dummy wafer
900. A multi-layered interconnection structure may be disposed in
the interconnection structure layer 100 to electrically connect
some members disposed on the first surface 101 of the
interconnection structure layer 100 to each other. The
interconnection structure layer 100 may be formed to include a
plurality of stacked dielectric layers that electrically insulate
or physically separate conductive trace patterns from each
other.
[0028] The dummy wafer 900 may be used as a supporter or a
substrate when the interconnection structure layer 100 is formed.
The dummy wafer 900 may be a bare silicon wafer. Alternatively, the
dummy wafer 900 may be a non-semiconductor wafer. For example, the
dummy wafer 900 may be a wafer including an insulation material or
a dielectric material. In some embodiments, the dummy wafer 900 may
be a sapphire wafer or a silicon on insulator (SOI) wafer. If a
bare silicon wafer is used as the dummy wafer 900, the
interconnection structure layer 100 may be formed using
semiconductor wafer processing apparatuses and semiconductor wafer
processing techniques.
[0029] As described more fully with reference to the drawings
later, first semiconductor devices and outer connectors may be
disposed on the first surface 101 of the interconnection structure
layer 100 and second semiconductor devices and heat spreaders may
be disposed on the second surface 102 of the interconnection
structure layer 100. The first surface 101 of the interconnection
structure layer 100 may have regions 173 on which first
semiconductor devices are disposed and regions 174 on which outer
connectors are disposed. The regions 174 may be set to be located
between the regions 173. The second surface 102 of the
interconnection structure layer 100 may have a region 175 on which
a second semiconductor device is disposed and regions 178 on which
a first heat spreader is disposed. The region 175 may be set to be
located between the regions 178.
[0030] Although processes for forming the interconnection structure
layer 100 are described hereinafter in conjunction with wafer
processing techniques, the present disclosure is not limited
thereto. For example, the interconnection structure layer 100 may
be formed by changing or modifying a process sequence or pattern
shapes used in the following embodiments. In some embodiments, the
interconnection structure layer 100 may be formed using processes
for forming general redistribution lines. The dummy wafer 900 may
provide the first surface 901 having a flat surface profile. Thus,
the interconnection structure layer 100 may be formed to include
conductive trace patterns having a fine pitch.
[0031] FIGS. 2 to 4 are enlarged views illustrating a portion of
the interconnection structure layer 100 and illustrating a step of
forming the interconnection structure layer 100. Referring to FIG.
2, first outer conductive trace patterns 110 may be formed on the
first surface 901 of the dummy wafer 900. For example, a conductive
layer such as a metal layer may be formed on the first surface 901
of the dummy wafer 900, and the conductive layer may be patterned
using a photolithography process and an etch process to form the
first outer conductive trace patterns 110. The first conductive
outer trace patterns 110 may be formed of a copper (Cu) layer or an
aluminum (Al) layer.
[0032] The first outer conductive trace patterns 110 may correspond
to some of interconnection lines included in the interconnection
structure layer 100. The first outer conductive trace patterns 110
may be formed to have pad shapes. The first outer conductive trace
patterns 110 may include first patterns 112 and second patterns 113
having substantially the same shape as the first patterns 112. The
first and second patterns 112 and 113 of the first outer conductive
trace patterns 110 may be connected to a first semiconductor device
which is disposed later. The first and second patterns 112 and 113
of the first outer conductive trace patterns 110 may be formed on
the region 173 of the first surface 101 of the interconnection
structure layer 100. The first outer conductive trace patterns 110
may further include third patterns 114 and fourth patterns 115
having substantially the same shape as the third patterns 114. The
third and fourth patterns 114 and 115 of the first outer conductive
trace patterns 110 may be connected to outer connectors such as
solder balls which are disposed later. The third and fourth
patterns 114 and 115 of the first outer conductive trace patterns
110 may be formed on the regions 174 of the first surface 101 of
the interconnection structure layer 100.
[0033] The third and fourth patterns 114 and 115 of the first outer
conductive trace patterns 110 may be formed to have a pitch (or a
width) which is greater than a pitch (or a width) of the first and
second patterns 112 and 113 of the first outer conductive trace
patterns 110. Even though a pitch of the third and fourth patterns
114 and 115 is different from a pitch of the first and second
patterns 112 and 113, all of the first outer conductive trace
patterns 110 may be patterned to have relatively finer pitches as
compared with a case that printed circuit patterns are formed on a
general printed circuit board (PCB) because a surface flatness of
the dummy wafer 900 is superior to that of the PCB.
[0034] Referring to FIG. 3, a first dielectric layer 191 may be
formed on the first surface 901 of the dummy wafer 900 to cover and
insulate the first outer conductive trace patterns 110 from each
other. The first dielectric layer 191 may be formed to include at
least one of various dielectric materials. For example, the first
dielectric layer 191 may be formed of an interlayer dielectric
(ILD) layer or an inter-metal dielectric (IMD) layer comprised of a
silicon oxide layer, a silicon nitride layer, or a polymer layer
such as a polyimide layer. The first dielectric layer 191 may be
formed using a lamination process, a deposition process or a
coating process.
[0035] First inner conductive trace patterns 120 may be formed on
the first dielectric layer 191. The first inner conductive trace
patterns 120 may be formed to provide routes of the first outer
conductive trace patterns 110. For example, the first inner
conductive trace patterns 120 may be formed to be electrically
connected to the first outer conductive trace patterns 110 through
vias 121v that substantially penetrate the first dielectric layer
191. A first pattern 120A corresponding to one of the first inner
conductive trace patterns 120 may be formed to act as a horizontal
interconnection portion 161 electrically connecting the second
pattern 113 of the first outer conductive trace patterns 110 to the
third pattern 114 of the first outer conductive trace patterns
110.
[0036] Referring to FIG. 4, a second dielectric layer 193 may be
formed on the first dielectric layer 191 to cover and insulate the
first inner conductive trace patterns 120 from each other. The
second dielectric layer 193 may be formed to include at least one
of various dielectric materials. Second inner conductive trace
patterns 130 may be formed on the second dielectric layer 193. The
second inner conductive trace patterns 130 may be divided into two
groups including first patterns 131 and second patterns 133. The
first patterns 131 of the second inner conductive trace patterns
130 may be formed to provide routes of the first inner conductive
trace patterns 120. The second patterns 133 of the second inner
conductive trace patterns 130 may be formed to provide heat
emission paths 167 (or heat transmission paths) in the
interconnection structure layer 100. The second patterns 133 of the
second inner conductive trace patterns 130 may be formed to overlap
with the region 178 on which a first heat spreader is disposed, and
some of the second patterns 133 may be formed to overlap with the
region 173 on which a first semiconductor device is disposed. The
heat emission paths 167 may be formed to conduct heat mainly
generated from the first semiconductor device (300 of FIG. 16) on
the region 173 to the second surface 102 of the interconnection
structure layer 100.
[0037] The first patterns 131 of the second inner conductive trace
patterns 130 may be formed to be electrically connected to the
first inner conductive trace patterns 120 through vias 131v that
substantially penetrate the second dielectric layer 193. The second
patterns 133 of the second inner conductive trace patterns 130 may
be formed not to be connected to the first inner conductive trace
patterns 120.
[0038] A third dielectric layer 194 may be formed on the second
dielectric layer 193 to cover and insulate the second inner
conductive trace patterns 130 from each other. The third dielectric
layer 194 may be formed to include at least one of various
dielectric materials. Third inner conductive trace patterns 140 may
be formed on the third dielectric layer 194. The third inner
conductive trace patterns 140 may be divided into two groups
including first patterns 141 and second patterns 143. The first
patterns 141 of the second inner conductive trace patterns 140 may
be formed to provide routes of the first patterns 131 of the second
inner conductive trace patterns 130. The second patterns 143 of the
third inner conductive trace patterns 140 may be formed to provide
the heat emission paths 167 in the interconnection structure layer
100. The second patterns 143 of the third inner conductive trace
patterns 140 may be formed to overlap with the region 178 on which
the first heat spreader (810 of FIG. 22) is disposed, and some of
the second patterns 143 may be formed to extend onto the region 173
overlapping with the first semiconductor device (300 of FIG.
16).
[0039] The first patterns 141 of the third inner conductive trace
patterns 140 may be formed to be electrically connected to the
first patterns 131 of the second inner conductive trace patterns
130 through vias 141v that substantially penetrate the third
dielectric layer 194. The second patterns 143 of the third inner
conductive trace patterns 140 may be electrically connected to the
second patterns 133 of the second inner conductive trace patterns
130 through vias 143v that substantially penetrate the third
dielectric layer 194 in order to constitute the heat emission paths
167.
[0040] A fourth dielectric layer 195 may be formed on the third
dielectric layer 194 to cover and insulate the third inner
conductive trace patterns 140 from each other. The fourth
dielectric layer 195 may be formed to include at least one of
various dielectric materials. Second outer conductive trace
patterns 150 may be formed to penetrate the fourth dielectric layer
195. The second outer conductive trace patterns 150 may be
electrically connected to the third inner conductive trace patterns
140, respectively. The second outer conductive trace patterns 150
may be divided into two groups including first patterns 151 and
second patterns 153. The first patterns 151 of the second outer
conductive trace patterns 150 may be formed to provide routes of
the first patterns 141 of the third inner conductive trace patterns
140. The second patterns 153 of the second outer conductive trace
patterns 150 may be formed to provide the heat emission paths 167
in the interconnection structure layer 100. The second patterns 153
of the second outer conductive trace patterns 150 may be formed to
overlap with the region 178 on which the first heat spreader (810
of FIG. 22) is disposed. The second patterns 153, the second
patterns 143 and the second patterns 133 may constitute the heat
emission paths 167 to efficiently conduct the heat generated at the
first surface 101 of the interconnection structure layer 100 to the
second surface 102 of the interconnection structure layer 100.
[0041] One of the first inner conductive trace patterns 120, one of
the first pattern 131 of the second inner conductive trace patterns
130, and one of the first patterns 141 of the third inner
conductive trace patterns 140 may constitute a first vertical
interconnection portion 162 that electrically connects one of the
first patterns 112 to one of the first patterns 151. Another one of
the first inner conductive trace patterns 120, another one of the
first pattern 131 of the second inner conductive trace patterns
130, and another one of the first patterns 141 of the third inner
conductive trace patterns 140 may constitute a second vertical
interconnection portion 163 that electrically connects one of the
fourth patterns 115 to another one of the first patterns 151.
[0042] The first to fourth dielectric layers 191, 193, 194 and 195
may constitute a body of the interconnection structure layer 100
that insulates the trace patterns 110, 120, 130, 140 and 150 from
each other.
[0043] FIG. 5 illustrates a step of forming first bump pads 250 and
first heat spreader bonding pads 280 on the second surface 102 of
the interconnection structure layer 100, and FIG. 6 is an enlarged
view illustrating a portion of the interconnection structure layer
100 illustrated in FIG. 5. Referring to FIGS. 5 and 6, first bump
pads 250 may be formed on the interconnection structure layer 100.
The first bump pads 250 may be pads on which connectors such as
bumps are landed later. The first bump pads 250 may be formed to
overlap with the first patterns 151 of the second outer conductive
trace patterns 150. The first bump pads 250 may be electrically
connected to the first patterns 151, respectively. One pad 250A of
the first bump pads 250 may be electrically connected to the first
vertical interconnection portion 162, and another pad 250B of the
first bump pads 250 may be electrically connected to the second
vertical interconnection portion 163. The first bump pads 250 may
be formed using a plating process. The first bump pads 250 may be
formed to include copper (Cu).
[0044] The first bump pads 250 may be formed on the region 175 of
the second surface 102 of the interconnection structure layer 100,
and a second semiconductor device (500 of FIG. 24) will be mounted
on the first bump pads 250 later. The first heat spreader bonding
pads 280 may be formed on the region 178 of the second surface 102
of the interconnection structure layer 100, and a first heat
spreader (810 of FIG. 28) will be mounted on the first heat
spreader bonding pads 280 later. The first heat spreader bonding
pads 280 may be formed to be bonded to the second patterns 153 of
the second outer conductive trace patterns 150.
[0045] The first heat spreader bonding pads 280 may be formed to
have a pitch (or a width) which is different from a pitch (or a
width) of the first bump pads 250. The first heat spreader bonding
pads 280 will be bonded to a heat emission member or a heat
transmission member such as a heat spreader which is different from
a semiconductor device, later. Thus, the first heat spreader
bonding pads 280 may be formed to include a metal layer having a
thickness which is different from a thickness of the first bump
pads 250. A thickness T2 of the first heat spreader bonding pads
280 may be greater than a thickness T1 of the first bump pads
250.
[0046] FIG. 7 is a cross-sectional view illustrating an example of
a stack structure of the first heat spreader bonding pads 280
illustrated in FIG. 6, and FIG. 8 is a cross-sectional view
illustrating another example of a stack structure of the first heat
spreader bonding pads 280 illustrated in FIG. 6. FIG. 9 is a
cross-sectional view illustrating a stack structure of the first
bump pads 250 illustrated in FIG. 6.
[0047] Referring to FIG. 7, according to some embodiments, each pad
280A of the first heat spreader bonding pads 280 may be formed to
have a stack structure including a seed metal layer 281, a first
copper layer 282, an intermediate metal layer 283, a second copper
layer 284 and a solder layer 285 which are sequentially stacked.
The seed metal layer 281 may be formed to include a multi-layered
metal layer comprised of a titanium (Ti) layer and a copper (Cu)
layer. The seed metal layer 281 may act as a base layer for growing
a copper layer when the first copper layer 282 is plated. A nickel
(Ni) layer may be formed on the first copper layer 282 to provide
the intermediate metal layer 283. The second copper layer 284 may
be plated on the nickel (Ni) layer corresponding to the
intermediate metal layer 283. The solder layer 285 may be formed of
an alloy layer containing tin (Sn) and silver (Ag) to act as an
adhesive layer. Since the first heat spreader bonding pad 280A is
formed to include a plurality of copper layers such as the first
and second copper layers 282 and 284 using a plating process, the
thickness T2 of the first heat spreader bonding pad 280A may be
greater than the thickness T1 of the first bump pads 250. The
solder layer 285 may be used as an adhesive layer that bonds the
second pattern 153 of the second outer conductive trace patterns
150 to a first heat spreader (810 of FIG. 28).
[0048] Referring to FIG. 8, according to some other embodiments,
each pad 280B of the first heat spreader bonding pads 280 may be
formed to have a stack structure including a seed metal layer
281-1, a copper layer 282-1 and a solder layer 285-1 which are
sequentially stacked. The copper layer 282-1 may be formed to a
thickness which is greater than a thickness of each of the first
and second copper layers 282 and 284 to increase a thickness of the
first heat spreader bonding pad 280B. In such a case, a process
time of a plating process for forming the copper layer 282-1 may
increase.
[0049] Referring to FIG. 9, each of the first bump pads 250 may be
formed to have the thickness T1 which is relatively less than the
thickness T2. The first bump pad 250 may be formed to have a stack
structure including a seed metal layer 251, a copper layer 252 and
a capping layer 253 which are sequentially stacked. The seed metal
layer 251 may be formed to include a multi-layered metal layer
comprised of a titanium (Ti) layer and a copper (Cu) layer. The
capping layer 253 may be formed to include a nickel (Ni) layer and
a gold (Au) layer.
[0050] FIG. 10 is a cross-sectional view illustrating a step of
attaching a carrier wafer 800 to the interconnection structure
layer 100. The carrier wafer 800 may be bonded to the
interconnection structure layer 100 using a temporary adhesive
layer 801 to protect the first bump pads 250 and the first heat
spreader bonding pads 280. The carrier wafer 800 may act as a
supporter for handling the interconnection structure layer 100 in
subsequent processes.
[0051] FIG. 11 is a cross-sectional view illustrating a step of
exposing the first surface 101 of the interconnection structure
layer 100. For example, the dummy wafer 900 may be removed from the
interconnection structure layer 100 to expose the first surface 101
of the interconnection structure layer 100. For example, the dummy
wafer 900 may be ground to reduce a thickness of the dummy wafer
900, and the remaining portion of the dummy wafer 900 may be etched
to expose the first surface 101 of the interconnection structure
layer 100. As a result, the interconnection structure layer 100 may
be separated from the dummy wafer 900 by grinding and etching the
dummy wafer 900.
[0052] FIG. 12 is a cross-sectional view illustrating a step of
forming second bump pads 230 on the first surface 101 of the
interconnection structure layer 100, and FIG. 13 is an enlarged
view of a portion of the interconnection structure layer 100
illustrated in FIG. 12. Referring to FIGS. 12 and 13, the second
bump pads 230 may be formed on the first surface 101 of the
interconnection structure layer 100. Connectors such as bumps may
be landed on and bonded to the second bump pads 230 later. The
second bump pads 230 may be formed to overlap with the first and
second patterns 112 and 113 of the first outer conductive trace
patterns 110, respectively. The second bump pads 230 may be
electrically connected to the first and second patterns 112 and
113, respectively. One pad 230A of the second bump pads 230 may be
electrically connected to the first vertical interconnection
portion 162, and another pad 230B of the second bump pads 230 may
be electrically connected to the horizontal interconnection portion
161. The second bump pads 230 may be formed to have the same
structure as the first bump pads 250. The second bump pads 230 may
be formed by plating a copper material.
[0053] FIG. 14 is a cross-sectional view illustrating a step of
forming third bump pads 240 on the first surface 101 of the
interconnection structure layer 100, and FIG. 15 is an enlarged
view of a portion of the interconnection structure layer 100
illustrated in FIG. 14. Referring to FIGS. 14 and 15, the third
bump pads 240 may be formed on the first surface 101 of the
interconnection structure layer 100. The third bump pads 240 may be
formed to have a pitch which is different from a pitch of the
second bump pads 230. For example, the third bump pads 240 may be
formed to have a pitch which is greater than a pitch of the second
bump pads 230. The third bump pads 240 may be formed of a
conductive layer having a thickness which is different from a
thickness of the second bump pads 230. For example, the third bump
pads 240 may be formed to include a copper layer having a thickness
which is greater than a thickness of the second bump pads 230.
[0054] The third bump pads 240 may be formed to overlap with the
third and fourth patterns 114 and 115 of the first outer conductive
trace patterns 110, respectively. The third bump pads 240 may be
electrically connected to the third and fourth patterns 114 and
115, respectively. One pad 240A of the third bump pads 240 may be
electrically connected to the horizontal interconnection portion
161, and another pad 240B of the third bump pads 240 may be
electrically connected to the second vertical interconnection
portion 163. The third bump pads 240 may be formed by plating a
copper material.
[0055] FIG. 16 is a cross-sectional view illustrating a step of
disposing first semiconductor devices 300 on the first surface 101
of the interconnection structure layer 100. The first semiconductor
devices 300 may be disposed to be connected to the second bump pads
230 through first chip connectors 630. The first chip connectors
630 may conductive connection members such as micro-bumps. At least
one of the first semiconductor devices 300 may be electrically
connected to the third bump pad 240A. For example, one of the first
semiconductor devices 300 may be electrically connected to the
third bump pad 240A through one of the first chip connectors 630,
one (230B of FIG. 15) of the second bump pads 230, and the
horizontal interconnection portion (161 of FIG. 15). The horizontal
interconnection portion (161 of FIG. 15) may be comprised of one of
the second patterns 113 of the first outer conductive trace
patterns 110, the first pattern (120A of FIG. 15) of the first
inner conductive trace patterns 120, and one of the third patterns
114 of the first outer conductive trace patterns 110. At least one
of the first semiconductor devices 300 may be electrically
connected to one or more pads of the first bump pads 250. At least
one of the first semiconductor devices 300 may be electrically
connected to one or more pads of the first bump pads 250 through
one of the first chip connectors 630, another one (230A of FIG. 15)
of the second bump pads 230, and the first vertical interconnection
portion (162 of FIG. 15). The first semiconductor devices 300 may
be memory devices. For example, the first semiconductor devices 300
may be DRAM devices.
[0056] FIG. 17 is a cross-sectional view illustrating a step of
disposing through mold ball connectors (TMBCs) 410B on the first
surface 101 of the interconnection structure layer 100. For
example, the TMBCs 410B may be attached to the third bump pads 240,
respectively. Each of the TMBCs 410B may have a metal ball shape,
for example, a copper ball shape. A solder ball containing tin (Sn)
has a low melting point of about 220 degrees Celsius. Thus, the tin
(Sn) based solder balls may be inappropriate for the TMBCs 410B.
Copper balls may have a melting point which is higher than a
melting point of the tin (Sn) based solder balls. Thus, the copper
balls may be appropriate for the TMBCs 410B. In addition, the
copper balls may have an electrical conductivity which is higher
than an electrical conductivity of the tin (Sn) based solder balls.
Thus, the copper balls may be more appropriate for the TMBCs 410B.
The copper balls coated with a solder layer may be picked and
placed on the third bump pads 240, respectively. Subsequently, the
copper balls may be bonded to the third bump pads 240 using a
solder reflow process to provide the TMBCs 410B attached to the
third bump pads 240. The solder layer coated on the copper balls
may include a nickel solder layer or a nickel layer. The nickel
solder layer may be, for example, a nickel-phosphorus (Ni--P)
layer. In some other embodiments, a solder layer may be formed on
surfaces of the third bump pads 240 without using the copper balls
coated with a solder layer, and the solder layer may be reflowed to
provide the TMBCs 410B on the third bump pads 240.
[0057] A height H1 of the TMBCs 410B from the first surface 101 of
the interconnection structure layer 100 may be greater than a
height H2 of the first semiconductor devices 300 mounted on the
second bump pads 230. In order to set the height H1 which is
greater than the height H2, copper balls having a relatively long
diameter may be used to form the TMBCs 410B or a thickness of the
third bump pads 240 may be increased. As a result, the lower ends
410L of the TMBCs 410B may be located at a level which is lower
than surfaces 301 of the first semiconductor devices 300. That is,
the TMBCs 410B may downwardly protrude from the first semiconductor
devices 300.
[0058] FIG. 18 is a cross-sectional view illustrating a step of
forming a molding layer 450A on the first surface 101 of the
interconnection structure layer 100. The molding layer 450A may be
formed using a wafer molding process to cover the TMBCs 410B and
the first semiconductor devices 300. The molding layer 450A may be
formed of a molding member such as an epoxy molding compound (EMC)
material. For example, the EMC material may be heated up to a
molding temperature of about 180 degrees Celsius to provide a
liquid EMC material, and the liquid EMC material may be coated and
molded on the first surface 101 of the interconnection structure
layer 100 to cover the TMBCs 410B and the first semiconductor
devices 300. The molded EMC material may be cured by a post mold
curing process to form the molding layer 450A. The post mold curing
process may be performed at a curing temperature of about 175
degrees Celsius, which is lower than the molding temperature. Since
the copper balls of the TMBCs 410B have a melting point which is
higher than the molding temperature and the curing temperature, the
TMBCs 410B may not be transformed even though the molding process
and the post mold curing process are performed. General tin (Sn)
based solder balls may have a relatively low melting point. Thus,
if the TMBCs 410B are formed of the tin (Sn) based solder balls
without using the copper balls, the TMBCs 410B may be transformed
during the molding process and the post mold curing process.
Accordingly, the TMBCs 410B may be formed using the copper balls
instead of the tin (Sn) based solder balls to provide stable ball
connectors.
[0059] FIG. 19 is a cross-sectional view illustrating a step of
exposing surfaces 410T of the TMBCs 410B. For example, the molding
layer 450A may be recessed to expose a portion of each of the TMBCs
410B, and the exposed portions of the TMBCs 410B may be removed to
provide the flat surfaces 410T of the TMBCs 410B. The molding layer
450A may be recessed using a grinding process to provide a molding
layer 450. In such a case, the lower ends 410L of the TMBCs 410B
may be removed during the grinding process. As a result, the
surfaces 410T of the TMBCs 410B may be exposed by removing a
portion of the molding layer 450A. Since the lower ends 410L of the
TMBCs 410B are removed while the molding layer 450A is recessed,
the exposed surfaces 410T of the TMBCs 410B may have a flat surface
profile. The molding layer 450A may be recessed until the surfaces
301 of the first semiconductor devices 300 are exposed. Since the
surfaces 301 of the first semiconductor devices 300 are exposed
after the molding layer 450A is recessed, heat generated from the
first semiconductor devices 300 may be efficiently radiated into an
outside space. While the molding layer 450A is recessed to provide
the molding layer 450, the first semiconductor devices 300 may be
partially removed so that the exposed surfaces 301 of the first
semiconductor devices 300 may be coplanar with a bottom surface of
the recessed molding layer 450A. As a result, the exposed surfaces
301 of the first semiconductor devices 300, a bottom surface 451 of
the recessed molding layer 450A, and the exposed surfaces 410T of
the TMBCs 410B may be coplanar with each other.
[0060] FIG. 20 is a cross-sectional view illustrating a step of
forming outer connectors 420 on the TMBCs 410B. The outer
connectors 420 may be bonded to the exposed surfaces 410T of the
TMBCs 410B, respectively. Each of the outer connectors 420 may have
a solder ball shape. The outer connectors 420 may be formed of a
tin based solder material including tin (Sn), silver (Ag) and
copper (Cu).
[0061] FIG. 21 is a cross-sectional view illustrating a step of
detaching the carrier wafer 800 from the interconnection structure
layer 100. The carrier wafer 800 may be detached from the
interconnection structure layer 100 by reducing an adhesive
strength of the temporary adhesive layer (801 of FIG. 20). For
example, the carrier wafer 800 may be detached from the
interconnection structure layer 100 by irradiating an ultraviolet
(UV) ray onto the temporary adhesive layer (801 of FIG. 20) or by
applying heat to the temporary adhesive layer (801 of FIG. 20). If
the carrier wafer 800 is detached from the interconnection
structure layer 100, the second surface 102 of the interconnection
structure layer 100, the first bump pads 250, and the first heat
spreader bonding pads 280 may be exposed.
[0062] FIG. 22 is a cross-sectional view illustrating a step of
disposing a first heat spreader 810 on the first heat spreader
bonding pads 280, and FIG. 23 is an enlarged view illustrating a
portion of the region 178 including the first heat spreader 810
illustrated in FIG. 22. The first heat spreader 810 may be disposed
on the second surface 102 of the interconnection structure layer
100. The first heat spreader 810 may be bonded to the first heat
spreader bonding pads 280 disposed on the regions 178 so that the
first heat spreader 810 is connected to the second patterns (153 of
FIG. 6) of the second outer conductive trace patterns 150. As a
result, the first heat spreader 810 may be connected to the heat
emission paths 167.
[0063] The heat generated from the first semiconductor devices 300
when the first semiconductor devices 300 operate may be trapped in
the interconnection structure layer 100 adjacent to the first
semiconductor devices 300. The interconnection structure layer 100
adjacent to the first semiconductor devices 300 may be covered with
the molding layer 450 having a relatively low heat conductivity.
Thus, almost all of the heat transmitted from the first
semiconductor devices 300 into the interconnection structure layer
100 may be trapped in the interconnection structure layer 100
without emission. The first heat spreader 810 may be attached to
the first heat spreader bonding pads 280 to efficiently emit the
heat trapped in the interconnection structure layer 100. The second
patterns (153 of FIG. 6) of the second outer conductive trace
patterns 150, the second patterns (143 of FIG. 6) of the third
inner conductive trace patterns 140, and the second patterns (133
of FIG. 6) of the second inner conductive trace patterns 130
constituting the heat emission paths (167 of FIG. 6) may be formed
of a metal material to have a heat conductivity which is higher
than that of the interconnection structure layer 100. Thus, the
heat trapped in the interconnection structure layer 100 may be
conducted to the first heat spreader 810 through the heat emission
paths (167 of FIG. 6).
[0064] FIG. 24 is a cross-sectional view illustrating a step of
disposing a second semiconductor device 500 on the first bump pads
250, and FIGS. 25 to 27 are plan views of a semiconductor package
10 illustrated in a direction `D` of FIG. 24. FIGS. 26 and 27 are
plan views illustrating an array of the first heat spreader bonding
pads 280 and an array of first heat spreader bonding pads 280S.
[0065] Referring to FIGS. 24 and 25, the second semiconductor
device 500 may be bonded to the first bump pads 250 using second
chip connectors 650. The first heat spreader 810 may have a
rectangular closed loop shape in a plan view to surround the second
semiconductor device 500. That is, the second semiconductor device
500 may be disposed in a through hole 811 surrounded by the first
heat spreader 810. Referring to FIG. 25, one portion of each of the
first semiconductor devices 300 may overlap with a portion of the
second semiconductor device 500, and the other portion of the each
of the first semiconductor devices 300 may overlap with a portion
of the first heat spreader 810.
[0066] Referring to FIG. 26, the first heat spreader bonding pads
280 connecting the interconnection structure layer 100 to the first
heat spreader 810 may be arrayed at cross points of a plurality of
rows and a plurality of columns intersecting the plurality of rows,
respectively. Alternatively, referring to FIG. 27, the first heat
spreader bonding pads 280S may be arrayed in a zigzag fashion along
a row direction and along a column direction.
[0067] Referring to FIG. 24, the second chip connectors 650 may be
conductive connection members such as micro-bumps. The second
semiconductor device 500 may be electrically connected to the first
semiconductor devices 300 through the first vertical
interconnection portions (162 of FIG. 15). For example, the second
semiconductor device 500 may be electrically connected to one of
the first semiconductor devices 300 through some of the second chip
connectors 650, some (250A of FIG. 15) of the first bump pad 250,
some of the first vertical interconnection portions (162 of FIG.
15) connecting the first patterns 112 of the first outer conductive
trace patterns 110 to some of the second outer conductive trace
patterns 150, and some (230A of FIG. 15) of the second bump pads
230. The second semiconductor device 500 may be electrically
connected to some of the outer connectors 420 through other second
vertical interconnection portions which are disconnected from the
first semiconductors 300. For example, the second semiconductor
device 500 may be electrically connected to some of the outer
connectors 420 through some of the second chip connectors 650, some
(250A of FIG. 15) of the first bump pad 250, some of the second
vertical interconnection portions (163 of FIG. 15) connecting the
second patterns 113 of the first outer conductive trace patterns
110 to some of the second outer conductive trace patterns 150, and
some (230A of FIG. 15) of the second bump pads 230.
[0068] Before the second semiconductor device 500 is bonded to the
first bump pads 250, the interconnection structure layer 100 and
the molding layer 450 may be separated into a plurality of pieces
by a die sawing process. The second semiconductor device 500 may be
bonded to the first bump pads 250 of any one piece of the
interconnection structure layer 100 to provide a semiconductor
package 10 including the first and second semiconductor devices 300
and 500 attached to the first and second surfaces 101 and 102 of
the interconnection structure layer 100.
[0069] FIGS. 28 and 29 are cross-sectional views illustrating a
structure of the semiconductor package 10 according to an
embodiment. The semiconductor package 10 illustrated in FIGS. 28
and 29 may be realized using the fabrication processes described
with reference to FIGS. 1 to 27. FIG. 28 illustrates the
semiconductor package 10 together with a heat emission path 167A,
and FIG. 29 illustrates the semiconductor package 10 together with
signal paths 160. In FIG. 28, the heat generated from the first
semiconductor devices 300 may be conducted to the second surface
102 of the interconnection structure layer 100 through the heat
emission path 167A and may be emitted into the outside space
through the first heat spreader 810.
[0070] Referring to FIG. 29, the second semiconductor device 500
may be disposed on the second surface 102 of the interconnection
structure layer 100. Since the second semiconductor device 500 is
bonded to the first bump pads 250 through the second chip
connectors 650 using a soldering process, the second semiconductor
device 500 may be mounted on the second surface 102 of the
interconnection structure layer 100. The first semiconductor
devices 300 may be disposed on the first surface 101 of the
interconnection structure layer 100. The first semiconductor
devices 300 may be disposed side by side on the first surface 101
of the interconnection structure layer 100. Since the first
semiconductor devices 300 are bonded to the second bump pads 230
through the first chip connectors 630 using a soldering process,
the first semiconductor devices 300 may be mounted on the first
surface 101 of the interconnection structure layer 100.
[0071] The second semiconductor device 500 may have a different
function from the first semiconductor devices 300, and the first
and second semiconductor devices 300 and 500 may constitute a
single unified system-in-package (CIP). The second semiconductor
device 500 or each of the first semiconductor devices 300 may
include a semiconductor substrate (not illustrated) such as a
silicon substrate, active devices (not illustrated) such as
transistors, and interconnection layers. The active devices may be
formed on the semiconductor substrate, and the interconnection
layers may be formed on the active devices and the semiconductor
substrate. The interconnection layers may be formed to include an
interlayer dielectric (ILD) layer or an inter-metal dielectric
(IMD) layer.
[0072] The second semiconductor device 500 may be, for example but
not limited to, a central processing unit (CPU) or a graphic
processing unit (GPU). The second semiconductor device 500 may be
provided in a chip form or a package form including a molding
member that protects a chip. The second semiconductor device 500
may be disposed on the second surface 102 of the interconnection
structure layer 100, and the first semiconductor devices 300 may be
disposed on the first surface 101 of the interconnection structure
layer 100 opposite to the second semiconductor device 500. The
second semiconductor device 500 may be vertically stacked on the
first semiconductor devices 300. The second semiconductor device
500 may be signally communicate with the first semiconductor
devices 300 through an interface physical layer (PHY). Since the
second semiconductor device 500 is vertically stacked on the first
semiconductor devices 300, a length of signal paths between the
second semiconductor device 500 and each of the first semiconductor
devices 300 may be reduced to improve an operation speed of the
semiconductor package 10. If the second semiconductor device 500
includes a GPU and the first semiconductor devices 300 are memory
devices, a length of signal paths between the second semiconductor
device 500 and each of the first semiconductor devices 300 may be
reduced to improve an image data processing speed of the
semiconductor package 10 including the GPU.
[0073] In the semiconductor package 10, the TMBCs 410B may be
disposed on the first surface 101 of the interconnection structure
layer 100. The TMBCs 410B and the first semiconductor devices 300
may be disposed on the first surface 101 of the interconnection
structure layer 100 to be adjacent to the first semiconductor
devices 300. Each of the TMBCs 410B may include a copper ball. In
some embodiments, each of the TMBCs 410B may include a plurality of
copper balls which are vertically stacked to have a pillar shape.
The TMBCs 410B may be bonded to the third bump pads 240,
respectively. Thus, the TMBCs 410B may be electrically connected to
the interconnection structure layer 100 through the third bump pads
240.
[0074] In the semiconductor package 10, the molding layer 450 may
be provided to cover the first surface 101 of the interconnection
structure layer 100 and to fill spaces between the TMBCs 410B and
the first semiconductor devices 300. The outer connectors 420 may
be attached to the TMBCs 410B, respectively. The TMBCs 410B may
substantially penetrate the molding layer 450 to electrically
connect the interconnection structure layer 100 to outer connectors
420. The lower surfaces 410T of the TMBCs 410B may be exposed at a
bottom surface of the molding layer 450 and may have a flat surface
profile. The outer connectors 420 such as solder balls may be more
readily attached to the lower surfaces 410T of the TMBCs 410B
because the lower surfaces 410T of the TMBCs 410B are flat.
[0075] The interconnection structure layer 100 may include the
signal paths 160, that is, interconnection portions. The
interconnection portions 160 may include the horizontal
interconnection portions 161, each of which electrically connects
one of the second bump pads 230 to one of the third bump pads 240.
The interconnection portions 160 may also include the first
vertical interconnection portions 162, each of which electrically
connects one of the second bump pads 230 to one of the first bump
pads 250. In addition, the interconnection portions 160 may further
include the second vertical interconnection portions 163, each of
which electrically connects one of the third bump pads 240 to one
of the first bump pads 250. The horizontal interconnection portions
161 may electrically connect the first semiconductor devices 300 to
some of the outer connectors 420, the first vertical
interconnection portions 162 may electrically connect the first
semiconductor devices 300 to the second semiconductor device 500,
and the second vertical interconnection portions 163 may
electrically connect the second semiconductor device 500 to some of
the outer connectors 420.
[0076] FIG. 30 is a cross-sectional illustrating one of the first
semiconductor devices 300 included in the semiconductor package 10
of FIG. 28. Referring to FIG. 30, the first semiconductor device
300 may include a plurality of semiconductor dice 310, 300A, 300B,
300C and 300D which are vertically stacked. For example, the master
die 310, the first slave die 300A, the second slave die 300B, the
third slave die 300C and the fourth slave die 300D may be
sequentially and downwardly stacked. The plurality of dice 310,
300A, 300B, 300C and 300D may be electrically connected to each
other by a through silicon via (TSV) structure including TSVs 311,
321A, 321B and 321C, internal interconnection lines 312, 322A, 322B
and 322C, and connection bumps 330. The first semiconductor device
300 may further include side molding part 330M covering the slave
dice 300A, 300B, 300C and 300D. A top surface 300T of the fourth
slave die 300D may be exposed to improve a heat emission efficiency
of the semiconductor package 10. The top surface 300T of the fourth
slave die 300D may correspond to the top surface 301 of the first
semiconductor device 300. A surface 303 of the master die 310
opposite to the slave dice 300A, 300B, 300C and 300D may also be
exposed, and the first chip connectors 630 may be attached to the
surface 303 of the master die 310. The first semiconductor device
300 including the plurality of semiconductor dice 310, 300A, 300B,
300C and 300D may be a high performance memory device such as a
high bandwidth memory (HBM) device.
[0077] The interconnection structure layer 100 of the semiconductor
package 10 illustrated in FIGS. 28 and 29 may be formed by
depositing dielectric layers and conductive layers and by
patterning the dielectric layers and the conductive layers. Thus, a
thickness of the interconnection structure layer 100 may be
reduced. This interconnection structure layer 100 may be formed
using a fine patterning technique such as a wafer processing
technique or a silicon processing technique. Accordingly, the
interconnection portions 160 may be formed to include a plurality
of interconnection lines having a fine pitch.
[0078] FIG. 31 is a cross-sectional view of a portion of a
defective semiconductor package in the event that the TMBCs 410B
are formed of solder balls. Since the TMBCs 410B are disposed to
substantially penetrate the molding layer 450, it may be important
to prevent the generation of defects while the molding layer 450 is
formed.
[0079] If the TMBCs 410B are formed of solder balls 410, the solder
balls may come out of the molding layer 450 when the outer
connectors (420 of FIG. 21) are attached to the solder balls 410.
The outer connectors (420 of FIG. 21) may be attached to the solder
balls 410 using a solder reflow process. In such a case, the solder
balls 410 may be melted and the molding layer 450 may be expanded.
Thus, at least one of the solder balls 410 may undesirably come out
of the molding layer 450 due to the heat generated by the solder
reflow process and pressure applied to the solder balls 410. This
is because the solder balls 410 containing a tin based solder
material has a relatively low melting point of about 220 degrees
Celsius. If at least one of the solder balls 410 is removed, a void
410V may be provided in the molding layer 450.
[0080] The loss of the solder balls 410 may cause a connection
failure of the solder balls 410. However, according to the
embodiments, the TMBCs 410B may be formed of metal balls having a
melting point which is higher than a melting point of a tin (Sn)
material. Thus, it may prevent the void 410V from being formed in
the molding layer 450. In some embodiments, the TMBCs 410B may be
formed of metal balls having a melting point which is at least
twice that of a tin (Sn) material. For example, each of the TMBCs
410B may be formed to include a copper ball. In such a case, the
TMBCs 410B may also have a high electrical conductivity to reduce
an electrical resistance of the TMBCs 410B. The copper ball may be
coated by a nickel layer or a nickel solder layer.
[0081] FIG. 32 is a cross-sectional view illustrating a
semiconductor package 20 according to an embodiment. The
semiconductor package 20 may be configured to include a package
substrate 700 and the semiconductor package 10 (illustrated in
FIGS. 28 and 29) mounted on the package substrate 700. The package
substrate 700 may electrically connect the semiconductor package 10
to an electronic product. The package substrate 700 may include
connectors 710 such as solder balls. The package substrate 700 may
be a printed circuit board (PCB).
[0082] The semiconductor package 20 may further include a second
heat spreader 850 attached to the second semiconductor device 500
using a first thermal interface material layer 865. The second heat
spreader 850 may also be attached to the first heat spreader 810
using a second thermal interface material layer 861. Since the
first heat spreader 810 is connected to the second heat spreader
850, the heat generated in the semiconductor package 10 may be
emitted and radiated through the heat emission path (167A of FIG.
28) and the second heat spreader 850. The first heat spreader 810
may include a metal material, for example, a copper foil or a
copper plate.
[0083] The second heat spreader 850 may be attached to the package
substrate 700 using a stiffener 730. The semiconductor package 10
may be disposed in a space which is surrounded by the second heat
spreader 850, the stiffener 730 and the package substrate 700.
[0084] FIG. 33 is a cross-sectional view illustrating a
semiconductor package 30 according to an embodiment. The present
embodiments may be similar to a previous embodiment described with
reference to FIG. 32. Thus, to avoid duplicate explanation,
differences between the present embodiments and a previous
embodiment illustrated in FIG. 32 will be mainly described
hereinafter. The semiconductor package 30 may include a third
thermal interface material layer 863 that bonds the first heat
spreader 810 to the interconnection structure layer 100. In such a
case, the first heat spreader 810 may be bonded to the
interconnection structure layer 100 by the third thermal interface
material layer 863 without even using the first heat spreader
bonding pads (280 of FIG. 32 and 280S of FIG. 27).
[0085] FIG. 34 is a block diagram illustrating an electronic system
including a memory card 7800 including at least one semiconductor
package according to an embodiment. The memory card 7800 includes a
memory 7810, such as a nonvolatile memory device, and a memory
controller 7820. The memory 7810 and the memory controller 7820 may
store data or read stored data. The memory 7810 and/or the memory
controller 7820 include at least one of the semiconductor packages
according to some embodiments.
[0086] The memory 7810 may include a nonvolatile memory device to
which the technology of the embodiments of the present disclosure
is applied. The memory controller 7820 may control the memory 7810
such that stored data is read out or data is stored in response to
a read/write request from a host 7830.
[0087] FIG. 35 is a block diagram illustrating an electronic system
8710 including at least one package according to an embodiment. The
electronic system 8710 may include a controller 8711, an
input/output device 8712, and a memory 8713. The controller 8711,
the input/output device 8712 and the memory 8713 may be coupled
with one another through a bus 8715 providing a path through which
data move.
[0088] In an embodiment, the controller 8711 may include one or
more microprocessor, digital signal processor, microcontroller,
and/or logic device capable of performing the same functions as
these components. The controller 8711 or the memory 8713 may
include one or more of the semiconductor packages according to
embodiments of the present disclosure. The input/output device 8712
may include at least one selected among a keypad, a keyboard, a
display device, a touchscreen and so forth. The memory 8713 is a
device for storing data. The memory 8713 may store data and/or
commands to be executed by the controller 8711, and the like.
[0089] The memory 8713 may include a volatile memory device such as
a DRAM and/or a nonvolatile memory device such as a flash memory.
For example, a flash memory may be mounted to an information
processing system such as a mobile terminal or a desktop computer.
The flash memory may constitute a solid state disk (SSD). In this
case, the electronic system 8710 may stably store a large amount of
data in a flash memory system.
[0090] The electronic system 8710 may further include an interface
8714 configured to transmit and receive data to and from a
communication network. The interface 8714 may be a wired or
wireless type. For example, the interface 8714 may include an
antenna or a wired or wireless transceiver.
[0091] The electronic system 8710 may be realized as a mobile
system, a personal computer, an industrial computer or a logic
system performing various functions. For example, the mobile system
may be any one of a personal digital assistant (PDA), a portable
computer, a tablet computer, a mobile phone, a smart phone, a
wireless phone, a laptop computer, a memory card, a digital music
system and an information transmission/reception system.
[0092] If the electronic system 8710 is an equipment capable of
performing wireless communication, the electronic system 8710 may
be used in a communication system such as of CDMA (code division
multiple access), GSM (global system for mobile communications),
NADC (north American digital cellular), E-TDMA (enhanced-time
division multiple access), WCDAM (wideband code division multiple
access), CDMA2000, LTE (long term evolution) and Wibro (wireless
broadband Internet).
[0093] Embodiments of the present disclosure have been disclosed
for illustrative purposes. Those skilled in the art will appreciate
that various modifications, additions and substitutions are
possible, without departing from the scope and spirit of the
present disclosure and the accompanying claims.
* * * * *