U.S. patent application number 15/367054 was filed with the patent office on 2017-11-30 for finfet with p/n stacked fins and method for fabricating the same.
This patent application is currently assigned to TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.. The applicant listed for this patent is TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.. Invention is credited to Hung-Pin CHEN, Li-Yi CHEN, Ru-Shang HSIAO, Chi-Cherng JENG.
Application Number | 20170345923 15/367054 |
Document ID | / |
Family ID | 60418274 |
Filed Date | 2017-11-30 |
United States Patent
Application |
20170345923 |
Kind Code |
A1 |
CHEN; Hung-Pin ; et
al. |
November 30, 2017 |
FINFET WITH P/N STACKED FINS AND METHOD FOR FABRICATING THE
SAME
Abstract
A semiconductor device is provided and includes a semiconductor
fin protruding from a semiconductor substrate. The semiconductor
fin includes plural pairs of semiconductor layers on the
semiconductor substrate, each pair of semiconductor layers consists
of a first semiconductor layer of a first conductivity type, and a
second semiconductor layer of a second conductivity type. The
second semiconductor layer is stacked on and contacts the first
semiconductor layer.
Inventors: |
CHEN; Hung-Pin; (Kaohsiung
City, TW) ; JENG; Chi-Cherng; (Tainan City, TW)
; HSIAO; Ru-Shang; (Hsinchu County, TW) ; CHEN;
Li-Yi; (Tainan City, TW) |
|
Applicant: |
Name |
City |
State |
Country |
Type |
TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD. |
Hsinchu |
|
TW |
|
|
Assignee: |
TAIWAN SEMICONDUCTOR MANUFACTURING
CO., LTD.
Hsinchu
TW
|
Family ID: |
60418274 |
Appl. No.: |
15/367054 |
Filed: |
December 1, 2016 |
Related U.S. Patent Documents
|
|
|
|
|
|
Application
Number |
Filing Date |
Patent Number |
|
|
62342127 |
May 26, 2016 |
|
|
|
Current U.S.
Class: |
1/1 |
Current CPC
Class: |
H01L 2029/7857 20130101;
H01L 29/785 20130101; H01L 21/30604 20130101; H01L 29/66795
20130101; H01L 29/0673 20130101; H01L 29/41791 20130101; H01L
27/1211 20130101; H01L 21/845 20130101; H01L 29/16 20130101; H01L
29/66439 20130101; H01L 29/36 20130101; H01L 21/26506 20130101;
H01L 29/775 20130101; H01L 29/42356 20130101 |
International
Class: |
H01L 29/78 20060101
H01L029/78; H01L 29/423 20060101 H01L029/423; H01L 29/36 20060101
H01L029/36; H01L 21/265 20060101 H01L021/265; H01L 29/16 20060101
H01L029/16; H01L 21/306 20060101 H01L021/306; H01L 29/66 20060101
H01L029/66; H01L 29/417 20060101 H01L029/417 |
Claims
1-9. (canceled)
10. A semiconductor device, comprising: a semiconductor substrate;
a semiconductor fin protruding from the semiconductor substrate,
the semiconductor fin comprising: at least one pair of
semiconductor layers on the semiconductor substrate, each of the at
least one pair of semiconductor layers consisting of: a first
semiconductor layer of a first conductivity type, wherein the first
semiconductor layer of a first pair of semiconductor layers is
disposed over the semiconductor substrate; and a second
semiconductor layer of a second conductivity type stacked on and in
contact with the first semiconductor layer, wherein the second
conductivity type is different from the first conductivity type,
and when a number of the at least one pair of the semiconductor
layers is more than one, the first semiconductor layer of the other
pair or pairs of semiconductor layers is stacked on and contact the
second semiconductor layer of an underlying pair of semiconductor
layers.
11. The semiconductor device of claim 10, wherein the semiconductor
substrate and the semiconductor fin are formed from SiGe.
12. The semiconductor device of claim 10, wherein a thickness ratio
of the first semiconductor layer to the second semiconductor layer
is substantially in a range from 0.01 to 100.
13. The semiconductor device of claim 10, wherein the first
semiconductor layer comprises an n type dopant, and the second
semiconductor layer comprises a p type dopant, wherein the second
semiconductor layer corresponds to a PMOS device.
14. The semiconductor device of claim 10, wherein the first
semiconductor layer comprises a p type dopant, and the second
semiconductor layer comprises an n type dopant, wherein the second
semiconductor layer corresponds to an NMOS device.
15. The semiconductor device of claim 10, further comprising: a
gate oxide covering side surfaces and top surface of the
semiconductor fin; and a gate electrode covering side surfaces and
top surface of the gate oxide.
16-20. (canceled)
21. The semiconductor device of claim 10, wherein a thickness ratio
of the first semiconductor layer to the second semiconductor layer
is substantially in a range from 0.1 to 10.
22. The semiconductor device of claim 10, wherein a thickness of
the first semiconductor layer is substantially twice of a thickness
of the second semiconductor layer.
23. The semiconductor device of claim 10, wherein the semiconductor
substrate and the semiconductor fin are formed from silicon.
24. The semiconductor device of claim 10, wherein an average ion
concentration of the second semiconductor layer is greater than an
average ion concentration of the first semiconductor layer.
25. The semiconductor device of claim 10, wherein the second
semiconductor layer has an average boron concentration
substantially in a range from 1.times.10.sup.16/cm.sup.3 to
1.times.10.sup.20/cm.sup.3, and the first semiconductor layer has
an average phosphorous concentration substantially in a range from
1.times.10.sup.16/cm.sup.3 to 1.times.10.sup.20/cm.sup.3.
26. The semiconductor device of claim 10, wherein the semiconductor
device is a junctionless thin-film transistor (JL-TFT), a
junctionless field effect transistor (JL-FET), an inversion mode
TFT or FET, or an accumulation mode TFT or FET.
27. The semiconductor device of claim 10, further comprising: an
isolation layer on the semiconductor substrate, wherein the first
semiconductor layer of the first pair of semiconductor layers is
disposed over the isolation layer.
28. A semiconductor device, comprising: a semiconductor substrate;
a semiconductor fin protruding from the semiconductor substrate,
the semiconductor fin comprising: a plurality of pairs of
semiconductor layers on the semiconductor substrate, each of the
pairs of semiconductor layers consisting of: a first semiconductor
layer comprising an n type dopant, wherein the first semiconductor
layer of a first pair of semiconductor layers of the plurality of
pairs of semiconductor layers is disposed over the semiconductor
substrate; and a second semiconductor layer that comprises a p type
dopant and is stacked on and in contact with the first
semiconductor layer, wherein the first semiconductor layer of other
pairs of semiconductor layers is stacked on and contacts the second
semiconductor layer of an underlying pair of semiconductor layers,
and the second semiconductor layer corresponds to a PMOS
device.
29. The semiconductor device of claim 28, wherein an average ion
concentration of the second semiconductor layer is greater than an
average ion concentration of the first semiconductor layer.
30. The semiconductor device of claim 28, wherein a thickness of
the first semiconductor layer is substantially twice of a thickness
of the second semiconductor layer.
31. The semiconductor device of claim 28, wherein the semiconductor
substrate and the semiconductor fin are formed from silicon or
SiGe.
32. A semiconductor device, comprising: a semiconductor substrate;
a semiconductor fin protruding from the semiconductor substrate,
the semiconductor fin comprising: a plurality of pairs of
semiconductor layers on the semiconductor substrate, each of the
pairs of semiconductor layers consisting of: a first semiconductor
layer comprising a p type dopant, wherein the first semiconductor
layer of a first pair of semiconductor layers of the plurality
pairs of semiconductor layers is disposed over the semiconductor
substrate; and a second semiconductor layer that comprises an n
type dopant and is stacked on and in contact with the first
semiconductor layer, wherein the first semiconductor layer of other
pairs of semiconductor layers is stacked on and contacts the second
semiconductor layer of an underlying pair of semiconductor layers,
and the second semiconductor layer corresponds to a NMOS
device.
33. The semiconductor device of claim 32, wherein an average ion
concentration of the second semiconductor layer is greater than an
average ion concentration of the first semiconductor layer.
34. The semiconductor device of claim 32, wherein a thickness of
the first semiconductor layer is substantially twice of a thickness
of the second semiconductor layer.
Description
RELATED APPLICATIONS
[0001] This application claims priority to U.S. Provisional
Application Ser. No. 62/342,127, filed May 26, 2016, which is
herein incorporated by reference.
BACKGROUND
[0002] The semiconductor integrated circuit (IC) industry has
experienced rapid growth. In the course of the IC evolution,
functional density (defined as the number of interconnected devices
per chip area) has generally increased while geometry size (i.e.,
the smallest component (or line) that can be created using a
fabrication process) has decreased. A scaling down process
generally provides benefits by increasing production efficiency and
lowering associated costs. But, such scaling down has increased the
complexity of processing and manufacturing ICs. For these advances
to be realized, similar developments in IC manufacturing are
needed.
[0003] As the semiconductor IC industry has progressed into
nanometer technology process nodes in pursuit of higher device
density, higher performance, and lower costs, challenges from both
fabrication and design have resulted in the development of
three-dimensional (3D) devices such fin-like field effect
transistors (FinFETs). Advantages of FinFET devices include
reducing the short channel effect and higher current flow. There
has been a desire to use a FinFET device with a high-k gate
dielectric and metal gate electrode to improve device performance
as feature sizes continue to decrease. As many critical scaling
limits become more difficult to overcome, a stacked FinFET
structure is one of promising ways to sustain scaling. However,
conventional stacked FinFET devices and methods of fabricating the
stacked FinFET devices have not been entirely satisfactory in all
respects.
BRIEF DESCRIPTION OF THE DRAWINGS
[0004] Aspects of the present disclosure are best understood from
the following detailed description when read with the accompanying
figures. It is noted that, in accordance with the standard practice
in the industry, various features are not drawn to scale. In fact,
the dimensions of the various features may be arbitrarily increased
or reduced for clarity of discussion.
[0005] FIG. 1 is a schematic 3D diagram of a semiconductor device
in accordance with some embodiments of the present disclosure.
[0006] FIG. 2 is a schematic 3D diagram of a semiconductor device
in accordance with certain embodiments of the present
disclosure.
[0007] FIG. 3 is a schematic cross-sectional view of a
semiconductor fin 310 in accordance with certain embodiments of the
present disclosure.
[0008] FIG. 4A to FIG. 4H are schematic cross-sectional views of
intermediate stages showing a method for fabricating a
semiconductor device in accordance with some embodiments of the
present disclosure.
[0009] FIG. 5 is a flow chart showing a method for fabricating a
semiconductor device in accordance with some embodiments of the
present disclosure.
DETAILED DESCRIPTION
[0010] The following disclosure provides many different
embodiments, or examples, for implementing different features of
the provided subject matter. Specific examples of components and
arrangements are described below to simplify the present
disclosure. These are, of course, merely examples and are not
intended to be limiting. For example, the formation of a first
feature over or on a second feature in the description that follows
may include embodiments in which the first and second features are
formed in direct contact, and may also include embodiments in which
additional features may be formed between the first and second
features, such that the first and second features may not be in
direct contact.
[0011] Terms used herein are only used to describe the specific
embodiments, which are not used to limit the claims appended
herewith. For example, unless limited otherwise, the term "one" or
"the" of the single form may also represent the plural form. In
addition, the present disclosure may repeat reference numerals
and/or letters in the various examples. This repetition is for the
purpose of simplicity and clarity and does not in itself dictate a
relationship between the various embodiments and/or configurations
discussed. The spatially relative terms are intended to encompass
different orientations of the device in use or operation in
addition to the orientation depicted in the figures. The device may
be otherwise oriented (rotated 90 degrees or at other orientations)
and the spatially relative descriptors used herein may likewise be
interpreted accordingly.
[0012] It will be understood that, although the terms "first",
"second", "third", etc., may be used in the claims to describe
various elements, these elements should not be limited by these
terms, and these elements correspondingly described in the
embodiments are presented by different reference numbers. These
terms are used to distinguish one element from another. For
example, a first element could be termed a second element, and,
similarly, a second element could be termed a first element,
without departing from the scope of the embodiments. As used
herein, the term "and/or" includes any and all combinations of one
or more of the associated listed items.
[0013] Embodiments of the present disclosure are directed to a
FinFET with multi-stacking hybrid P/N types of semiconductor layers
and a manufacturing method thereof, and more particularly to a
three-dimensional (3D) stacked hybrid P/N (or N/P) types of
semiconductor layers for p-channel (or n-channel) junctionless
thin-film transistor (JL-TFT) with nanowire (NW) structures. For
manufacturing a p-type metal-oxide-silicon filed-effect transistor
(PMOS) device, embodiments of the present disclosure includes at
least one pair of a p-type semiconductor layer and n-type
semiconductor layer underlying the p-type semiconductor layer, in
which the n-type semiconductor layer between the vertically stacked
p-type semiconductor layers produces an additional depletion
region, such that the effective channel thickness is reduced to
strengthen the gate controllability. For manufacturing an n-type
metal-oxide-silicon filed-effect transistor (NMOS) device,
embodiments of the present disclosure includes at least one pair of
an n-type semiconductor layer and a p-type semiconductor layer
underlying the n-type semiconductor layer, in which the p-type
semiconductor layer between the vertically stacked n-type
semiconductor layers produces an additional depletion region, such
that the effective channel thickness is reduced to strengthen the
gate controllability.
[0014] Referring to FIG. 1, FIG. 1 is a schematic 3D diagram of a
semiconductor device in accordance with some embodiments of the
present disclosure. The semiconductor device includes a
semiconductor substrate 100, a semiconductor fin 110, a gate oxide
170, a gate electrode 180, a source/drain portion 190, and the
other source source/drain portion (not shown). The semiconductor
substrate 100 is defined as any construction including
semiconductor materials, including, but is not limited to, bulk
silicon, a semiconductor wafer, or a silicon germanium (SiGe)
substrate. Other semiconductor materials including group III, group
IV, and group V elements may also be used. Each of the source/drain
portions, for example the source/drain portion 190, includes an end
portion of the semiconductor fin 110 and a contact portion 160
overlying the semiconductor fin 110. The source/drain portion 190
is disposed on the semiconductor fin 110 adjacent to one side of
the gate electrode 180, and the other source source/drain portion
is disposed on the semiconductor fin 110 adjacent to the other side
of the gate electrode 180. The gate oxide 170 is disposed between
the source/drain portion 190 and the other source source/drain
portion, and covers sides surfaces and top surface of the
semiconductor fin 110, and the gate electrode 180 covers side
surfaces and top surface of the gate oxide 170. In some
embodiments, the gate electrode 180 may be an omegagate. However,
different types of gate electrode are suitable for use in
embodiments of the present disclosure. Thus, the source/drain
portions together with the gate electrode form a FinFET device.
[0015] The semiconductor fin 110 includes a first semiconductor
layer 120 of a first conductivity type and a second semiconductor
layer 130 of a second conductivity type. The first semiconductor
layer 120 and the second semiconductor layer 130 are defined as any
construction including semiconductor materials, including, but is
not limited to, bulk silicon, a semiconductor wafer, or a silicon
germanium (SiGe) substrate. Other semiconductor materials including
group III, group IV, and group V elements may also be used. The
first semiconductor layer 120 of the first conductivity type is
disposed on the semiconductor substrate 100, in which the first
semiconductor layer 120 comprises one of an n type dopant and a p
type dopant. The second semiconductor layer 130 of the second
conductivity type is stacked on and in contact with the first
semiconductor layer, in which the second semiconductor layer 130
comprises the other one of the n type dopant and the p type dopant.
For example, when the first semiconductor layer 120 includes the n
type dopant and the second semiconductor layer 130 includes the p
type dopant, the semiconductor fin 110 has a PN structure, and the
second semiconductor layer 130 corresponds to a PMOS device. When
the first semiconductor layer 120 includes the p type dopant and
the second semiconductor layer 130 includes the n type dopant, the
semiconductor fin 110 has an NP structure, and the second
semiconductor layer 130 corresponds to an NMOS device. In some
embodiments, the semiconductor device further includes an isolation
layer 102, such as tetraethyl orthosilicate (TEOS), disposed on the
semiconductor substrate 100. In that case, the first semiconductor
layer 120 of the first conductivity type is disposed on the
isolation layer 102. In some embodiments, the semiconductor fin 110
is formed by directly processing the semiconductor substrate 100,
such as a bulk FinFET structure, in which the first semiconductor
layer 120 of the first conductivity type is directly disposed on
the semiconductor substrate 100.
[0016] The semiconductor device of the present disclosure may be a
junctionless thin-film transistor (JL-TFT), a junctionless field
effect transistor (JL-FET), an inversion mode TFT or FET, or an
accumulation mode TFT or FET. The thickness of the first
semiconductor layer 120 and the second semiconductor layer 130 is
determined by the type of the semiconductor device and the ion
concentrations of the first semiconductor layer 120 and the second
semiconductor layer 130. In some embodiments, a thickness ratio of
the first semiconductor layer to the second semiconductor layer is
substantially in a range from 0.01 to 100. In certain embodiments,
the thickness ratio is substantially in a range from 0.1 to 10. For
example, a thickness of the first semiconductor layer 120 is about
300 Angstrom, and a thickness of the second semiconductor layer 130
is about 150 Angstrom), and thus the thickness ratio is 2. In some
embodiments, the second semiconductor layer 130 has an average
boron concentration substantially in a range from
1.times.10.sup.16/cm.sup.3 to 1.times.10.sup.20/cm.sup.3, for
example 5.times.10.sup.19/cm.sup.3, and the first semiconductor
layer 120 has an average phosphorous concentration substantially in
a range from 1.times.10.sup.16/cm.sup.3 to
1.times.10.sup.20/cm.sup.3, for example 4.times.10.sup.19/cm.sup.3.
Because the first semiconductor layer 120 is of a conductivity type
(such as an n type) opposite to a conductivity type (such as a p
type) of the second semiconductor layer 130, a depletion region is
produced at the p/n junction between the first semiconductor layer
120 and the second semiconductor layer 130, and thus the effective
channel thickness is reduced to strengthen the controllability of
the gate over that in a conventional JL-TFT, and the semiconductor
device shown in FIG. 1 has good electrical performance. In some
embodiments, the first semiconductor layer 120 and the second
semiconductor layer 130 may be formed from silicon or SiGe. Thus,
the semiconductor device shown in FIG. 1 has good thermal
conductivity due to good Si thermal conductivity, and has good
device variability robustness in processes of forming silicon or
SiGe layers. Accordingly, the stacked hybrid P/N (or N/P) structure
shown in FIG. 1 is a highly promising architecture for 3D stacked
ICs and memory applications due to good Si thermal conductivity,
gate controllability and device variability robustness in process
and electrical performance.
[0017] Referring to FIG. 2, FIG. 2 is a schematic 3D diagram of a
semiconductor device in accordance with certain embodiments of the
present disclosure. The semiconductor device includes a
semiconductor substrate 200, a semiconductor fin 210, a gate oxide
270, a gate electrode 280, a source/drain portion 290, and the
other source source/drain portion (not shown). The semiconductor
substrate 200 is defined as any construction including
semiconductor materials, including, but is not limited to, bulk
silicon, a semiconductor wafer, or a silicon germanium (SiGe)
substrate. Other semiconductor materials including group III, group
IV, and group V elements may also be used. Each of the source/drain
portions, for example the source/drain portion 290, includes an end
portion of the semiconductor fin 210 and a contact portion 260
overlying the semiconductor fin 210. The source/drain portion 290
is disposed on the semiconductor fin 210 adjacent to one side of
the gate electrode 280, and the other source source/drain portion
is disposed on the semiconductor fin 210 adjacent to the other side
of the gate electrode 280. The gate oxide 270 is disposed between
the source/drain portion 290 and the other source source/drain
portion, and covers sides surfaces and top surface of the
semiconductor fin 210, and the gate electrode 280 covers side
surfaces and top surface of the gate oxide 270. In some
embodiments, the gate electrode 280 may be an omegagate. However,
different types of gate electrode are suitable for use in
embodiments of the present disclosure. Thus, the source/drain
portions together with the gate electrode form a FinFET device.
[0018] The semiconductor fin 210 includes a first semiconductor
layer 220 of a first conductivity type, a second semiconductor
layer 230 of a second conductivity type, a third semiconductor
layer 240 of the first conductivity type, and a fourth
semiconductor layer 250 of the second conductivity type, in which
the first conductivity type is one of an n type and a p type, and
the second conductivity type is the other of the n type and the p
type. The first semiconductor layer 220 of the first conductivity
type is disposed on the semiconductor substrate 200. The second
semiconductor layer 230 of the second conductivity type is stacked
on and in contact with the first semiconductor layer 220, in which
the second conductivity type is the other of the n type and the p
type. For example, when the first conductivity type is the n type
and the second conductivity type is the p type, the semiconductor
fin 210 has a PNPN structure, and the second semiconductor layer
230 and the fourth semiconductor layer 250 are corresponding to
respective PMOS devices. When the first conductivity type is the p
type and the second conductivity type is the n type, the
semiconductor fin 210 has an NPNP structure, and the second
semiconductor layer 230 and the fourth semiconductor layer 250
correspond to respective NMOS devices. Therefore, the semiconductor
device shown in FIG. 2 includes two MOS devices of the same type.
In some embodiments, the semiconductor device further includes an
isolation layer 202, such as tetraethyl orthosilicate (TEOS),
disposed on the semiconductor substrate 200. In that case, the
first semiconductor layer 220 of the first conductivity type is
disposed on the isolation layer 202.
[0019] In some embodiments, a thickness (such as about 300
Angstrom) of the first semiconductor layer 220 is substantially
twice of a thickness (such as about 150 Angstrom) of the second
semiconductor layer 230. A thickness (such as about 300 Angstrom)
of the third semiconductor layer 240 is substantially twice of a
thickness (such as about 150 Angstrom) of the fourth semiconductor
layer 250. An average ion concentration of the second semiconductor
layer 230 is greater than an average ion concentration of the first
semiconductor layer 220. An average ion concentration of the fourth
semiconductor layer 250 is greater than an average ion
concentration of the third semiconductor layer 240. In some
embodiments, each of the second semiconductor layer 230 and the
fourth semiconductor layer 250 has an average boron concentration
substantially in a range from 1.times.10.sup.16/cm.sup.3 to
1.times.10.sup.20/cm.sup.3, for example 5.times.10.sup.19/cm.sup.3,
and each of the first semiconductor layer 220 and the third
semiconductor layer 240 has an average phosphorous concentration
substantially in a range from 1.times.10.sup.16/cm.sup.3 to
1.times.10.sup.20/cm.sup.3, for example 4.times.10.sup.19/cm.sup.3.
Because the first semiconductor layer 220 is of a conductivity type
(such as an n type) opposite to a conductivity type (such as a p
type) of the second semiconductor layer 230, a depletion region is
produced at the p/n junction between the first semiconductor layer
220 and the second semiconductor layer 230. Because the third
semiconductor layer 240 is of a conductivity type (such as the n
type) opposite to conductivity types (such as the p type) of the
second semiconductor layer 230 and the fourth semiconductor layer
250, depletion regions are produced at the p/n junction between the
second semiconductor layer 230 and the third semiconductor layer
240, and at the p/n junction between the third semiconductor layer
240 and the fourth semiconductor layer 250. Thus, the second
semiconductor layer 230 corresponding to a MOS device and the
fourth semiconductor layer 250 corresponding to another MOS device
are separated by the third semiconductor layer 240. The effective
channel thickness of each MOS device is reduced to strengthen the
controllability of the gate over that in a conventional JL-TFT, and
the semiconductor device shown in FIG. 2 has good electrical
performance. In some embodiments, the first semiconductor layer
220, the second semiconductor layer 230, the third semiconductor
layer 240 and the fourth semiconductor layer 250 may be formed from
silicon or SiGe. Thus, the semiconductor device shown in FIG. 2 has
good thermal conductivity due to good Si thermal conductivity, and
has good device variability robustness in processes of forming
silicon or SiGe layers. Therefore, the stacked hybrid P/N (or N/P)
structure shown in FIG. 2 is a highly promising architecture for 3D
stacked ICs and memory applications due to good Si thermal
conductivity, gate controllability and device variability
robustness in process and electrical performance.
[0020] For analyzing the characteristic of the PNPN structure (i.e.
the first conductivity type is the n type and the second
conductivity type is the p type) shown in FIG. 2, each nanowire of
the PNPN structure with about 17 nm high.times.35 nm wide is made
for testing stacked P/N JL-TFTs with an omega-gate. To analyze the
doping profile within the stacked hybrid P/N channels (the PNPN
structure), a secondary ion mass spectroscopy (SIMS) measurement is
performed on an un-patterned Si wafer that is performed through the
identical processes except the patterning processes. The p-type
semiconductor layers are doped with average boron concentration of
5.times.10.sup.19 cm.sup.-3 and the underlying n-type semiconductor
layer is doped with phosphorus concentration of 4.times.10.sup.19
cm.sup.-3. The superb transfer characteristics of the stacked P/N
JL-TFTs with a channel length (Lg) of 1 .mu.m are as follows: (1)
subthreshold swing (SS)=70 mV/dec and (2) I.sub.on/I.sub.off
ratio>10.sup.9. The stacked P/N JL-TFTs have the advantages of
an additional depletion region between channel/substrate. The
stacked P/N JL-TFTs show very high I.sub.on/I.sub.off ratio over
10.sup.9 and excellent SS value of 70 mV/dec. Additionally, the
PNPN device has less temperature and device performance fluctuation
in terms of V.sub.th and subthreshold swing (SS).
[0021] Referring to FIG. 3, FIG. 3 is a schematic cross-sectional
view of a semiconductor fin 310 in accordance with certain
embodiments of the present disclosure. The semiconductor fin 310
includes plural pairs 340 of semiconductor layers stacked on a
semiconductor substrate 300. The semiconductor substrate 200 is
defined as any construction including semiconductor materials,
including, but is not limited to, bulk silicon, a semiconductor
wafer, or a silicon germanium (SiGe) substrate. Other semiconductor
materials including group III, group IV, and group V elements may
also be used. Each pair 340 of semiconductor layers consists of a
first semiconductor layer 320 of a first conductivity type, and a
second semiconductor layer 330 of a second conductivity type, in
which the first semiconductor layer 320 includes one of an n type
dopant and a p type dopant, and the second semiconductor layer 330
includes the other of the n type dopant and the p type dopant. The
second semiconductor layer 330 of the second conductivity type is
stacked on and in contact with the first semiconductor layer 320.
For example, when the first semiconductor layer 320 includes the n
type dopant and the second semiconductor layer 330 includes the p
type dopant, the second semiconductor layer 330 in each pair 340 of
semiconductor layers correspond to a PMOS device. When the first
semiconductor layer 320 includes the p type dopant and the second
semiconductor layer 330 includes the n type dopant, the second
semiconductor layer 330 in each pair 340 of semiconductor layers
corresponds to an NMOS device. Therefore, for a k pairs 340 of
semiconductor layers (k is a positive integer), the semiconductor
device shown in FIG. 3 includes k MOS devices of the same
conductivity type. In some embodiments, the semiconductor device
further includes an isolation layer (not shown), such as tetraethyl
orthosilicate (TEOS). In that case, the semiconductor fin 310 is
disposed on the isolation layer.
[0022] In some embodiments, a thickness (such as about 300
Angstrom) of the first semiconductor layer 320 is substantially
twice of a thickness (such as about 150 Angstrom) of the second
semiconductor layer 330. An average ion concentration of the second
semiconductor layer 330 is greater than an average ion
concentration of the first semiconductor layer 320. In some
embodiments, the second semiconductor layer 330 has an average
boron concentration substantially in a range from
1.times.10.sup.16/cm.sup.3 to 1.times.10.sup.20/cm.sup.3, for
example 5.times.10.sup.19/cm.sup.3, and the first semiconductor
layer 320 has an average phosphorous concentration substantially in
a range from 1.times.10.sup.16/cm.sup.3 to
1.times.10.sup.20/cm.sup.3, for example 4.times.10.sup.19/cm.sup.3.
Because the first semiconductor layer 320 is of a conductivity type
(such as an n type) opposite to a conductivity type (such as a p
type) of the second semiconductor layer 330, depletion regions are
produced at a p/n junction between the first semiconductor layer
320 and the second semiconductor layer 330, and at another p/n
junction between the second semiconductor layer 330 and its
overlying first semiconductor layer 320 of the overlying pair 340
of semiconductor layers. Thus, the second semiconductor layer 330
(corresponding to a MOS device) of each pair 340 of semiconductor
layers is separated by its adjoining first semiconductor layers
320. The effective channel thickness of each MOS device is reduced
to strengthen the controllability of the gate over that in a
conventional JL-TFT, and the semiconductor device shown in FIG. 3
has good electrical performance. In some embodiments, the first
semiconductor layer 320 and the second semiconductor layer 330 may
be formed from silicon or SiGe. Thus, the semiconductor device
shown in FIG. 3 has good thermal conductivity due to good Si
thermal conductivity, and has good device variability robustness in
processes of forming silicon or SiGe layers. Accordingly, the
stacked hybrid P/N (or N/P) structure shown in FIG. 3 is a highly
promising architecture for 3D stacked ICs and memory applications
due to good Si thermal conductivity, gate controllability and
device variability robustness in process and electrical
performance.
[0023] Referring to FIG. 5 together with FIG. 4A to FIG. 4H, FIG. 5
is a flow chart showing a method 500 for fabricating a
semiconductor device in accordance with some embodiments of the
present disclosure, and FIG. 4A to FIG. 4H are schematic
cross-sectional views of intermediate stages showing a method for
fabricating a semiconductor device in accordance with some
embodiments of the present disclosure. As shown in FIG. 4A, when
the method 500 begins, a semiconductor substrate 400 is provided,
and an isolation layer 402, such as tetraethyl orthosilicate
(TEOS), is optionally formed on the semiconductor substrate 400.
The semiconductor substrate 100 is defined as any construction
including semiconductor materials, including, but is not limited
to, bulk silicon, a semiconductor wafer, or a silicon germanium
(SiGe) substrate. Other semiconductor materials including group
III, group IV, and group V elements may also be used.
[0024] As shown in FIG. 4B, at operation 510, a first semiconductor
layer 420 is formed on the isolation layer 402. The first
semiconductor layer 420 is formed from such as silicon or
silicon-germanium. In some embodiments, an epitaxy or epitaxial
(epi) process is used to form the first semiconductor layer 420.
The epi process may include a selective epitaxy growth (SEG)
process, CVD deposition techniques (e.g., vapor-phase epitaxy (VPE)
and/or ultra-high vacuum CVD (UHV-CVD)), molecular beam epitaxy,
other suitable epi processes, or combinations thereof. Then, as
shown in FIG. 4C, an operation 520 is performed to implant a first
dopant 422 of a first dopant type into the first semiconductor
layer 410, in which the first dopant type is one of an n type and a
p type. In some examples, the p-type dopant is boron or BF.sub.2,
and the n-type dopant is phosphorus or arsenic, or a combination
thereof. The operation 520 is performed at a dopant dose of about
2.times.10.sup.14/cm.sup.2, for example.
[0025] As shown in FIG. 4D, at operation 530, a second
semiconductor layer 430 is formed on and contacts the first
semiconductor layer 420. The second semiconductor layer 430 is
formed from such as silicon or silicon-germanium. In some
embodiments, an epitaxy or epitaxial (epi) process is used to form
the first semiconductor layer 420. The epi process may include a
selective epitaxy growth (SEG) process, CVD deposition techniques
(e.g., vapor-phase epitaxy (VPE) and/or ultra-high vacuum CVD
(UHV-CVD)), molecular beam epitaxy, other suitable epi processes,
or combinations thereof.
[0026] Then, as shown in FIG. 4E, an operation 540 is performed to
implant a second dopant 432 of a second dopant type into the second
semiconductor layer 430, in which the second dopant type is one of
the n type and the p type. In some examples, the p-type dopant is
boron or BF.sub.2, and the n-type dopant is phosphorus or arsenic,
or a combination thereof. For example, when the first dopant is an
n-type dopant, the second dopant is a p-type dopant; and when the
first dopant is a p-type dopant, the second dopant is an n-type
dopant. The operation 540 is performed at a dopant dose of
2.times.10.sup.14/cm.sup.2, for example. The operations 520 to 540
form a pair of semiconductor layers (a PN or NP structure) as shown
in FIG. 1. In some embodiments, a thickness (such as about 300
Angstrom) of the first semiconductor layer 420 is substantially
twice of a thickness (such as about 150 Angstrom) of the second
semiconductor layer 430. An average ion concentration of the second
semiconductor layer 430 is greater than an average ion
concentration of the first semiconductor layer 420. In some
embodiments, the second semiconductor layer 430 has an average
boron concentration substantially in a range from
1.times.10.sup.16/cm.sup.3 to 1.times.10.sup.20/cm.sup.3, for
example 5.times.10.sup.19/cm.sup.3, and the first semiconductor
layer 420 has an average phosphorous concentration substantially in
a range from 1.times.10.sup.16/cm.sup.3 to
1.times.10.sup.20/cm.sup.3, for example
4.times.10.sup.19/cm.sup.3.
[0027] The operations 520 to 540 can be repeated twice to form two
pairs of semiconductor layers (a PNPN or NPNP structure)
corresponding to two MOS devices as shown in FIG. 2. The operations
520 to 540 can be repeated for k times to form k pairs of
semiconductor layers (a PNPN or NPNP structure) corresponding to k
MOS devices as shown in FIG. 3, in which k is a positive
integer.
[0028] Thereafter, as shown in FIG. 4F, at operation 550, the first
semiconductor layer 420 and the second semiconductor layer 430 are
etched by using a masking layer (not shown) along with a suitable
etching process, so as to form a semiconductor fin 410. As shown in
FIG. 4G, at operation 560, a gate oxide 470 is formed to cover side
surfaces and top surface of the semiconductor fin 410. As shown in
FIG. 4H, at operation 570, the gate electrode 480 is formed to
cover side surfaces and top surface of the gate oxide 470. In some
embodiments, the gate electrode 480 may be an omegagate.
Thereafter, at operation 580, source/drain portions are formed on
both ends of the semiconductor fin and sandwich the gate electrode.
Thus, the source/drain portions together with the gate electrode
form a FinFET device.
[0029] In accordance with some embodiments, a semiconductor device
includes a semiconductor substrate, and a semiconductor fin
protruding from the semiconductor substrate. The semiconductor fin
includes a first semiconductor layer of a first conductivity type
and a second semiconductor layer of a second conductivity type. The
first semiconductor layer of the first conductivity type is
disposed on the semiconductor substrate. The second semiconductor
layer of the second conductivity type is stacked on and in contact
with the first semiconductor layer.
[0030] In accordance with certain embodiments, a semiconductor
device includes a semiconductor substrate, and a semiconductor fin
protruding from the semiconductor substrate. The semiconductor fin
includes plural pairs of semiconductor layers on the semiconductor
substrate. Each of the pairs of semiconductor layers consists of a
first semiconductor layer of a first conductivity type and a second
semiconductor layer of a second conductivity type. The second
semiconductor layer of the second conductivity type is stacked on
and in contact with the first semiconductor layer.
[0031] In accordance with some embodiments, a method for forming a
semiconductor device includes the following steps. A first
semiconductor layer is formed on a semiconductor substrate. A first
dopant of a first dopant type is implanted into the first
semiconductor layer, in which the first dopant type is one of an n
type and a p type. A second semiconductor layer is formed on and
contacts the first semiconductor layer. A second dopant of a second
dopant type is implanted into the second semiconductor layer, in
which the second dopant type is one of the n type and the p type.
The first semiconductor layer and the second semiconductor layer
are etched to form a semiconductor fin.
[0032] The foregoing outlines features of several embodiments so
that those skilled in the art may better understand the aspects of
the present disclosure. Those skilled in the art should appreciate
that they may readily use the present disclosure as a basis for
designing or modifying other processes and structures for carrying
out the same purposes and/or achieving the same advantages of the
embodiments introduced herein. Those skilled in the art should also
realize that such equivalent constructions do not depart from the
spirit and scope of the present disclosure, and that they may make
various changes, substitutions, and alterations herein without
departing from the spirit and scope of the present disclosure.
* * * * *