U.S. patent application number 15/165902 was filed with the patent office on 2017-11-30 for retainer ring for semiconductor manufacturing processes.
The applicant listed for this patent is Taiwan Semiconductor Manufacturing Company, Ltd.. Invention is credited to Cheng-Chun Chang, Chih-Chung Chang, Hsin-Kai Chen, Liang-Guang Chen, Chun-Wei Hsu, Shi-Ya Hsu, Tsung-Ju Lin, Yi-Sheng Lin, Chi-Jen Liu, Yi-Sheng Ma.
Application Number | 20170341201 15/165902 |
Document ID | / |
Family ID | 60420352 |
Filed Date | 2017-11-30 |
United States Patent
Application |
20170341201 |
Kind Code |
A1 |
Hsu; Chun-Wei ; et
al. |
November 30, 2017 |
RETAINER RING FOR SEMICONDUCTOR MANUFACTURING PROCESSES
Abstract
An embodiment retainer ring includes an outer ring encircling an
opening and an inner ring attached to the outer ring. The inner
ring is disposed between the opening and the outer ring. The inner
ring includes a softer material than the outer ring and a plurality
of voids within the softer material.
Inventors: |
Hsu; Chun-Wei; (Hsin-Chu,
TW) ; Liu; Chi-Jen; (Taipei City, TW) ; Chen;
Liang-Guang; (Hsin-Chu, TW) ; Chang; Chih-Chung;
(Hsin-Chu, TW) ; Chang; Cheng-Chun; (Hsin-Chu,
TW) ; Chen; Hsin-Kai; (Hsin-Chu, TW) ; Lin;
Yi-Sheng; (Hsin-Chu, TW) ; Hsu; Shi-Ya;
(Hsin-Chu, TW) ; Lin; Tsung-Ju; (Hsin-Chu, TW)
; Ma; Yi-Sheng; (Hsin-Chu, TW) |
|
Applicant: |
Name |
City |
State |
Country |
Type |
Taiwan Semiconductor Manufacturing Company, Ltd. |
Hsin-Chu |
|
TW |
|
|
Family ID: |
60420352 |
Appl. No.: |
15/165902 |
Filed: |
May 26, 2016 |
Current U.S.
Class: |
1/1 |
Current CPC
Class: |
B24B 37/20 20130101;
B24B 37/32 20130101 |
International
Class: |
B24B 37/32 20120101
B24B037/32; B24B 37/20 20120101 B24B037/20 |
Claims
1. A retainer ring comprising: an outer ring encircling an opening;
and an inner ring attached to the outer ring, wherein the inner
ring is disposed between the opening and the outer ring, and
wherein the inner ring comprises: a softer material than the outer
ring; and a plurality of voids within the softer material.
2. The retainer ring of claim 1, wherein the inner ring is attached
to the outer ring by an adhesive layer disposed between the inner
ring and the outer ring.
3. The retainer ring of claim 1, wherein the inner ring comprises
polyurethane.
4. The retainer ring of claim 1, wherein the outer ring comprises
polyether ether ketone (PEEK), polyphenylene sulfide (PPS), or a
combination thereof.
5. The retainer ring of claim 1, wherein a specific gravity of the
inner ring is less than about 1.0.
6. The retainer ring of claim 1, wherein a hardness of the inner
ring is less than about 55 in a Shore A hardness scale or about 20
in a Shore B hardness scale.
7. The retainer ring of claim 1, wherein the inner ring comprises a
top surface lower than a top surface of the outer ring.
8. The retainer ring of claim 1, wherein the retainer ring is
configured to secure a wafer in the opening, and wherein a height
of the inner ring is at least a height of the wafer.
9. A polishing apparatus comprising: a polishing head; and a
retainer ring attached to the polishing head, wherein the retainer
ring comprises: an outer ring comprising a first material; and an
inner ring comprising a porous second material having a specific
gravity less than about 1.0, wherein the porous second material is
softer than the first material, and wherein the inner ring is
disposed between edges of a wafer and the outer ring when the
retainer ring secures a wafer.
10. The polishing apparatus of claim 9, wherein the porous second
material comprises polyurethane, and wherein the first material
comprises polyether ether ketone (PEEK), polyphenylene sulfide
(PPS), or a combination thereof.
11. The polishing apparatus of claim 9, wherein the specific
gravity of the porous second material is less than about 0.8.
12. The polishing apparatus of claim 9, wherein the porous second
material is less than about 55 in a Shore A hardness scale or less
than about 20 in a Shore B hardness scale.
13. The polishing apparatus of claim 9, wherein the polishing head
further comprises a membrane configured to apply downward pressure
on a wafer secured by the retainer ring.
14. The polishing apparatus of claim 9 further comprising a
polishing pad, wherein the polishing head is configured to rotate a
wafer secured by the retainer ring against the polishing pad.
15. The polishing apparatus of claim 9, wherein the retainer ring
is attached to the polishing head using mechanical screws.
16. A method for processing a wafer comprising: providing a
retainer ring comprising: an outer ring encircling an opening; and
an inner ring attached to the outer ring and encircling the
opening, wherein the inner ring comprises a different material than
the outer ring, and wherein the different material is porous;
positioning a wafer in the opening, wherein the inner ring is
disposed between edges of the wafer and the outer ring; and
processing the wafer while the wafer is secured by the retainer
ring.
17. The method of claim 16, wherein the inner ring comprises a
softer material than the outer ring.
18. The method of claim 16, wherein the inner ring comprises
polyurethane, and wherein the outer ring comprises polyether ether
ketone (PEEK), polyphenylene sulfide (PPS), or a combination
thereof.
19. The method of claim 16, wherein a specific gravity of the inner
ring is less than about 1.0.
20. The method of claim 16, wherein processing the wafer comprises
applying a chemical mechanical polish (CMP) process to the wafer.
Description
BACKGROUND
[0001] Generally, semiconductor devices comprise active components,
such as transistors, formed on a substrate. Any number of
interconnect layers may be formed over the substrate connecting the
active components to each other and to outside devices. The
interconnect layers are typically made of low-k dielectric
materials comprising metallic trenches/vias.
[0002] As the layers of a device are formed, it is sometimes
desirable to planarize the device. For example, the formation of
metallic features in the substrate or in a metal layer may cause
uneven topography. This uneven topography creates difficulties in
the formation of subsequent layers. For example, uneven topography
may interfere with the photolithographic process used to form
various features in a device. It is, therefore, desirable to
planarize the surface of the device after various features or
layers are formed. One method of planarization is chemical
mechanical polishing (CMP).
BRIEF DESCRIPTION OF THE DRAWINGS
[0003] Aspects of the present disclosure are best understood from
the following detailed description when read with the accompanying
figures. It is noted that, in accordance with the standard practice
in the industry, various features are not drawn to scale. In fact,
the dimensions of the various features may be arbitrarily increased
or reduced for clarity of discussion.
[0004] FIGS. 1A, 1B, and 1C illustrate varying views of a retainer
ring in accordance with some embodiments.
[0005] FIG. 2 illustrates a cross sectional view of the retainer
ring during a semiconductor process in accordance with some
embodiments.
[0006] FIGS. 3A and 3B illustrate a micrographic view of
semiconductor wafer edges after processing.
[0007] FIG. 4 illustrates a process flow of a semiconductor process
using a retainer ring according to some embodiments.
DETAILED DESCRIPTION
[0008] The following disclosure provides many different
embodiments, or examples, for implementing different features of
the invention. Specific examples of components and arrangements are
described below to simplify the present disclosure. These are, of
course, merely examples and are not intended to be limiting. For
example, the formation of a first feature over or on a second
feature in the description that follows may include embodiments in
which the first and second features are formed in direct contact,
and may also include embodiments in which additional features may
be formed between the first and second features, such that the
first and second features may not be in direct contact. In
addition, the present disclosure may repeat reference numerals
and/or letters in the various examples. This repetition is for the
purpose of simplicity and clarity and does not in itself dictate a
relationship between the various embodiments and/or configurations
discussed.
[0009] Further, spatially relative terms, such as "beneath,"
"below," "lower," "above," "upper" and the like, may be used herein
for ease of description to describe one element or feature's
relationship to another element(s) or feature(s) as illustrated in
the figures. The spatially relative terms are intended to encompass
different orientations of the device in use or operation in
addition to the orientation depicted in the figures. The apparatus
may be otherwise oriented (rotated 90 degrees or at other
orientations) and the spatially relative descriptors used herein
may likewise be interpreted accordingly.
[0010] Various embodiments are described with respect to a specific
context, namely a retainer ring for use during a chemical
mechanical polish (CMP) process. However, those skilled in the art
will recognize that the described retainer ring could provide
advantageous features in other manufacturing processes,
particularly processes where it is desirable to provide a
relatively soft interface to protect wafer edges during processing
and/or handling steps.
[0011] Various embodiments include a retainer ring for securing a
wafer during processing (e.g., a CMP process). The retainer ring
may include an outer ring and an inner ring attached to a sidewall
of the outer ring. Compared to the material of the outer ring, the
inner ring may comprise a relatively soft material. In some
embodiments, the relatively soft material of the inner ring may be
porous. During processing, the inner ring is disposed between a
wafer and the relatively hard material of the outer ring in order
to protect the edges of the wafer from colliding with the outer
ring. Thus, wafer bevel peeling and scratches resulting from
collisions between the wafer and the outer ring can be
advantageously reduced. Furthermore, in embodiments where the inner
ring comprises a porous material, the voids within the inner ring
may absorb collision energy and protect the wafer during
processing, which may further reduce manufacturing defects.
[0012] FIG. 1A is a schematic diagram of an embodiment retainer
ring 100 for CMP according to some embodiments. The retainer ring
100 includes an outer ring 102 and an inner ring 104 attached to
the outer ring 102. In some embodiments, the inner ring 104 is
attached to the inside of the outer ring 102 using an adhesive
(e.g., glue) layer 110 at the interface between the outer ring 102
and the inner ring 104. In other embodiments, the inner ring 104
may be secured to the outer ring 102 using a different
mechanism.
[0013] The retainer ring 100 is generally annular in shape with an
opening 108 disposed in a center portion. The outer ring 102 and
the inner ring 104 encircle the opening 108, with the inner ring
104 being disposed between the outer ring 102 and the opening 108.
During processing, a wafer may be disposed within opening 108 of
the retainer ring 100, and the retainer ring 100 may secure the
wafer as explained in greater detail below. FIG. 1B is a sliced
cross-sectional view of the embodiment retainer ring 100 in FIG. 1A
taken along the line 106 according to some embodiments. FIG. 1C
illustrates a detailed cross-sectional view of the inner ring 104
according to some embodiments.
[0014] In various embodiments, the inner ring 104 comprises a
softer material than the outer ring 102. In some embodiments, the
inner ring 104 has a hardness less than about 55 in Shore A
hardness scale or less than about 20 in Shore B hardness scale.
Shore hardness is a measure of the resistance of a material to
penetration of a spring loaded needle-like indenter (sometimes
known as a durometer). Hardness of polymers (rubbers, plastics) may
be measured by Shore scales. Shore A scale is used for testing soft
elastomers (e.g., rubbers) and other soft polymers. Hardness of
hard elastomers and most other polymer materials may be measured by
Shore D scale. Different indenter shapes and different spring loads
may be used for different Shore scales (e.g., A and D). For
example, the loading force of Shore A may be about 822 g, and the
loading force of Shore D may be about 4536 g. Shore hardness values
may vary in range from 0 to 100 with a maximum hardness value of
100 corresponding to zero penetration. It has been observed that by
using a relatively soft material for the inner ring 104 within the
above range, wafer edge damage (e.g., scratches and/or peeling)
during processing can be reduced.
[0015] The material of the inner ring 104 may be selected so that
the inner ring 104 is relatively impervious to damage during
processing. For example, during CMP, a chemical slurry may be
applied to a wafer held by the retainer ring 100 (see e.g., FIG.
2), and the retainer ring 100 may also be exposed to the slurry.
The material of the inner ring 104 may be selected to avoid damage
by the slurry environment (e.g., a low pH environment, a high pH
environment, an oxidant containing environment, and the like). In
an embodiment, the inner ring 104 comprises a polymer material,
such as, polyurethane although other suitable materials (e.g.,
having a Shore hardness value as described above) may be used as
well. In contrast, the outer ring 102 may comprise a relatively
hard material (e.g., harder than the inner ring 104). For example,
in an embodiment, the outer ring 102 may comprises polyether ether
ketone (PEEK), polyphenylene sulfide (PPS), any combination
thereof, or any other suitable material. In some embodiments, outer
ring 102 has a hardness greater than about 85 in Shore D hardness
scale. It has been observed that when the hardness of outer ring
102 falls within the above range, outer ring 102 provides improved
chemical and wear resistance and advantageously increases the
durability of retainer ring 100.
[0016] The inner ring 104 may further comprise a porous material,
which may include pores (e.g., voids 104') as illustrated by FIG.
1C. Voids 104' may be formed, for example, by solvent casting
combined with particle leaching (e.g., leaching solid particles,
such as porogens, from a polymer solution), thermally-induced phase
separation, melt molding (e.g., molding with polymer powder and
porogen at a high temperature, such as higher than the polymer
glass-transition temperature and leaching out the porogen), gas
foaming, emulsion freeze drying (e.g., cooling a polymer solution
to form solvent ice crystals and removing the solvent by using a
pressure lower than an equilibrium vapor pressure of the solvent),
or the like. In some embodiments, a specific gravity of the inner
ring 104 may be less than about 1.0, such as less than about 0.8,
for example. Voids 104' may be used to absorb energy (e.g., when a
wafer collides with the retainer ring 100) during processing. Thus,
the inner ring 104 may protect edges of the wafer from damage
caused by collisions during processing. For example, it has been
observed that when the specific gravity of the inner ring 104 is
within the above range, damage to a wafer during processing may be
advantageously reduced.
[0017] In some embodiments, the inside diameter D1 of the retainer
ring 100 ranges 300 mm to 303 mm, the outside diameter D2 ranges
from 329 mm to 333 mm. The size of the retainer ring 100 may be
selected based on a size of a wafer the retainer ring 100 secures
during processing. For example, in other embodiments, the size of
the retainer ring 100 can be different, e.g. being sized to
accommodate a 450 mm diameter wafer during a CMP process or other
process where the wafer is retained during a process step.
[0018] In some embodiments, the inner ring 104 has a thickness T1
ranging from about 0.1 mm to about 0.7 mm. Furthermore, the inner
ring 104 may have a height T2 of about 0.8 mm to about 20 mm. The
height of the inner ring 104 may be selected based on a height of a
wafer secured by the retainer ring 100 during processing. For
example, in other embodiments, the height of the inner ring 104 may
be different, e.g., being sized to accommodate a taller wafer
during a CMP process or other process where the wafer is retained
during a process step. Thus, the inner ring 104 may be disposed
between all sidewalls of the wafer and the outer ring 102 during
processing in order to protect the wafer and reduce damage to wafer
edges.
[0019] In some embodiments, height T2 of the inner ring 104 may be
less than a height of the outer ring 102 in an embodiment. For
example, in FIG. 1B, a top surface of the inner ring 104 is lower
than a top surface of the outer ring 102. In other embodiments,
heights of the inner ring 104 and the outer ring 102 may be
substantially equal.
[0020] FIG. 2 illustrates the retainer ring 100 of Fig. lA in use
during a CMP process according to some embodiments. In FIG. 2, a
retainer ring 100 including the outer ring 102 and the retainer
ring 100 is mounted to a carrier head 202 using mechanical
fasteners such as screws or by any other suitable means. As
described above, the inner ring 104 is softer than the outer ring
102. In some embodiments, the inner ring 104 has a hardness ranging
from 15 to 105 in Shore A hardness scale. Furthermore, the inner
ring 104 may comprise a porous material to further protect edges of
the wafer 200 during processing. For example, the porous material
may act as a shock absorber. In some embodiments, the inner ring
104 comprises porous polyurethane, or any other suitable material,
the outer ring 102 comprises polyether ether ketone (PEEK),
polyphenylene sulfide (PPS), any combination thereof, or any other
suitable material.
[0021] The carrier head 202 has a membrane 204 that interfaces with
a wafer 200. The wafer 200 may be a semiconductor wafer comprising,
for example, a semiconductor substrate (e.g., comprising silicon
although other III-V semiconductor materials may be used as well),
active devices (e.g., transistors) disposed at a top surface of the
semiconductor structure, and/or various interconnect structures.
The interconnect structure may include conductive features, which
electrically connect the active devices in order to form functional
circuits. In various embodiments, CMP processing may be applied to
the wafer 200 during any stage of manufacture in order to
planarize, reduce, or remove features (e.g., dielectric material,
semiconductor material, and/or conductive material) of the wafer
200. Thus, the wafer 200 being processed may include any subset of
the above features as well as other features.
[0022] Initially, the carrier head 202 may be lowered towards a
wafer 200 placed on a stage (not illustrated). The carrier head 202
may pick up the wafer 200 from the stage using vacuum suction on
the membrane 204 so that the wafer 200 is disposed within an
opening 108 of the retainer ring 100. While the wafer 200 is held
by the carrier head 202, the inner ring 104 may be disposed between
edges of the wafer 200 and the outer ring 102. Thus, the inner ring
104 acts as a buffer between the wafer 200 and the outer ring 102
in order to reduce edge damage (e.g., peeling, scratches, and the
like) caused by collisions between the wafer 200 and the retainer
ring 100, which may occur during processing.
[0023] The carrier head 202 may carry the wafer 200 to a polishing
pad 206 disposed over a platen 208. In an embodiment the polishing
pad 206 may be a single layer or composite layer of materials such
as polyurethane or polyurethane mixed with fillers, and may have a
hardness of about 50 or less on the Shore D Hardness scale. The
surface of the polishing pad 206 may be a roughened surface with
micropores within it. However, any other suitable polishing pad may
alternatively be used to planarize the wafer 200.
[0024] The carrier head 202 may be lowered towards the polishing
pad 206 for polishing the wafer 200. The wafer 200 is positioned so
that the surface to be planarized faces downward towards the
polishing pad 206. Other methods of disposing the wafer 200 over
the polishing pad 206 may be used as well. For example, in another
embodiment, the wafer 200 may be placed on the polishing pad 206
using a different mechanism, and the carrier head 202 may be
lowered onto the wafer 200 while the wafer 200 is on the polishing
pad 206.
[0025] During CMP, the membrane 204 inside the carrier head 202 is
pressurized to push the wafer 200 onto the polishing pad 206. The
wafer 200 is polished by rotating the carrier head 202 and/or the
polishing pad 206/platen 208 as indicated by arrows 210. Although
FIG. 2 illustrates a particular direction of rotation, the carrier
head 202 and/or the platen 208 may be rotated in either directing
during processing, and the rotation direction of the carrier head
202 and/or the platen 208 may or may not be the same. By rotating
the wafer 200 against the polishing pad 206, the polishing pad 206
mechanically grinds a surface of the wafer 200 to remove
undesirable wafer material and planarize the wafer 200.
[0026] During CMP, a chemical slurry is dispensed over a top
surface of the polishing pad 206 by a slurry dispenser (not
illustrated). Although not explicitly illustrated, in an
embodiment, a gap may be disposed between the retainer ring 100 and
the polishing pad 206 during CMP to allow the slurry to be
distributed under a bottom surface (e.g., a surface to be
planarized) of the wafer 200. In other embodiments, the retainer
ring 100 may contact the polishing pad 206, and the retainer ring
100 may include one or more grooves extending from an outer
sidewall to an inner sidewall in order to dispense slurry onto the
wafer 200. As discussed above, a material of the retainer ring 100
(e.g., the outer ring 102 and the inner ring 104) may be selected
to be undamaged by the slurry environment. For example, the inner
ring 104 may comprise porous polyurethane.
[0027] The composition of the slurry depends on the type of
material on the wafer surface undergoing CMP. For example, the
slurry may comprise a first reactant, an abrasive, a first
surfactant, and a solvent. The first reactant may be a chemical
that will chemically react with a material of the wafer 200 (e.g.,
a conductive material) in order to assist the polishing pad 206 in
grinding away the material, such as an oxidizer. In an embodiment
in which the material is tungsten, the first reactant may be
hydrogen peroxide, although any other suitable reactant, such as
hydroxylamine, periodic acid, ammonium persulfate, other
periodates, iodates, peroxomono, sulfates, peroxymonosulfuric acid,
perborates, malonamide, combinations of these, and the like, that
will aid in the removal of the material may alternatively be
utilized. Other reactants may be used in order to remove other
materials. As another example, in an embodiment in which the
material is an oxide, the first reactant may comprise an HNO.sub.3
reactant.
[0028] The abrasive may be any suitable particulate that, in
conjunction with the polishing pad 206, aids in the planarization
of the wafer 200. In an embodiment the abrasive may be silica
(e.g., silicon oxide). However, any other suitable abrasive, such
as aluminum oxide, cerium oxide, polycrystalline diamond, polymer
particles such as polymethacrylate or polymethacryclic,
combinations of these, or the like, may alternatively be utilized
and are fully intended to be included within the scope of the
embodiments.
[0029] The first surfactant may be utilized to help disperse the
first reactant and abrasive within the CMP slurry and also prevent
(or at least reduce) the abrasive from agglomerating during the CMP
process. In an embodiment the first surfactant may include sodium
salts of polyacrylic acid, potassium oleate, sulfosuccinates,
sulfosuccinate derivatives, sulfonated amines, sulfonated amides,
sulfates of alcohols, alkylanyl sulfonates, carboxylated alcohols,
alkylamino propionic acids, alkyliminodipropionic acids, potassium
oleate, sulfosuccinates, sulfosuccinate derivatives, sulfates of
alcohols, alkylanyl sulfonates, carboxylated alcohols, sulfonated
amines, sulfonated amides, alkylamino propionic acids,
alkyliminodipropionic acids, combinations of these, or the like.
However, these embodiments are not intended to be limited to these
surfactants, as any suitable surfactant may alternatively be
utilized as the first surfactant.
[0030] The remainder of the CMP slurry may be a solvent that may be
utilized to combine the first reactant, the abrasive, and the first
surfactant and allow the mixture to be moved and dispersed onto the
polishing pad 206. In an embodiment the solvent of the CMP slurry
may a solvent such as deionized water or an alcohol. However, any
other suitable solvent may alternatively be utilized.
[0031] Furthermore, a pad conditioner arm (not illustrated) may
move a rotating pad conditioning head (not illustrated) in a
sweeping motion over a region of the polishing pad 206 during CMP.
The conditioning head holds a pad conditioner in contact with the
polishing pad 206. The pad conditioner may comprise a substrate
over which an array of abrasive particles, such as diamonds, is
bonded using, for example, electroplating. The pad conditioner may
be used to remove built-up wafer debris and excess slurry from the
polishing pad 206. The pad conditioner may also acts as an abrasive
for the polishing pad 206 to create an appropriate texture against
which the wafer 200 may be mechanically ground.
[0032] The CMP process may be a one-step CMP process (e.g., where a
single polishing pad 206 is used) or a multi-step CMP process. For
example, the polishing pad 206 may be used during a bulk CMP
process. In such embodiments, the wafer 200 may be removed from the
polishing pad 206 and may be transferred to a buffing polishing pad
(not illustrated). The buffing polishing pad may perform a similar
CMP process as described above, with the second polishing pad
grinding away a surface of the wafer 200 and a buffing slurry being
dispersed to aid in the grinding process. The buffing slurry may be
selected based on a material of the wafer 200 being planarized.
[0033] In an embodiment the second polishing pad may be a soft
buffing pad which may planarize the wafer 200 at a slower and more
controlled rate than the first polishing pad 206 while also buffing
and eliminating defects and scratches that may have been caused by
the bulk CMP process. In an embodiment the second polishing pad may
be rotated relative to the wafer 200 while the buffing slurry is
dispensed on the second polishing pad. The buffing CMP process may
be continued until desired materials have been removed from the
surface of the wafer 200. In some embodiments, a timed or optical
end-point detection may be used to determine when to stop the
polishing on the wafer 200.
[0034] During the various CMP processes described above, the wafer
200 is confined within the inner ring 104 during the polishing.
With the retainer ring 100, the softer inner ring 104 absorbs
impact/contact energy and reduces vibrations between the retainer
ring 100 and the wafer 200 during the CMP process and prevents
damage/peeling on the wafer 200. For example, FIG. 3A illustrates a
micrographic view of a semiconductor wafer edge 300 after
processing using a retainer ring without a soft inner ring, and
FIG. 3B illustrates a micrographic view of a semiconductor wafer
edge 350 after processing using a retainer ring having a soft inner
ring (e.g., inner ring 104 as described above). Comparing the edge
300 with the edge 350, fewer defects (e.g., scratches and/or
peeling) are formed in the wafer edge 350 where a soft inner ring
was used than in the wafer edge 300 where the soft inner ring was
omitted.
[0035] FIG. 4 illustrates a process flow 400 of a semiconductor
process in accordance with some embodiments. In step 402, a
retainer ring is provided. Retainer ring includes an outer ring and
an inner ring attached to the outer ring. In some embodiments, the
inner ring comprises a relatively soft, porous material (e.g.,
porous polyurethane), and a material of the inner ring may be
softer than a material of the outer ring. In contrast, the material
of the outer ring may be harder than the material of the inner
ring. For example, the outer ring may comprise polyether ether
ketone (PEEK), polyphenylene sulfide (PPS), any combination
thereof, or any other suitable material.
[0036] The inner ring encircles a hollow, center area of the
retainer ring, and a wafer may be secured in the hollow center area
of the retainer ring during processing. In step 406, a wafer is
positioned within the retainer ring (e.g., within the hollow center
area of the retainer ring). The inner ring may be disposed between
edges of the wafer and the outer ring while the wafer is secured by
the retainer ring. The inner ring may be at least as tall as the
wafer in order to protect wafer edges during processing. In step
406, processing is performed on the wafer while the wafer is
secured by the retainer ring. For example, a CMP process may be
performed while the retainer ring secures the wafer. The retainer
ring may be secured to a polish head during processing in order to
position and rotate the wafer against a polishing pad as described
above. Furthermore, a chemical slurry may be dispensed under the
wafer (e.g., under the retainer ring and/or through grooves in the
retainer ring) during processing. In some embodiments, the material
of the retainer ring may be selected to be resilient to damage from
a chemical slurry environment. In various embodiments, the inner
ring may protect edges of the wafer from colliding with the
relatively hard material of the outer ring during processing. In
embodiments where the inner ring comprises a porous material, the
voids in the material may facilitate shock absorption, which
further reduces damage to the wafer edges. Thus, damage (e.g.,
bevel edge peeling and/or scratches) to the wafer edge may be
advantageously reduced.
[0037] Various embodiments include a retainer ring for securing a
wafer during processing (e.g., a CMP process). The retainer ring
may include an outer ring and an inner ring attached to an inner
sidewall of the outer ring. Both the outer ring and the inner ring
may encircle an opening with the inner ring being disposed between
the outer ring and the opening. The inner ring may comprise a
relatively soft material, which may be porous. During processing,
the inner ring is disposed between a wafer secured by the retainer
ring and the relatively hard material of the outer ring. Thus, the
inner ring may protect edges of the wafer from colliding with the
outer ring. By including an inner ring, wafer bevel peeling and
scratches resulting from collisions between the wafer and the outer
ring can be advantageously reduced. Furthermore, in embodiments
where the inner ring comprises a porous material, the voids within
the inner ring may absorb collision energy and protect the wafer
during processing, which may further reduce manufacturing
defects.
[0038] In accordance with an embodiment, a retainer ring includes
an outer ring encircling an opening and an inner ring attached to
the outer ring. The inner ring is disposed between the opening and
the outer ring. The inner ring includes a softer material than the
outer ring and a plurality of voids within the softer material.
[0039] In accordance with another embodiment, a polishing apparatus
includes a polishing head and a retainer ring attached to the
polishing head. The retainer ring includes an outer ring including
a first material and an inner ring including a porous second
material having a specific gravity less than about 1.0. The porous
second material is softer than the first material. The inner ring
is disposed between edges of a wafer and the outer ring when the
retainer ring secures a wafer.
[0040] In accordance with yet another embodiment, a method for
processing a wafer includes providing a retainer ring having an
outer ring encircling an opening and an inner ring attached to the
outer ring and encircling the opening. The inner ring includes a
different material than the outer ring, and the different material
is porous. The method also includes positioning a wafer in the
opening. The inner ring is disposed between edges of the wafer and
the outer ring. The method also includes processing the wafer while
the wafer is secured by the retainer ring.
[0041] The foregoing outlines features of several embodiments so
that those skilled in the art may better understand the aspects of
the present disclosure. Those skilled in the art should appreciate
that they may readily use the present disclosure as a basis for
designing or modifying other processes and structures for carrying
out the same purposes and/or achieving the same advantages of the
embodiments introduced herein. Those skilled in the art should also
realize that such equivalent constructions do not depart from the
spirit and scope of the present disclosure, and that they may make
various changes, substitutions, and alterations herein without
departing from the spirit and scope of the present disclosure.
* * * * *