U.S. patent application number 15/224471 was filed with the patent office on 2017-11-02 for parallel instruction scheduler for block isa processor.
This patent application is currently assigned to Microsoft Technology Licensing, LLC. The applicant listed for this patent is Microsoft Technology Licensing, LLC. Invention is credited to Jan S. Gray, Aaron L. Smith.
Application Number | 20170315812 15/224471 |
Document ID | / |
Family ID | 60158893 |
Filed Date | 2017-11-02 |
United States Patent
Application |
20170315812 |
Kind Code |
A1 |
Smith; Aaron L. ; et
al. |
November 2, 2017 |
PARALLEL INSTRUCTION SCHEDULER FOR BLOCK ISA PROCESSOR
Abstract
Apparatus and methods are disclosed for implementing block-based
processors, including field programmable gate-array (FPGA)
implementations. In one example of the disclosed technology, an
instruction decoder configured to generate ready state data for a
set of instructions in an instruction block, each of the set of
instructions being associated with a different instruction
identifier encoded in the transactional block and a parallel
instruction scheduler configured to issue an instruction from the
set of instructions based on the decoded ready state data. In some
examples, the parallel instruction scheduler allows for improved
area and energy savings according to the size and type of FPGA
components available.
Inventors: |
Smith; Aaron L.; (Seattle,
WA) ; Gray; Jan S.; (Bellevue, WA) |
|
Applicant: |
Name |
City |
State |
Country |
Type |
Microsoft Technology Licensing, LLC |
Redmond |
WA |
US |
|
|
Assignee: |
Microsoft Technology Licensing,
LLC
Redmond
WA
|
Family ID: |
60158893 |
Appl. No.: |
15/224471 |
Filed: |
July 29, 2016 |
Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
|
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62328976 |
Apr 28, 2016 |
|
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Current U.S.
Class: |
1/1 |
Current CPC
Class: |
G06F 9/3885 20130101;
G06F 9/30181 20130101; G06F 9/3836 20130101; G06F 9/3017 20130101;
G06F 9/3818 20130101; G06F 9/3873 20130101; G06F 9/3855 20130101;
G06F 15/7867 20130101; G06F 9/3005 20130101; G06F 12/0875 20130101;
G06F 9/30185 20130101; G06F 9/3838 20130101; G06F 9/3802 20130101;
G06F 9/3897 20130101; G06F 9/3016 20130101; G06F 9/3889 20130101;
G06F 9/3834 20130101 |
International
Class: |
G06F 9/38 20060101
G06F009/38; G06F 9/38 20060101 G06F009/38; G06F 9/30 20060101
G06F009/30 |
Claims
1. An apparatus comprising a block-based processor, the block-based
processor comprising: an instruction decoder configured to generate
ready state data for a set of instructions in an instruction block,
each of the set of instructions being associated with a different
instruction identifier encoded in the instruction block; and a
parallel instruction scheduler configured to issue an instruction
from the set of instructions based on the decoded ready state
data.
2. The apparatus of claim 1, wherein the parallel instruction
scheduler comprises a scheduler slice for each respective
instruction in the set of instructions.
3. The apparatus of claim 2, wherein the scheduler slice comprises
storage configured to store ready state data for its respective
instruction, and wherein the scheduler slice is further configured
to generate a ready signal indicating that its respective
instruction is ready to issue.
4. The apparatus of claim 2, wherein the scheduler slice is
configured to update active ready state data based in part on event
signals generated during execution of the instruction block.
5. The apparatus of claim 2, wherein the scheduler slice is
configured to update active ready state data based in part on
receiving an instruction identifier indicating that the scheduler
slice's respective instruction has issued.
6. The apparatus of claim 1, wherein the ready state data comprises
decoded ready state data and active ready state data, the decoded
ready state data being invariant for an instruction in an
instruction block, the active ready state data being seeded using
the decoded ready state data as a mask.
7. The apparatus of claim 1, wherein the block-based processor is a
soft core processor implemented with a configurable logic
device.
8. The apparatus of claim 1, wherein the parallel instruction
scheduler is further configured to: in a first clock cycle of the
processor, issue a first instruction and generate a ready signal
that a second instruction is ready to issue, the second instruction
being dependent on the first instruction; and in the next clock
cycle of the processor, issue the second instruction.
9. The apparatus of claim 1, further comprising: a data operand
buffer configured to store operand data for not more than one
instruction per clock cycle; and bypass logic that allows a data
operand for a different instruction to be forwarded to an execution
unit of the processor in the same clock cycle as different data
operand is stored in the data operand buffer.
10. A reconfigurable logic device configured to execute a
block-based processor instruction set, the device comprising: a
plurality of lookup-tables (LUTs); an instruction decoder
configured to generate representations of dependencies for
instructions encoded in an instruction block; a parallel
instruction scheduler configured to generate a ready signal
indicating that dependencies for a respective instruction are
satisfied; and one or more execution units configured to perform
operations specified by the respective instruction after receiving
its ready signal.
11. The reconfigurable logic device of claim 10, wherein the
instruction scheduler is split into two or more banks, each of the
banks being assigned to a different portion of the plurality of
multi-input LUTs.
12. The reconfigurable logic device of claim 10, wherein the
instruction scheduler is implemented with random access memory
(RAM) formed using a portion of the plurality of LUTs.
13. The reconfigurable logic device of claim 10, wherein the
instruction scheduler is coupled to: a decoded instruction word
memory configured to store decoded instruction control data for at
least a portion of the received instructions; and a plurality of
operand buffers configured to store operand data for executing the
received instructions.
14. The reconfigurable logic device of claim 10, wherein the device
is further configured to execute a subsequent instance of an
instruction block by refreshing and re-executing the instruction
block, and wherein the ready state data comprises decoded ready
state information, which is not cleared upon the refreshing and
active ready state data, which is cleared upon the refreshing.
15. The reconfigurable logic device of claim 14, wherein the
scheduler stores the ready state data for each instruction in a set
of flip-flops of the configurable logic device that can be cleared
and/or set with a single signal.
16. A method of forming a block-based processor with a configurable
logic device, the method comprising: producing a configuration
bitstream comprising configuration information for implementing a
circuit for the block-based processor with a configurable logic
device, the circuit for the block-based processor comprising: a
parallel instruction scheduler configured to issue instructions
based on ready state data stored in a memory indexed by an
instruction identifier uniquely identifying each respective
instruction of a transactional instruction block.
17. The method of claim 16, further comprising using a logic
compiler to map portions of the scheduler having N or fewer inputs
to lookup table memories of the configurable logic device having N
or fewer inputs.
18. The method of claim 16, further comprising using a logic
compiler to map portions of the scheduler to a first bank of logic
resources of the configurable logic device and other portions of
the scheduler to a second bank of logic resources of the
configurable logic device.
19. The method of claim 16, further comprising: applying the
configuration bitstream to a configuration port of an integrated
circuit comprising the configurable logic devices; and executing
one or more instruction blocks with the block-based processor.
20. The method of claim 16, further comprising storing the
configuration bitstream in a computer-readable storage device or
memory.
Description
CROSS-REFERENCE TO RELATED APPLICATIONS
[0001] This application claims the benefit of U.S. Provisional
Patent Application No. 62/328,976, entitled "OUT-OF-ORDER
BLOCK-BASED PROCESSORS AND INSTRUCTION SCHEDULERS," filed Apr. 28,
2016, which is incorporated herein by reference in its
entirety.
BACKGROUND
[0002] Microprocessors have benefitted from continuing gains in
transistor count, integrated circuit cost, manufacturing capital,
clock frequency, and energy efficiency due to continued transistor
scaling predicted by Moore's law, with little change in associated
processor Instruction Set Architectures (ISAs). However, the
benefits realized from photolithographic scaling, which drove the
semiconductor industry over the last 40 years, are slowing or even
reversing. Reduced Instruction Set Computing (RISC) architectures
have been the dominant paradigm in processor design for many years.
Out-of-order superscalar implementations have not exhibited
sustained improvement in area or performance. Accordingly, there is
ample opportunity for improvements in processor ISAs to extend
performance improvements.
SUMMARY
[0003] Methods, apparatus, and computer-readable storage devices
are disclosed for configuring, operating, and compiling code for,
block-based processor architectures (BB-ISAs), including explicit
data graph execution (EDGE) architectures. The microarchitecture of
the processors includes a parallel instruction scheduler. The
described techniques and tools for solutions for, e.g., improving
processor performance and/or reducing energy consumption can be
implemented separately, or in various combinations with each other.
As will be described more fully below, the described techniques and
tools can be implemented in a digital signal processor,
microprocessor, application-specific integrated circuit (ASIC), a
soft processor (e.g., a microprocessor core implemented in a field
programmable gate array (FPGA) using reconfigurable logic),
programmable logic, or other suitable logic circuitry. As will be
readily apparent to one of ordinary skill in the art, the disclosed
technology can be implemented in various computing platforms,
including, but not limited to, servers, mainframes, cellphones,
smartphones, handheld devices, handheld computers, personal digital
assistants (PDAs), touch screen tablet devices, tablet computers,
wearable computers, and laptop computers.
[0004] Soft processor implementations of block-based processor
architectures can improve design productivity. For example,
descriptions of a block-based soft-processor written in a suitable
description language (e.g., C, SystemC, SystemVerilog, or Verilog)
can undergo logic synthesized to generate a gate-level netlist
mapped to an FPGA. A bitstream is generated for the FPGA that is
used to program the FPGA. A costly initial port of software into
hardware instead becomes a simple cross-compile targeting the soft
processors, and most design turns are quick recompiles. Application
bottlenecks can then be offloaded to custom hardware exposed as new
instructions, function units, autonomous accelerators, memories, or
interconnects.
[0005] Certain examples of the disclosed technology allow for the
configuration of high instruction level parallelism (ILP),
out-of-order (OoO) superscalar soft processors without reduced
complexity and overhead. In some examples, an Explicit Data Graph
Execution (EDGE) instruction set architecture is provided for area
and energy efficient high ILP execution. Together the EDGE
architecture and its compiler finesse away much of the register
renaming, CAMs, and complexity, enabling an out-of-order processor
for only a few hundred FPGA lookup tables ("LUTs") more than an
in-order scalar RISC.
[0006] This disclosed technology introduces an EDGE ISA and
explores how EDGE microarchitectures compare to in-order RISCs.
Methods and apparatus are disclosed for building small, fast
dataflow instruction schedulers in FPGAs.
BRIEF DESCRIPTION OF THE DRAWINGS
[0007] FIG. 1 illustrates an example block-based processor
including multiple processor cores as can be employed according to
some examples of the disclosed technology.
[0008] FIG. 2 illustrates an example microarchitecture for
implementing a block-based processor as can be used in certain
examples of the disclosed technology.
[0009] FIG. 3 is a block diagram outlining an example FPGA
microarchitecture as can be used in some examples of the disclosed
technology.
[0010] FIG. 4 illustrates example reconfigurable logic in a
reconfigurable logic block as can be used in certain examples of
the disclosed technology.
[0011] FIG. 5 illustrates example block-based processor headers and
instructions as can be used in some examples of the disclosed
technology.
[0012] FIG. 6 illustrates an example source code portion and
corresponding instruction blocks as can be used in certain examples
of the disclosed technology.
[0013] FIG. 7 illustrates an example of instruction formats that
can be used for certain examples of block-based processors
according to the disclosed technology.
[0014] FIG. 8 is a flow chart illustrating an example of a
progression of execution states of a processor core in a
block-based processor, as can be used in certain examples of the
disclosed technology.
[0015] FIG. 9 is a block diagram illustrating an example
implementation of a parallel instruction scheduler, as can be used
in certain examples of the disclosed technology.
[0016] FIG. 10 is a floorplan of an FPGA implementation of a
parallel instruction scheduler, as can be implemented in certain
examples of the disclosed technology.
[0017] FIG. 11 is a block diagram illustrating an example
configuration including a block-based processor and memory, as can
be used in certain examples of the disclosed technology.
[0018] FIG. 12 is a flow chart illustrating an example method of
issuing instructions using a parallel instruction scheduler, as can
be used in certain examples of the disclosed technology.
[0019] FIG. 13 is a flow chart outlining an example method of
issuing and executing instructions with a parallel instruction
scheduler, as can be performed in certain examples of the disclosed
technology.
[0020] FIG. 14 is a flow chart outlining an example method of
producing a configuration bit-stream for implementing a block-based
processor with a parallel instruction scheduler, as can be
performed in certain examples of the disclosed technology.
[0021] FIG. 15 is a block diagram illustrating a suitable computing
environment for implementing certain embodiments of the disclosed
technology.
DETAILED DESCRIPTION
I. General Considerations
[0022] This disclosure is set forth in the context of
representative embodiments that are not intended to be limiting in
any way.
[0023] As used in this application the singular forms "a," "an,"
and "the" include the plural forms unless the context clearly
dictates otherwise. Additionally, the term "includes" means
"comprises." Further, the term "coupled" encompasses mechanical,
electrical, magnetic, optical, as well as other practical ways of
coupling or linking items together, and does not exclude the
presence of intermediate elements between the coupled items.
Furthermore, as used herein, the term "and/or" means any one item
or combination of items in the phrase.
[0024] The systems, methods, and apparatus described herein should
not be construed as being limiting in any way. Instead, this
disclosure is directed toward all novel and non-obvious features
and aspects of the various disclosed embodiments, alone and in
various combinations and subcombinations with one another. The
disclosed systems, methods, and apparatus are not limited to any
specific aspect or feature or combinations thereof, nor do the
disclosed things and methods require that any one or more specific
advantages be present or problems be solved. Furthermore, any
features or aspects of the disclosed embodiments can be used in
various combinations and subcombinations with one another.
[0025] Although the operations of some of the disclosed methods are
described in a particular, sequential order for convenient
presentation, it should be understood that this manner of
description encompasses rearrangement, unless a particular ordering
is required by specific language set forth below. For example,
operations described sequentially may in some cases be rearranged
or performed concurrently. Moreover, for the sake of simplicity,
the attached figures may not show the various ways in which the
disclosed things and methods can be used in conjunction with other
things and methods. Additionally, the description sometimes uses
terms like "produce," "generate," "display," "receive," "emit,"
"verify," "execute," and "initiate" to describe the disclosed
methods. These terms are high-level descriptions of the actual
operations that are performed. The actual operations that
correspond to these terms will vary depending on the particular
implementation and are readily discernible by one of ordinary skill
in the art.
[0026] Theories of operation, scientific principles, or other
theoretical descriptions presented herein in reference to the
apparatus or methods of this disclosure have been provided for the
purposes of better understanding and are not intended to be
limiting in scope. The apparatus and methods in the appended claims
are not limited to those apparatus and methods that function in the
manner described by such theories of operation.
[0027] Any of the disclosed methods can be implemented as
computer-executable instructions stored on one or more
computer-readable media (e.g., computer-readable media, such as one
or more optical media discs, volatile memory components (such as
DRAM or SRAM), or nonvolatile memory components (such as hard
drives)) and executed on a computer (e.g., any commercially
available computer, including smart phones or other mobile devices
that include computing hardware). Any of the computer-executable
instructions for implementing the disclosed techniques, as well as
any data created and used during implementation of the disclosed
embodiments, can be stored on one or more computer-readable media
(e.g., computer-readable storage media). The computer-executable
instructions can be part of, for example, a dedicated software
application or a software application that is accessed or
downloaded via a web browser or other software application (such as
a remote computing application). Such software can be executed, for
example, on a single local computer (e.g., with general-purpose
and/or block-based processors executing on any suitable
commercially available computer) or in a network environment (e.g.,
via the Internet, a wide-area network, a local-area network, a
client-server network (such as a cloud computing network), or other
such network) using one or more network computers.
[0028] For clarity, only certain selected aspects of the
software-based implementations are described. Other details that
are well known in the art are omitted. For example, it should be
understood that the disclosed technology is not limited to any
specific computer language or program. For instance, the disclosed
technology can be implemented by software written in C, C++, Java,
or any other suitable programming language. Likewise, the disclosed
technology is not limited to any particular computer or type of
hardware. Certain details of suitable computers and hardware are
well-known and need not be set forth in detail in this
disclosure.
[0029] Furthermore, any of the software-based embodiments
(comprising, for example, computer-executable instructions for
causing a computer to perform any of the disclosed methods) can be
uploaded, downloaded, or remotely accessed through a suitable
communication means. Such suitable communication means include, for
example, the Internet, the World Wide Web, an intranet, software
applications, cable (including fiber optic cable), magnetic
communications, electromagnetic communications (including RF,
microwave, and infrared communications), electronic communications,
or other such communication means.
II. Introduction to the Disclosed Technologies
[0030] Superscalar out-of-order microarchitectures employ
substantial circuit resources to rename registers, schedule
instructions in dataflow order, clean up after miss-speculation,
and retire results in-order for precise exceptions. This includes
expensive circuits, such as deep, many-ported register files,
many-ported content-accessible memories (CAMs) for dataflow
instruction scheduling wakeup, and many-wide bus multiplexers and
bypass networks, all of which are resource intensive. For example,
FPGA-based implementations of multi-read, multi-write RAMs
typically require a mix of replication, multi-cycle operation,
clock doubling, bank interleaving, live-value tables, and other
expensive techniques.
[0031] The disclosed technologies can realize performance
enhancement through application of techniques including high
instruction-level parallelism (ILP), out-of-order (OoO),
superscalar execution, while avoiding substantial complexity and
overhead in both processor hardware and associated software. In
some examples of the disclosed technology, a block-based processor
uses an EDGE ISA designed for area- and energy-efficient, high-ILP
execution. In some examples, use of EDGE architectures and
associated compilers finesses away much of the register renaming,
CAMs, and complexity.
[0032] In certain examples of the disclosed technology, an EDGE ISA
can eliminate the need for one or more complex architectural
features, including register renaming, dataflow analysis,
misspeculation recovery, and in-order retirement while supporting
mainstream programming languages such as C and C++. In certain
examples of the disclosed technology, a block-based processor
executes a plurality of two or more instructions as an atomic
block. Block-based instructions can be used to express semantics of
program data flow and/or instruction flow in a more explicit
fashion, allowing for improved compiler and processor performance.
In certain examples of the disclosed technology, an explicit data
graph execution instruction set architecture (EDGE ISA) includes
information about program control flow that can be used to improve
detection of improper control flow instructions, thereby increasing
performance, saving memory resources, and/or and saving energy.
[0033] In some examples of the disclosed technology, instructions
organized within instruction blocks are fetched, executed, and
committed atomically. Instructions inside blocks execute in
dataflow order, which reduces or eliminates using register renaming
and provides power-efficient OoO execution. A compiler can be used
to explicitly encode data dependencies through the ISA, reducing or
eliminating burdening processor core control logic from
rediscovering dependencies at runtime. Using predicated execution,
intra-block branches can be converted to dataflow instructions, and
dependencies, other than memory dependencies, can be limited to
direct data dependencies. Disclosed target form encoding techniques
allow instructions within a block to communicate their operands
directly via operand buffers, reducing accesses to a power-hungry,
multi-ported physical register files.
[0034] Between instruction blocks, instructions can communicate
using memory and registers. Thus, by utilizing a hybrid dataflow
execution model, EDGE architectures can still support imperative
programming languages and sequential memory semantics, but
desirably also enjoy the benefits of out-of-order execution with
near in-order power efficiency and complexity.
III. Example Block-Based Processor
[0035] FIG. 1 is a block diagram 10 of a block-based processor 100
as can be implemented in some examples of the disclosed technology.
The processor 100 is configured to execute atomic blocks of
instructions according to an instruction set architecture (ISA),
which describes a number of aspects of processor operation,
including a register model, a number of defined operations
performed by block-based instructions, a memory model, interrupts,
and other architectural features. The block-based processor
includes a plurality of one or more processing cores 110, including
a processor core 111. The block-based processor can be implemented
in as a custom or application-specific integrated circuit (e.g.,
including a system-on-chip (SoC) integrated circuit), as a field
programmable gate array (FPGA) or other reconfigurable logic, or as
a soft processor virtual machine hosted by a physical general
purpose processor.
[0036] As shown in FIG. 1, the processor cores are connected to
each other via core interconnect 120. The core interconnect 120
carries data and control signals between individual ones of the
cores 110, a memory interface 140, and an input/output (I/O)
interface 150. The core interconnect 120 can transmit and receive
signals using electrical, optical, magnetic, or other suitable
communication technology and can provide communication connections
arranged according to a number of different topologies, depending
on a particular desired configuration. For example, the core
interconnect 120 can have a crossbar, a bus, a point-to-point bus,
or other suitable topology. In some examples, any one of the cores
110 can be connected to any of the other cores, while in other
examples, some cores are only connected to a subset of the other
cores. For example, each core may only be connected to a nearest 4,
8, or 20 neighboring cores. The core interconnect 120 can be used
to transmit input/output data to and from the cores, as well as
transmit control signals and other information signals to and from
the cores. For example, each of the cores 110 can receive and
transmit semaphores that indicate the execution status of
instructions currently being executed by each of the respective
cores. In some examples, the core interconnect 120 is implemented
as wires connecting the cores 110, and memory system, while in
other examples, the core interconnect can include circuitry for
multiplexing data signals on the interconnect wire(s), switch
and/or routing components, including active signal drivers and
repeaters, or other suitable circuitry. In some examples of the
disclosed technology, signals transmitted within and to/from the
processor 100 are not limited to full swing electrical digital
signals, but the processor can be configured to include
differential signals, pulsed signals, or other suitable signals for
transmitting data and control signals.
[0037] In the example of FIG. 1, the memory interface 140 of the
processor includes interface logic that is used to connect to
memory 145, for example, memory located on another integrated
circuit besides the processor 100 (e.g., the memory can be static
RAM (SRAM) or dynamic RAM (DRAM)), or memory embedded on the same
integrated circuit as the processor (e.g., embedded SRAM or DRAM
(eDRAM)). The memory interface 140 and/or the main memory can
include caches (e.g., n-way or associative caches) to improve
memory access performance In some examples the cache is implemented
using static RAM (SRAM) and the main memory 145 is implemented
using dynamic RAM (DRAM). In some examples the memory interface 140
is included on the same integrated circuit as the other components
of the processor 100. In some examples, the memory interface 140
includes a direct memory access (DMA) controller allowing transfer
of blocks of data in memory without using register file(s) and/or
the processor 100. In some examples, the memory interface 140
manages allocation of virtual memory, expanding the available main
memory 145. In some examples, support for bypassing cache
structures or for ensuring cache coherency when performing memory
synchronization operations (e.g., handling contention issues or
shared memory between plural different threads, processes, or
processors) are provided by the memory interface 140 and/or
respective cache structures.
[0038] The I/O interface 150 includes circuitry for receiving and
sending input and output signals to other components 155, such as
hardware interrupts, system control signals, peripheral interfaces,
co-processor control and/or data signals (e.g., signals for a
graphics processing unit, floating point coprocessor, physics
processing unit, digital signal processor, or other co-processing
components), clock signals, semaphores, or other suitable I/O
signals. The I/O signals may be synchronous or asynchronous. In
some examples, all or a portion of the I/O interface is implemented
using memory-mapped I/O techniques in conjunction with the memory
interface 140. In some examples the I/O signal implementation is
not limited to full swing electrical digital signals, but the I/O
interface 150 can be configured to provide differential signals,
pulsed signals, or other suitable signals for transmitting data and
control signals.
[0039] The block-based processor 100 can also include a control
unit 160. The control unit 160 supervises operation of the
processor 100. Operations that can be performed by the control unit
160 can include allocation and de-allocation of cores for
performing instruction processing, control of input data and output
data between any of the cores, register files, the memory interface
140, and/or the I/O interface 150, modification of execution flow,
and verifying target location(s) of branch instructions,
instruction headers, and other changes in control flow. The control
unit 160 can generate and control the processor according to
control flow and metadata information representing exit points and
control flow probabilities for instruction blocks.
[0040] The control unit 160 can also process hardware interrupts,
and control reading and writing of special system registers, for
example a program counter stored in one or more register file(s).
In some examples of the disclosed technology, the control unit 160
is at least partially implemented using one or more of the
processing cores 110, while in other examples, the control unit 160
is implemented using a non-block-based processing core (e.g., a
general-purpose RISC processing core coupled to memory, a hard
macro processor block provided in an FPGA, or a general purpose
soft processor). In some examples, the control unit 160 is
implemented at least in part using one or more of: hardwired finite
state machines, programmable microcode, programmable gate arrays,
or other suitable control circuits. In alternative examples,
control unit functionality can be performed by one or more of the
cores 110.
[0041] The control unit 160 includes a number of schedulers 165-168
that are used to control instruction pipelines of the processor
cores 110. In other examples, schedulers can be arranged so that
they are contained with each individual processor core. As used
herein, scheduler block allocation refers to directing operation of
an instruction blocks, including initiating instruction block
mapping, fetching, decoding, execution, committing, aborting,
idling, and refreshing an instruction block. Further, instruction
scheduling refers to scheduling the issuance and execution of
instructions within an instruction block. For example, based on
instruction dependencies and data indicating a relative ordering
for memory access instructions, the control unit 160 can determine
which instruction(s) in an instruction block are ready to issue and
initiate issuance and execution of the instructions. Processor
cores 110 are assigned to instruction blocks during instruction
block mapping. The recited stages of instruction operation are for
illustrative purposes and in some examples of the disclosed
technology, certain operations can be combined, omitted, separated
into multiple operations, or additional operations added. Each of
the schedulers 165-168 schedules the flow of instructions,
including allocation and de-allocation of cores for performing
instruction processing, control of input data and output data
between any of the cores, register files, the memory interface 140,
and/or the I/O interface 150.
[0042] The block-based processor 100 also includes a clock
generator 170, which distributes one or more clock signals to
various components within the processor (e.g., the cores 110,
interconnect 120, memory interface 140, and I/O interface 150). In
some examples of the disclosed technology, all of the components
share a common clock, while in other examples different components
use a different clock, for example, a clock signal having differing
clock frequencies. In some examples, a portion of the clock is
gated to allowing power savings when some of the processor
components are not in use. In some examples, the clock signals are
generated using a phase-locked loop (PLL) to generate a signal of
fixed, constant frequency and duty cycle. Circuitry that receives
the clock signals can be triggered on a single edge (e.g., a rising
edge) while in other examples, at least some of the receiving
circuitry is triggered by rising and falling clock edges. In some
examples, the clock signal can be transmitted optically or
wirelessly.
IV. Example Block-Based Processor Microarchitecture
[0043] FIG. 2 is a block diagram further detailing an example
microarchitecture 200 for implementing the block-based processor
100, and in particular, an instance of one of the block-based
processor cores, as can be used in certain examples of the
disclosed technology. For ease of explanation, the exemplary
microarchitecture has five pipeline stages including: instruction
fetch (IF), decode (DC), issue, including operand fetch (IS),
execute (EX), and memory/data access (LS). However, it will be
readily understood by one of ordinary skill in the relevant art
that modifications to the illustrated microarchitecture, such as
adding/removing stages, adding/removing units that perform
operations, and other implementation details can be modified to
suit a particular application for a block-based processor.
[0044] As shown in FIG. 2, the processor core includes an
instruction cache 210 that is coupled to an instruction decoder
220. The instruction cache 210 is configured to receive block-based
processor instructions from a memory. In some FPGA implementations,
the instruction cache can be implemented by a dual read port, dual
write port, 18 or 36 Kb (kilobit), 32 bit wide block RAM. In some
examples, the physical block RAM is configured to operate as two or
more smaller block RAMs.
[0045] The processor core further includes an instruction window
230, which includes an instruction scheduler 235, a decoded
instruction store 236, and a plurality of operand buffers 239. In
FPGA implementations, each of these instruction window components
230 can be implemented including the use of LUT RAM (e.g., with
SRAM configured as lookup tables) or BRAM (block RAM). The
instruction scheduler 235 can send an instruction identifier
(instruction ID or IID) for an instruction to the decoded
instruction store 236 and the operand buffers 239 as a control
signal. As discussed further below, each instruction in an
instruction block has an associated instruction identifier that
uniquely identifies the instruction within the instruction block.
In some examples, instruction targets for sending the result of
executing an instruction are encoded in the instruction. In this
way, dependencies between instructions can be tracked using the
instruction identifier instead of monitoring register dependencies.
In some examples, the processor core can include two or more
instruction windows. In some examples, the processor core can
include one instruction window with multiple block contexts.
[0046] As will be discussed further below, the microarchitecture
200 includes a register file 290 that stores data for registers
defined in the block-based processor architecture, and can have one
or more read ports and one or more write ports. Because an
instruction block executes on a transactional basis, changes to
register values made by an instance of an instruction block are not
visible to the same instance; the register writes will be committed
upon completing execution of the instruction block.
[0047] The decoded instruction store 236 stores decoded signals for
controlling operation of hardware components in the processor
pipeline. For example, a 32-bit instruction may be decoded into
128-bits of decoded instruction data. The decoded instruction data
is generated by the decoder 220 after an instruction is fetched.
The operand buffers 239 store operands (e.g., register values
received from the register file, data received from memory,
immediate operands coded within an instruction, operands calculated
by an earlier-issued instruction, or other operand values) until
their respective decoded instructions are ready to execute.
Instruction operands and predicates for the execute phase of the
pipeline are read from the operand buffers 239, respectively, not
(directly, at least) from the register file 290. The instruction
window 230 can include a buffer for predicates directed to an
instruction, including wired-OR logic for combining predicates sent
to an instruction by multiple instructions.
[0048] In some examples, all of the instruction operands, except
for register read operations, are read from the operand buffers 239
instead of the register file. In some examples the values are
maintained until the instruction issues and the operand is
communicated to the execution pipeline. In some FPGA examples, the
decoded instruction store 236 and operand buffers 239 are
implemented with a plurality of LUT RAMs.
[0049] The instruction scheduler 235 maintains a record of ready
state of each decoded instruction's dependencies (e.g., the
instruction's predicate and data operands). When all of the
instruction's dependencies (if any) are satisfied, the instruction
wakes up and is ready to issue. In some examples, the lowest
numbered ready instruction ID is selected each pipeline clock cycle
and its decoded instruction data and input operands are read.
Besides the data mux and function unit control signals, the decoded
instruction data can encode up to two ready events in the
illustrated example. The instruction scheduler 235 accepts these
and/or events from other sources (selected for input to the
scheduler on inputs T0 and T1 with multiplexers 237 and 238,
respectively) and updates the ready state of other instructions in
the window. Thus dataflow execution proceeds, starting with the
instruction block's ready zero-input instructions, then
instructions that these instructions target, and so forth. Some
instructions are ready to issue immediately (e.g., move immediate
instructions) as they have no dependencies. Depending on the ISA,
control structures, and other factors, the decoded instruction
store 236 is about 100 bits wide in some examples, and includes
information on instruction dependencies, including data indicating
which target instruction(s)'s active ready state will be set as a
result of issuing the instruction.
[0050] As used herein, ready state refers to processor state that
indicates, for a given instruction, whether and which of its
operands (if any) are ready, and whether the instruction itself is
now ready for issue. In some examples, ready state includes decoded
ready state and active ready state. Decoded ready state data is
initialized by decoding instruction(s). Active ready state
represents the set of input operands of an instruction that have
been evaluated so far during the execution of the current instance
of an instruction block. A respective instruction's active ready
state is set by executing instruction(s) which target, for example,
the left, right, and/or predicate operands of the respective
instruction.
[0051] Attributes of the instruction window 230 and instruction
scheduler 235, such as area, clock period, and capabilities can
have significant impact to the realized performance of an EDGE core
and the throughput of an EDGE multiprocessor. In some examples, the
front end (IF, DC) portions of the microarchitecture can run
decoupled from the back end portions of the microarchitecture (IS,
EX, LS). In some FPGA implementations, the instruction window 230
is configured to fetch and decode two instructions per clock into
the instruction window.
[0052] The instruction scheduler 235 has diverse functionality and
requirements. It can be highly concurrent. Each clock cycle, the
instruction decoder 220 writes decoded ready state and decoded
instruction data for one or more instructions into the instruction
window 230. Each clock cycle, the instruction scheduler 235 selects
the next instruction(s) to issue, and in response the back end
sends ready events, for example, target ready events targeting a
specific instruction's input slot (e.g., predicate slot, right
operand (OP0), or left operand (OP1)), or broadcast ready events
targeting all instructions waiting on a broadcast ID. These events
cause per-instruction active ready state bits to be set that,
together with the decoded ready state, can be used to signal that
the corresponding instruction is ready to issue. The instruction
scheduler 235 sometimes accepts events for target instructions
which have not yet been decoded, and the scheduler can also can
also inhibit reissue of issued ready instructions.
[0053] Control circuits (e.g., signals generated using the decoded
instruction store 236) in the instruction window 230 are used to
generate control signals to regulate core operation (including,
e.g., control of datapath and multiplexer select signals) and to
schedule the flow of instructions within the core. This can include
generating and using memory access instruction encodings,
allocation and de-allocation of cores for performing instruction
processing, control of input data and output data between any of
the cores 110, register files, the memory interface 140, and/or the
I/O interface 150.
[0054] In some examples, the instruction scheduler 235 is
implemented as a finite state machine coupled to other instruction
window logic. In some examples, the instruction scheduler is mapped
to one or more banks of RAM in an FPGA, and can be implemented with
block RAM, LUT RAM, or other reconfigurable RAM. As will be readily
apparent to one of ordinary skill in the relevant art, other
circuit structures, implemented in an integrated circuit,
programmable logic, or other suitable logic can be used to
implement hardware for the instruction scheduler 235. In some
examples of the disclosed technology, front-end pipeline stages IF
and DC can run decoupled from the back-end pipelines stages (IS,
EX, LS).
[0055] In the example of FIG. 2, the operand buffers 239 send the
data operands, which can be designated left operand (LOP) and right
operand (ROP) for convenience, to a set of execution state pipeline
registers 245 via one or more switches (e.g., multiplexers 241 and
242). These operands can also be referred to as OP1 and OP0,
respectively. A first router 240 is used to send data from the
operand buffers 239 to one or more of the functional units 250,
which can include but are not limited to, integer ALUs (arithmetic
logic units) (e.g., integer ALUs 255), floating point units (e.g.,
floating point ALU 256), shift/rotate logic (e.g., barrel shifter
257), or other suitable execution units, which can including
graphics functions, physics functions, and other mathematical
operations. In some examples, a programmable execution unit 258 can
be reconfigured to implement a number of different arbitrary
functions (e.g., a priori or at runtime).
[0056] Data from the functional units 250 can then be routed
through a second router (not shown) to a set of load/store pipeline
registers 260, to a load/store queue 270 (e.g., for performing
memory load and memory store operations), or fed back to the
execution pipeline registers, thereby bypassing the operand buffers
239. The load/store queue 270 is coupled to a data cache 275 that
caches data for memory operations. The outputs of the data cache
275, and the load/store pipelines registers 260 can be sent to a
third router 280, which in turn sends data to the register file
290, the operand buffers 239, and/or the execution pipeline
registers 245, according to the instruction being executed in the
pipeline stage.
[0057] When execution of an instruction block is complete, the
instruction block is designated as "committed" and signals from the
control outputs can in turn can be used by other cores within the
block-based processor 100 and/or by the control unit 160 to
initiate scheduling, fetching, and execution of other instruction
blocks.
[0058] As will be readily understood to one of ordinary skill in
the relevant art, the components within an individual core are not
limited to those shown in FIG. 2, but can be varied according to
the requirements of a particular application. For example, a core
may have fewer or more instruction windows, a single instruction
decoder might be shared by two or more instruction windows, and the
number of and type of functional units used can be varied,
depending on the particular targeted application for the
block-based processor. Other considerations that apply in selecting
and allocating resources with an instruction core include
performance requirements, energy usage requirements, integrated
circuit die, process technology, and/or cost.
[0059] It will be readily apparent to one of ordinary skill in the
relevant art that trade-offs can be made in processor performance
by the design and allocation of resources within the instruction
window and control unit of the processor cores 110. The area, clock
period, capabilities, and limitations substantially determine the
realized performance of the individual cores 110 and the throughput
of the block-based processor 100.
[0060] Updates to the visible architectural state of the processor
(such as to the register file 290 and the memory) affected by the
executed instructions can be buffered locally within the core until
the instructions are committed. The control circuitry can determine
when instructions are ready to be committed, sequence the commit
logic, and issue a commit signal. For example, a commit phase for
an instruction block can begin when all register writes are
buffered, all writes to memory (including unconditional and
conditional stores) are buffered, and a branch target is
calculated. The instruction block can be committed when updates to
the visible architectural state are complete. For example, an
instruction block can be committed when the register writes are
written to as the register file, the stores are sent to a
load/store unit or memory controller, and the commit signal is
generated. The control circuit also controls, at least in part,
allocation of functional units to the instructions window.
[0061] Because the instruction block is committed (or aborted) as
an atomic transactional unit, it should be noted that results of
certain operations are not available to instructions within an
instruction block. This is in contrast to RISC and CISC
architectures that provide results visible on an individual,
instruction-by-instruction basis. Thus, additional techniques are
disclosed for supporting memory synchronization and other memory
operations in a block-based processor environment.
[0062] In some examples, block-based instructions can be
non-predicated, or predicated true or false. A predicated
instruction does not become ready until it is targeted by another
instruction's predicate result, and that result matches the
predicate condition. If the instruction's predicate does not match,
then the instruction never issues.
[0063] In some examples, upon branching to a new instruction block,
all instruction window ready state (stored in the instruction
scheduler 235) is flash cleared (block reset). However when a block
branches back to itself (block refresh), only active ready state is
cleared; the decoded ready state is preserved so that it is not
necessary to re-fetch and decode the blocks instructions. Thus,
refresh can be used to save time and energy in loops, instead of
performing a block reset.
[0064] Since some software critical paths include a single chain of
dependent instructions (for example, instruction A targets
instruction B, which in turn targets instruction C), it is often
desirable that the dataflow scheduler not add pipeline bubbles for
successive back-to-back instruction wakeup. In such cases, the
IS-stage ready-issue-target-ready pipeline recurrence should
complete in one cycle, assuming that this does not severely affect
clock frequency.
[0065] Instructions such as ADD have a latency of one cycle. With
EX-stage result forwarding, the scheduler can wake their targets'
instructions in the IS-stage, even before the instruction
completes. Other instruction results may await ALU comparisons,
take multiple cycles, or have unknown latency. These instructions
wait until later to wake their targets.
[0066] Finally, the scheduler design can be scalable across a
spectrum of EDGE ISAs. In some examples, each pipeline cycle can
accept from one to four decoded instructions and from two to four
target ready events, and issue one to two instructions per
cycle.
[0067] A number of different technologies can be used to implement
the instruction scheduler 235. For example, the scheduler 235 can
be implemented as a parallel scheduler, where instructions' ready
state is explicitly represented in FPGA D-type flip-flops (FFs),
and in which the ready status of every instruction is reevaluated
each cycle. In other examples, the instruction scheduler 235 can be
implemented as a more compact incremental scheduler that keeps
ready state in LUT RAM and which updates ready status of about two
to four target instructions per cycle.
[0068] The register file 290 may include two or more write ports
for storing data in the register file, as well as having a
plurality of read ports for reading data from individual registers
within the register file. In some examples, a single instruction
window (e.g., instruction window 230) can access only one port of
the register file at a time, while in other examples, the
instruction window 230 can access one read port and one write port,
or can access two or more read ports and/or write ports
simultaneously. In some examples, the microarchitecture is
configured such that not all the read ports of the register 290 can
use the bypass mechanism. For the example microarchitecture 200
shown in FIG. 2, the register file can send register data on the
bypass path to one of the multiplexers 242 for the operand OP0, but
not operand OP1. Thus, for multiple register reads in one cycle,
only one operand can use the bypass, while the other register read
results are sent to the operand buffers 239, which inserts an extra
clock cycle in the instruction pipeline.
[0069] In some examples, the register file 290 can include 64
registers, each of the registers holding a word of 32 bits of data.
(For convenient explanation, this application will refer to 32-bits
of data as a word, unless otherwise specified. Suitable processors
according to the disclosed technology could operate with 8-, 16-,
64-, 128-, 256-bit, or another number of bits words) In some
examples, some of the registers within the register file 290 may be
allocated to special purposes. For example, some of the registers
can be dedicated as system registers examples of which include
registers storing constant values (e.g., an all zero word), program
counter(s) (PC), which indicate the current address of a program
thread that is being executed, a physical core number, a logical
core number, a core assignment topology, core control flags,
execution flags, a processor topology, or other suitable dedicated
purpose. In some examples, the register file 290 is implemented as
an array of flip-flops, while in other examples, the register file
can be implemented using latches, SRAM, or other forms of memory
storage. The ISA specification for a given processor specifies how
registers within the register file 290 are defined and used.
V. Example Field Programmable Gate Array Architecture
[0070] FIG. 3 is a block diagram 300 that depicts an example field
programmable gate array (FPGA) architecture that is configured to
implement certain examples of the disclosed technology. For
example, the block-based processor 100 discussed above regarding
FIG. 1, including those examples that used the microarchitecture
200 depicted in FIG. 2 can be mapped to the FPGA architecture of
FIG. 3.
[0071] The FPGA includes an array of reconfigurable logic blocks
arranged in an array. For example, the FPGA includes a first row of
logic blocks, including logic blocks 310, 311, and 319, and a
second row of logic blocks including logic blocks 320, 321, and
329. Each of the logic blocks includes logic that can be
reconfigured to implement arbitrary logic functions and can also
include sequential logic elements such as latches, flip-flops, and
memories. The logic blocks are interconnected to each other using a
routing fabric that includes a number of interconnect switches that
can also be programmable. For example, there is a first row of
switch blocks 330, 331, 332, etc., positioned between the first row
of reconfigurable logic blocks and the second row of reconfigurable
logic blocks. The switches can be configured in order to change
wire connections that carry signals between the reconfigurable
logic blocks. For example, instructions schedulers, functional
units, pipeline buffers, and operand buffers can be mapped to the
logic blocks connected using the switch blocks of FIG. 3.
[0072] The FPGA also includes a number of more complex components.
For example, the logic block includes a number of block RAMs, for
example, block RAM 340 and block RAM 349. The block RAMs typically
contain a larger number of memory bits, for example, a few thousand
memory bits that are accessed by applying an address to the memory,
and reading from one or more read ports. In some examples, the
block RAMs can include two or more write ports and two or more read
ports. In other examples, the block RAMs may only have a single
read and/or a single write port. While the block RAMs are typically
accessed by applying an address and reading corresponding data, in
some examples, the block RAMs can be configured with additional
circuitry that allows for implementation of more complex functions
including shift registers and First-In First-Out (FIFO)
buffers.
[0073] The illustrated FPGA also includes a number of hard macro
blocks including hard macro block 350 and hard macro block 359.
These macro blocks can include more complex functionality such as
processor functionality, digital signal processing functionality,
accelerators, or other functions deemed to be desirable. The FPGA
is further surrounded by an I/O ring 360 that can be coupled to the
logic blocks, the block rams, and/or the hard macro blocks in order
to receive and send signals to components away from the FPGA. In
some examples, the I/O signals are full rail voltage signals, while
other examples, differential signals are used. In some examples,
the I/O ports can be multiplexed (e.g. time-multiplexed) in order
to support input and output of more signals than the number of pins
available on the FPGA.
[0074] While many examples of FPGAs are typically reconfigurable an
arbitrary number of times through the use of electrically erasable
memories, in other examples, one-time programmable logic elements
can be used. For example, the logic blocks and switches can be
programmed with the use of fuses, anti-fuses, or with a ROM mask to
program a logic function once that is not easily reversible.
[0075] In the reconfigurable case, the FPGA typically has a
configuration port that receives data according to a file dubbed a
bitstream, or a configuration bitstream. The bitstream data is read
into the device and used to program and configure the logic blocks,
the switches, the block rams, and/or the hard macros. When a new
design is desired, the configuration can be erased and a new design
configured into the device. In some examples, the FPGA can be
partially reconfigured in order to save on programming time. For
example, a subset of the logic blocks, the switches, or block rams
can be dynamically reconfigured in the field without reprogramming
the entire device.
[0076] One challenge for block-based processor implementations
mapped onto reconfigurable logic is determining micro-architectural
structures that can be efficiently implemented using the available
blocks of a custom or off-the-shelf device. However, using the
disclosed technologies, higher performance, and/or more efficient
structures can be implemented. Further, it should be readily
understood that while some examples of the FPGAs are a stand-alone
integrated circuit, in other examples, the FPGA may be packaged
differently, for example, in a multi-chip module (MCM), or on the
same circuit die as a custom or basic system-on-chip (SoC).
[0077] FIG. 4 is a block diagram 400 illustrating four
reconfigurable logic blocks 410, 411, 412, and 413 that can
configured to form part of the logic fabric of an example
FPGA-integrated circuit. The components inside the reconfigurable
logic blocks shown are identical, or homogenous, but it should be
readily understood, in other examples, more than one type of
reconfigurable logic block may be present on a single FPGA.
[0078] A first reconfigurable logic block 410 includes a six-input
Look Up Table (LUT) 420 that is coupled to carry logic 430, a
number of multiplexers 440 and 445, and a storage element (here, a
D flip-flop) 450. The LUT 420 can be implemented using a small
memory (for example, a memory having six address bits and two
output bits as shown). Thus, any six-input Boolean function can be
implemented by using a single LUT. In some examples, outputs of
LUTs can be combined, or a reconfigurable logic block can have
multiple LUTs that can be connected together in order to perform
more complex logic functions. In some examples, common logic
functions can be providing in addition to the LUT. For example, the
carry logic 430 can be configured to perform the carry propagation
logic for an adder. The multiplexers are used to select various
output from other components. For example, the multiplexer 440 can
be used to select the output of either the LUT 420 or the carry
logic 430, while the multiplexer 445 can be used to select another
output of the LUT 420 or the multiplexer 440. In some examples, the
multiplexer is used to either select a sequential output of a state
element (e.g. flip-flop 450), or a combinational output of a Look
Up Table. It should be readily understood to one of ordinary skill
in the art that different logic functions, LUT sizes, and
sequential elements can be employed in a reconfigurable logic
element. Thus, techniques for mapping block-based processors to
such reconfigurable logic can vary depending on the specific target
FPGA architecture. The configuration of the logic inside the
reconfigurable logic block can be programmed using the
configuration port of the FPGA. In some examples, the LUTs are not
programmed once, but can be configured to act as small memories
that store certain data used in the block-based processor.
[0079] In some examples of the disclosed technology, a logic
synthesis tool (logic compiler) is used to transform a
specification for a block-processor into a configuration bitstream
that can be applied to a configuration port of an FPGA to configure
logic to implement a block-based processor. In some examples, the
designer can use an RPM (relationally placed macro) methodology to
improve area and interconnect delays and achieve a repeatable
layout for easy routing and timing closure under module composition
and massive replication. For example, by including structural RTL
instantiating modules and tiling them into a scheduler, logic for
the instruction scheduler can be locked to a set of single LUTs,
allow for a compact clustering and placement of logic within the
FPGA.
VI. Example Stream of Instruction Blocks
[0080] Turning now to the diagram 500 of FIG. 5, a portion 510 of a
stream of block-based instructions, including a number of variable
length instruction blocks 511-514 is illustrated. The stream of
instructions can be used to implement user application, system
services, or any other suitable use. The stream of instructions can
be stored in memory, received from another process in memory,
received over a network connection, or stored or received in any
other suitable manner In the example shown in FIG. 5, each
instruction block begins with an instruction header, which is
followed by a varying number of instructions. For example, the
instruction block 511 includes a header 520 and twenty instructions
521. The particular instruction header 520 illustrated includes a
number of data fields that control, in part, execution of the
instructions within the instruction block, and also allow for
improved performance enhancement techniques including, for example
branch prediction, speculative execution, lazy evaluation, and/or
other techniques. The instruction header 520 also includes an
indication of the instruction block size. The instruction block
size can be in larger chunks of instructions than one, for example,
the number of 4-instruction chunks contained within the instruction
block. In other words, the size of the block is shifted 4 bits in
order to compress header space allocated to specifying instruction
block size. Thus, a size value of 0 indicates a minimally-sized
instruction block which is a block header followed by four
instructions. In some examples, the instruction block size is
expressed as a number of bytes, as a number of words, as a number
of n-word chunks, as an address, as an address offset, or using
other suitable expressions for describing the size of instruction
blocks. In some examples, the instruction block size is indicated
by a terminating bit pattern in the instruction block header and/or
footer.
[0081] The instruction block header 520 can also include one or
more execution flags that indicate one or more modes of operation
for executing the instruction block. For example, the modes of
operation can include core fusion operation, vector mode operation,
memory dependence prediction, and/or in-order or deterministic
instruction execution. Further, the execution flags can include a
block synchronization flag that inhibits speculative execution of
the instruction block.
[0082] In some examples of the disclosed technology, the
instruction header 520 includes one or more identification bits
that indicate that the encoded data is an instruction header. For
example, in some block-based processor ISAs, a single ID bit in the
least significant bit space is always set to the binary value 1 to
indicate the beginning of a valid instruction block. In other
examples, different bit encodings can be used for the
identification bit(s). In some examples, the instruction header 520
includes information indicating a particular version of the ISA for
which the associated instruction block is encoded.
[0083] The block instruction header can also include a number of
block exit types for use in, for example, branch prediction,
control flow determination, and/or branch processing. The exit type
can indicate what the type of branch instructions are, for example:
sequential branch instructions, which point to the next contiguous
instruction block in memory; offset instructions, which are
branches to another instruction block at a memory address
calculated relative to an offset; subroutine calls, or subroutine
returns. By encoding the branch exit types in the instruction
header, the branch predictor can begin operation, at least
partially, before branch instructions within the same instruction
block have been fetched and/or decoded.
[0084] The illustrated instruction block header 520 also includes a
store mask that indicates which of the load-store queue identifiers
encoded in the block instructions are assigned to store operations.
The instruction block header can also include a write mask, which
identifies which global register(s) the associated instruction
block will write. In some examples, the store mask is stored in a
store vector register by, for example, an instruction decoder
(e.g., decoder 220). In other examples, the instruction block
header 520 does not include the store mask, but the store mask is
generated dynamically by the instruction decoder by analyzing
instruction dependencies when the instruction block is decoded. For
example, the decoder can generate load store identifiers for
instruction block instructions to determine a store mask and store
the store mask data in a store vector register. Similarly, in other
examples, the write mask is not encoded in the instruction block
header, but is generated dynamically (e.g., by analyzing registers
referenced by instructions in the instruction block) by an
instruction decoder) and stored in a write mask register. The write
mask can be used to determine when execution of an instruction
block has completed and thus to initiate commitment of the
instruction block. The associated register file must receive a
write to each entry before the instruction block can complete. In
some examples a block-based processor architecture can include not
only scalar instructions, but also single-instruction multiple-data
(SIMD) instructions, that allow for operations with a larger number
of data operands within a single instruction.
[0085] Examples of suitable block-based instructions that can be
used for the instructions 521 can include instructions for
executing integer and floating-point arithmetic, logical
operations, type conversions, register reads and writes, memory
loads and stores, execution of branches and jumps, and other
suitable processor instructions. In some examples, the instructions
include instructions for configuring the processor to operate
according to one or more of operations by, for example,
speculative. Because an instruction's dependencies are encoded in
the instruction block (e.g., in the instruction block header, other
instructions that target the instruction, and/or in the instruction
itself), instructions can issue and execute out of program order
when the instruction's dependencies are satisfied.
VII. Example Block Instruction Target Encoding
[0086] FIG. 6 is a diagram 600 depicting an example of two portions
610 and 615 of C language source code and their respective
instruction blocks 620 and 625, illustrating how block-based
instructions can explicitly encode their targets. In this example,
the first two READ instructions 630 and 631 target the right
(T[2R]) and left (T[2L]) operands, respectively, of the ADD
instruction 632 (2R indicates targeting the right operand of
instruction number 2; 2L indicates the left operand of instruction
number 2). In the illustrated ISA, the read instruction is the only
instruction that reads from the global register file (e.g.,
register file 290); however any instruction can target the global
register file. When the ADD instruction 632 receives the results of
both register reads it will become ready and execute. It is noted
that the present disclosure sometimes refers to the right operand
as OP0 and the left operand as OP1.
[0087] When the TLEI (test-less-than-equal-immediate) instruction
633 receives its single input operand from the ADD, it will become
ready to issue and execute. The test then produces a predicate
operand that is broadcast on channel one (B[1P]) to all
instructions listening on the broadcast channel for the predicate,
which in this example are the two predicated branch instructions
(BRO_T 634 and BRO_F 635). The branch instruction that receives a
matching predicate will issue, but the other instruction, encoded
with the complementary predicated, will not issue.
[0088] A dependence graph 640 for the instruction block 620 is also
illustrated, as an array 650 of instruction nodes and their
corresponding operand targets 655 and 656. This illustrates the
correspondence between the block instructions 620, the
corresponding instruction window entries, and the underlying
dataflow graph represented by the instructions. Here decoded
instructions READ 630 and READ 631 are ready to issue, as they have
no input dependencies. As they issue and execute, the values read
from registers R0 and R7 are written into the right and left
operand buffers of ADD 632, marking the left and right operands of
ADD 632 "ready." As a result, the ADD 632 instruction becomes
ready, issues to an ALU, executes, and the sum is written to the
left operand of the TLEI instruction 633.
VIII. Example Block-Based Instruction Formats
[0089] FIG. 7 is a diagram illustrating generalized examples of
instruction formats for an instruction header 710, a generic
instruction 720, a branch instruction 730, and a memory access
instruction 740 (e.g., a memory load or store instruction). The
instruction formats can be used for instruction blocks executed
according to a number of execution flags specified in an
instruction header that specify a mode of operation. Each of the
instruction headers or instructions is labeled according to the
number of bits. For example the instruction header 710 includes
four 32-bit words and is labeled from its least significant bit
(lsb) (bit 0) up to its most significant bit (msb) (bit 127). As
shown, the instruction header includes a write mask field, a number
of execution flag fields, an instruction block size field, and an
instruction header ID bit (the least significant bit of the
instruction header). In some examples, the instruction header 710
includes additional metadata 715 and/or 716, which can be used to
control additional aspects of instruction block execution and
performance.
[0090] The execution flag fields depicted in FIG. 7 occupy bits 6
through 13 of the instruction block header 710 and indicate one or
more modes of operation for executing the instruction block. For
example, the modes of operation can include core fusion operation,
vector mode operation, branch predictor inhibition, memory
dependence predictor inhibition, block synchronization, break after
block, break before block, block fall through, and/or in-order or
deterministic instruction execution. The block synchronization flag
occupies bit 9 of the instruction block and inhibits speculative
execution of the instruction block when set to logic 1. Inhibiting
speculative execution is highly desirable for example, when shared
memory operations such as store conditional instructions or other
share memory operations are performed by an instruction block to
prevent memory hazards in violation of the ISA specification.
[0091] The exit type fields include data that can be used to
indicate the types of control flow instructions encoded within the
instruction block. For example, the exit type fields can indicate
that the instruction block includes one or more of the following:
sequential branch instructions, offset branch instructions,
indirect branch instructions, call instructions, and/or return
instructions. In some examples, the branch instructions can be any
control flow instructions for transferring control flow between
instruction blocks, including relative and/or absolute addresses,
and using a conditional or unconditional predicate. The exit type
fields can be used for branch prediction and speculative execution
in addition to determining implicit control flow instructions.
[0092] The illustrated generic block instruction 720 is stored as
one 32-bit word and includes an opcode field, a predicate field, a
broadcast ID field (BID), a vector operation field (V), a single
instruction multiple data (SIMD) field, a first target field (T1),
and a second target field (T2). For instructions with more
consumers than target fields, a compiler can build a fanout tree
using move instructions, or it can assign high-fanout instructions
to broadcasts. Broadcasts support sending an operand over a
lightweight network to any number of consumer instructions in a
core.
[0093] While the generic instruction format outlined by the generic
instruction 720 can represent some or all instructions processed by
a block-based processor, it will be readily understood by one of
skill in the art that, even for a particular example of an ISA, one
or more of the instruction fields may deviate from the generic
format for particular instructions. The opcode field specifies the
operation(s) performed by the instruction 720, such as memory
read/write, register load/store, add, subtract, multiply, divide,
shift, rotate, system operations, or other suitable instructions.
The predicate field specifies the condition under which the
instruction will execute. For example, the predicate field can
specify the value "true," and the instruction will only execute if
a corresponding condition flag matches the specified predicate
value. In some examples, the predicate field specifies, at least in
part, which is used to compare the predicate, while in other
examples, the execution is predicated on a flag set by a previous
instruction (e.g., the preceding instruction in the instruction
block). In some examples, the predicate field can specify that the
instruction will always, or never, be executed. Thus, use of the
predicate field can allow for denser object code, improved energy
efficiency, and improved processor performance, by reducing the
number of branch instructions.
[0094] The target fields T1 and T2 specify the instructions to
which the results of the block-based instruction are sent. For
example, an ADD instruction at instruction slot 7 can specify that
its computed result will be sent to instructions at slots 3 and 10,
including specification of the operand slot (e.g., left operation,
right operand, or predicate operand). Depending on the particular
instruction and ISA, one or both of the illustrated target fields
can be replaced by other information, for example, the first target
field T1 can be replaced by an immediate operand, an additional
opcode, specify two targets, etc.
[0095] The branch instruction 730 includes an opcode field, a
predicate field, a broadcast ID field (BID), and an offset field.
The opcode and predicate fields are similar in format and function
as described regarding the generic instruction. The offset can be
expressed in units of groups of four instructions, thus extending
the memory address range over which a branch can be executed. The
predicate shown with the generic instruction 720 and the branch
instruction 730 can be used to avoid additional branching within an
instruction block. For example, execution of a particular
instruction can be predicated on the result of a previous
instruction (e.g., a comparison of two operands). If the predicate
is false, the instruction will not commit values calculated by the
particular instruction. If the predicate value does not match the
required predicate, the instruction does not issue. For example, a
BRO_F (predicated false) instruction will issue if it is sent a
false predicate value.
[0096] It should be readily understood that, as used herein, the
term "branch instruction" is not limited to changing program
execution to a relative memory location, but also includes jumps to
an absolute or symbolic memory location, subroutine calls and
returns, and other instructions that can modify the execution flow.
In some examples, the execution flow is modified by changing the
value of a system register (e.g., a program counter PC or
instruction pointer), while in other examples, the execution flow
can be changed by modifying a value stored at a designated location
in memory. In some examples, a jump register branch instruction is
used to jump to a memory location stored in a register. In some
examples, subroutine calls and returns are implemented using jump
and link and jump register instructions, respectively.
[0097] The memory access instruction 740 format includes an opcode
field, a predicate field, a broadcast ID field (BID), an immediate
field (IMM), and a target field (T1). The opcode, broadcast,
predicate fields are similar in format and function as described
regarding the generic instruction. For example, execution of a
particular instruction can be predicated on the result of a
previous instruction (e.g., a comparison of two operands). If the
predicate is false, the instruction will not commit values
calculated by the particular instruction. If the predicate value
does not match the required predicate, the instruction does not
issue. The immediate field can be used as an offset for the operand
sent to the load or store instruction. The operand plus (shifted)
immediate offset is used as a memory address for the load/store
instruction (e.g., an address to read data from, or store data to,
in memory). For some instructions, such as a store conditional
instruction, the target field T1 745 is used to specify where a
status indicator generated by executing will be stored. For
example, the target field T1 745 can specify a register to store a
status indicator value that indicates whether the store conditional
instruction executed successfully or not (e.g., based on the load
link address and link values). A subsequent instruction block can
check the status indicator value and take appropriate action (e.g.,
by flushing an instruction block, causing the instruction block to
re-execute, raising an exception, etc.).
IX. Example Processor State Diagram
[0098] FIG. 8 is a state diagram 800 illustrating number of states
assigned to an instruction block as it is mapped, executed, and
retired. For example, one or more of the states can be assigned
during execution of an instruction according to one or more
execution flags. It should be readily understood that the states
shown in FIG. 8 are for one example of the disclosed technology,
but that in other examples an instruction block may have additional
or fewer states, as well as having different states than those
depicted in the state diagram 800. At state 805, an instruction
block is unmapped. The instruction block may be resident in memory
coupled to a block-based processor, stored on a computer-readable
storage device such as a hard drive or a flash drive, and can be
local to the processor or located at a remote server and accessible
using a computer network. The unmapped instructions may also be at
least partially resident in a cache memory coupled to the
block-based processor.
[0099] At instruction block map state 810, control logic for the
block-based processor, such as an instruction scheduler, can be
used to monitor processing core resources of the block-based
processor and map the instruction block to one or more of the
processing cores.
[0100] The control unit can map one or more of the instruction
block to processor cores and/or instruction windows of particular
processor cores. In some examples, the control unit monitors
processor cores that have previously executed a particular
instruction block and can re-use decoded instructions for the
instruction block still resident on the "warmed up" processor core.
Once the one or more instruction blocks have been mapped to
processor cores, the instruction block can proceed to the fetch
state 820.
[0101] When the instruction block is in the fetch state 820 (e.g.,
instruction fetch), the mapped processor core fetches
computer-readable block instructions from the block-based
processors' memory system and loads them into a memory associated
with a particular processor core. For example, fetched instructions
for the instruction block can be fetched and stored in an
instruction cache within the processor core. The instructions can
be communicated to the processor core using core interconnect. Once
at least one instruction of the instruction block has been fetched,
the instruction block can enter the instruction decode state
830.
[0102] During the instruction decode state 830, various bits of the
fetched instruction are decoded into signals that can be used by
the processor core to control execution of the particular
instruction, including generation of identifiers indicating
relative ordering of memory access instructions. For example, the
decoded instructions can be stored in one of the memory stores
shown above, in FIG. 2. The decoding includes generating
dependencies for the decoded instruction, operand information for
the decoded instruction, and targets for the decoded instruction.
Once at least one instruction of the instruction block has been
decoded, the instruction block can proceed to issue state 840.
[0103] During the issue state 840, instruction dependencies are
evaluated to determine if an instruction is ready for execution.
For example, an instruction scheduler can monitor an instruction's
source operands and predicate operand (for predicated instructions)
must be available before an instruction is ready to issue. For some
encodings, certain instructions also must issue according to a
specified ordering. For example, memory load store operations are
ordered according to an LSID value encoded in each instruction. In
some examples, more than one instruction is ready to issue
simultaneously, and the instruction scheduler selects one of the
ready to issue instructions to issue. Instructions can be
identified using their IID to facilitate evaluation of instruction
dependencies. Once at least one instruction of the instruction
block has issued, source operands for the issued instruction(s) can
be fetched (or sustained on a bypass path), and the instruction
block can proceed to execution state 850.
[0104] During the execution state 850, operations associated with
the instruction are performed using, for example, functional units
260 as discussed above regarding FIG. 2. As discussed above, the
functions performed can include arithmetical functions, logical
functions, branch instructions, memory operations, and register
operations. Control logic associated with the processor core
monitors execution of the instruction block, and once it is
determined that the instruction block can either be committed, or
the instruction block is to be aborted, the instruction block state
is set to commit/abort state 860. In some examples, the control
logic uses a write mask and/or a store mask for an instruction
block to determine whether execution has proceeded sufficiently to
commit the instruction block.
[0105] At the commit/abort state 860, the processor core control
unit determines that operations performed by the instruction block
can be completed. For example memory load store operations,
register read/writes, branch instructions, and other instructions
will definitely be performed according to the control flow of the
instruction block. For conditional memory instructions, data will
be written to memory, and a status indicator value that indicates
success generated during the commit/abort state 860. Alternatively,
if the instruction block is to be aborted, for example, because one
or more of the dependencies of instructions are not satisfied, or
the instruction was speculatively executed on a predicate for the
instruction block that was not satisfied, the instruction block is
aborted so that it will not affect the state of the sequence of
instructions in memory or the register file. Regardless of whether
the instruction block has committed or aborted, the instruction
block goes to state 870 to determine whether the instruction block
should be refreshed. If the instruction block is refreshed, the
processor core re-executes the instruction block, typically using
new data values, particularly the registers and memory updated by
the just-committed execution of the block, and proceeds directly to
the execute state 850. Thus, the time and energy spent in mapping,
fetching, and decoding the instruction block can be avoided.
Alternatively, if the instruction block is not to be refreshed,
then the instruction block enters an idle state 880.
[0106] In the idle state 880, the processor core executing the
instruction block can be idled by, for example, powering down
hardware within the processor core, while maintaining at least a
portion of the decoded instructions for the instruction block. At
some point, the control unit determines 890 whether the idle
instruction block on the processor core is to be refreshed or not.
If the idle instruction block is to be refreshed, the instruction
block can resume execution at execute state 850. Alternatively, if
the instruction block is not to be refreshed, then the instruction
block is unmapped and the processor core can be flushed and
subsequently instruction blocks can be mapped to the flushed
processor core.
[0107] While the state diagram 800 illustrates the states of an
instruction block as executing on a single processor core for ease
of explanation, it should be readily understood to one of ordinary
skill in the relevant art that in certain examples, multiple
processor cores can be used to execute multiple instances of a
given instruction block, concurrently.
X. Example Parallel Scheduler
[0108] FIG. 9 is a block diagram that depicts an example parallel
instruction scheduler 900 as can be implemented in certain examples
of the disclosed technology. For example, the instruction scheduler
235 for the instruction window 230 of FIG. 2 can be implemented
using the depicted parallel instruction scheduler 900. In some
examples, the parallel instruction scheduler 900 is implemented
using configurable logic in an FPGA. In other examples, the
parallel instruction scheduler 900 is implemented using cell-based
or custom logic circuits in an integrated circuit.
[0109] The illustrated parallel instruction scheduler 900 includes
32 slices of scheduler logic, one for scheduling each instruction
in a 32-instruction instruction block. For simplicity, only the
internal components of instruction slice 2 (910) is illustrated,
while the internal components of the other instruction slices are
substantially identical. Instruction slice 2 corresponds to the
instruction having IID 2 in the currently-executing instruction
block. Each of the instruction slices is configured to receive
similar signals, but are configured to respond according to their
corresponding instruction.
[0110] Each of the instruction slices receives a number of event
signals 920 generated during execution of the instruction block.
The event signals 920 are typically updated with each clock cycle.
The event signals 920 include target ready event signals T0 and T1,
which indicate that an instruction has been targeted by an
executing instruction. In some examples, the target ready event
signals include an indication of the IID and the input slot (e.g.,
OP0, OP1, or predicate slot) being targeted. In processor ISAs
supporting broadcast, the event signals 920 include a broadcast ID
BID event signal that indicates an executing instruction has
targeted a broadcast channel, and identifies the targeted channel
(e.g., one of 3 broadcast channels). The event signals 920 also can
be qualified by various input type enables ENs.
[0111] For each scheduler slice, there are a number of bits of
decoded ready state initialized by the instruction decoder when the
instruction is decoded. The decoded ready state is received from
the decoder via a bus labeled DEC.RDYS. In the example slice 910 of
the parallel instruction scheduler 900 of FIG. 9, there are six
bits of decoded ready state 930 initialized by the instruction
decoder: [0112] DBID: which indicates a 2-bit binary broadcast ID
channel that the instruction receives broadcast data on, or which
can be encoded 00 if the instruction receives no broadcast
operands; [0113] DRT, DRF: which indicate whether the instruction
is dependent on receiving a predicate true (or a predicate false)
values. In the illustrated configuration, values of DRT=1/DRF=1
indicates the instruction awaits no predicate, DRT=0/DRF=1
indicates the instruction is predicated true (awaits being targeted
by a true predicate), DRT=1/DRF=0 indicates the instruction is
predicated false (awaits being targeted by a false predicate), and
DRT=0/DRF=0 indicates the corresponding instruction has not been
decoded (the entry is empty. The same encoding can be used for
active ready state RT/RF; and [0114] DR0, DR1: which indicate that
the instruction's right operand (OP0) or left operand (OP1) are
ready, respectively.
[0115] The decoded ready state 930 can be stored in any suitable
storage component, which can include flip-flops, latches, and
memory cells. In the example coding described herein, the ready
state events (the decoded ready state events and the active ready
state events discussed below) are encoded as a zero bit if the
instruction is dependent on receiving a signal, or as a one bit if
the corresponding ready state is not a dependency of the
instruction, or has been received. Together these bits encode
whether the instruction has been decoded, awaits one or more
operand(s) (including data or predicate operands, and perhaps via a
broadcast channel), or is immediately ready to issue. These decoded
ready state 930 bits are cleared upon block reset.
[0116] For each scheduler slice, there are also a number of bits of
active ready state 940. In the example shown, there six bits of
active ready state 940: [0117] RT, RF: which indicates that the
corresponding instructions predicate true (or predicate false)
value is ready; [0118] R0, R1: which indicate that the
corresponding right operand (OP0) or left operand (OP1) are ready,
respectively; [0119] INH: which indicates that the instruction is
inhibited, because the instruction has already issued to the
instruction pipeline; and [0120] RDY: which indicates that the
corresponding instruction is ready to issue
[0121] When the RDY state indicates that the instruction is ready
to issue, a ready signal can be generated and sent to, for example,
a priority encoder to select a next one or more instructions to
issue. The active ready state 940 can be stored in any suitable
storage component, which can include flip-flops, latches, and
memory cells.
[0122] Each of the instruction scheduler slices (e.g., slice 910)
include a set of NEXT RDYS logic, which compares data that can
include: incoming event signals 920, decoded active ready state
930, previous values of the active ready state 940, and the IID of
the next issued instruction in order to update the active ready
state values, as further detailed below.
[0123] In any clock cycle any one or more (or, none) of the 32 RDY
signals can be asserted, depending on the execution state of the
processor. As more than one of the RDY signals can be asserted in a
given clock cycle, an arbitration circuit is employed to select one
instruction to issue next. In the illustrated examples, a 32-bit
priority encoder 960 reduces the asserted RDY signals to a selected
one 5-bit IID for the next instruction to issue, along with a valid
bit V. For microarchitectures that support multiple issue (more
than one instruction issuing at a time), a plurality of two or more
instruction IIDs can issue in a given clock cycles, depending on
the capacity and configuration of the processor pipeline.
[0124] As further detailed below, the processor control unit
reinitializes the decoded ready state 930 when a RESET signal is
received, and reinitializes the active ready state 940 when the
RESET signal is received, or when a REFRESH signal is received. The
RESET signal indicates that a new instruction block has been
scheduled on the pipeline hardware, and so both the decoded and
active ready state is to be initialized. The REFRESH signal
indicates that a new instance of the same instruction block has
been invoked, and thus the active ready state is to be refreshed.
However, in the refresh operation, the decoded ready state 930 can
remain, as it is invariant across instances of the same instruction
block.
[0125] In the example instruction scheduler 900, an instruction is
ready if (RT & RF & R0 & R1 & .about.INH). Any of
RT, RF, R0, R1 may be set when: [0126] its corresponding DRX is set
by the decoder, or [0127] an executing instruction targets that
input, explicitly, or via a broadcast event (broadcast ID,
input).
[0128] Active ready state bits are cleared upon block reset or
refresh. Table 1 depicts an example of a block's instruction
scheduler ready state after decoding six instructions and issuing
the first instruction (the READ instruction in the first row).
These instructions correspond to the instruction block 620
discussed above regarding FIG. 6.
TABLE-US-00001 TABLE 1 Decoded ready state Active ready state
Instruction DBID DRT DRF DR0 DR1 RT RF R0 R1 INH RDY READ 00 1 1 1
1 1 1 1 1 1 0 READ 00 1 1 1 1 1 1 1 1 0 1 ADD 00 1 1 0 0 1 1 1 0 0
0 TLEI 00 1 1 0 1 1 1 0 1 0 0 BRO.T B1 01 0 1 1 1 0 1 1 1 0 0 BRO.F
B1 01 1 0 1 1 1 0 1 1 0 0 undecoded 00 0 0 x x 0 0 x x x 0
[0129] As shown in Table 1, the first four non-predicated
instructions have DRT and DRF set, indicating that the
corresponding instructions do not await any particular predicate
results (in other words, the first four instructions are not
predicated). Thus, the two READ instructions, unpredicated and with
zero input operands (operands to be received from another
instruction in the instruction block), are immediately ready to
issue. The first has issued--and so is now inhibited from reissue
(and thus, its INH active ready state bit is set to 1)--targeting
operand 0 (OP0) of the ADD instruction, whose R0 active ready state
bit is now set to 1. The second READ will issue in the next IS
pipeline cycle. The TLEI (test-less-than-or-equal-immediate)
instruction broadcasts its predicate outcome on broadcast channel
1; the two branch instructions, BRO.T and BRO.F, which are
predicated true/false respectively, await this predicate result.
The seventh entry has not been decoded, and so the values of DRT
and DRF in the decoded ready state are set to zero (0).
[0130] To reduce the critical path of dataflow scheduling, the
front end can write predecoded EDGE instructions into the decoded
instructions buffer. As instruction IID issues, its decoded
instruction is read by the back end. Amongst other things it
contains two target operand ready event fields, _T0 and _T1, which
designate the 0-2 (IID, input) explicit targets of the instruction,
as well as a 4-bit vector of input enables: ENs={RT_EN, RF_EN,
R0_EN, R1_EN}. Referring back to FIG. 2, these signals are
multiplexed with ready events from other pipeline stages into T0
and T1 input by the scheduler using multiplexers 237 and 238. In
some examples, these ready event signals include takes inputs from
the EX pipeline registers 245 and one or more of the functional
units 250 to generate target ready events resulting from
instruction execution (as opposed to instruction issue). An example
of a logic unit that can generate such target ready events is
dubbed an EX TS control unit (not shown in FIG. 2).
[0131] For example, when the IS stage issues an instruction with a
fixed latency of two cycles, such as a multiply, it is premature to
wake up the targets of that instruction because the result will not
be available (e.g., via result forwarding) in the next cycle, but
the cycle after that. Accordingly, the issued decoded instruction
first moves into the EX pipeline stage (one cycle) and in that
cycle the EX TS control unit issues zero, one, or two target ready
events to the scheduler.
[0132] As another example, when the IS stage issues an instruction
which targets predicate operands of other instructions (e.g., a
test instruction such as TLEI), it is premature to wake up the
target(s) of that test because the true/false outcome of the test
are not yet known. Accordingly, the issued test instruction first
moves into the EX pipeline stage, the test result is determined
with one of the functional units 250, and the test result is sent
by the EX TS unit to send (predicate true or predicate false)
target ready events to the scheduler.
[0133] In some other execution scenarios, the EX TS unit is not
used to generate ready event signals. For example, when the IS
stage issues an instruction with a fixed latency of one cycle,
(e.g., an ADD instruction), the decoded instruction includes target
ready event fields to wake up the targets of the instruction as it
issues, so these target(s) may in turn issue in the next cycle (in
the example of FIG. 2, these target ready event fields are inputs
to the T0, T1 multiplexers 237 and 238). This can be used to enable
back-to-back wakeup/issue.
[0134] With careful attention to the FPGA circuit design, the area
and clock period of the scheduler can be reduced. The
32-instruction window shown will use 32*(6+6)=384 FFs for the ready
state, and 32*12 LUTs to decode ready events and update each
entry's ready state.
[0135] A modern FPGA, such as that described above in FIG. 3, packs
a set of LUTs (lookup tables) and D-flip-flops (FFs) together into
a logic cluster. For example, Xilinx Virtex-7 series devices group
four 6-LUTs and eight FFs into each "slice" cluster. Each LUT has
two outputs and may be used as one 6-LUT, or two 5-LUTs with five
common inputs. Each output may be registered (stored) in a FF. The
flip-flops have optional CE (clock enable) and SR (set/reset)
inputs but these signals are common to all eight FFs in the
cluster. This basic cluster architecture is similar in many
respects to Altera FPGAs.
[0136] From this follows two design considerations. First is the
use of fracturable 6-LUT decoders. For target instruction index
decoding, so long as the input indices are .ltoreq.5 bits, two
decoders may fit into a single 6-LUT. Second, is slice FF packing
and cluster control set restrictions. To reduce area and wire
delays, the design packs the ready state FFs densely, with about
4-8 FFs per cluster. Every 6-bit decoded ready state entry is
written together (common RST and CE) and can pack into one or two
slices.
[0137] For the active ready state FFs, each of these 32*6=192 FFs
may be individually set, but by packing four FFs per slice, when
one FF is clock enabled, all are clock enabled. Whenever a FF is
set by a ready event, the other FFs in its slice should not change.
This can be implemented using CE functionality in each FF's input
LUT, feeding back its output into its input: FF_NXT=FF|(EN &
input). Table 2 below is a Verilog hardware description language
code listing that generates the NEXT RDYS signals for an N-entry
parallel scheduler. In other examples, logic to generate NEXT RDYS
signals can be expressed in other forms, including using schematic
capture, netlists, or other suitable formats for expressing
logic.
TABLE-US-00002 TABLE 2 generate for (i = 0; i < N; i = i + 1)
begin: R always @* begin // target decoders T00[i] = T0 == i;
T01[i] = T0 == (i|N); T10[i] = T1 == i; T11[i] = T1 == (i|N); B[i]
= BID == DBID[i]; // next active ready state logic RT_NXT[i] =
RT[i] | DRT[i] | (RT_EN & (T01[i]|T11[i]|B[i])); RF_NXT[i] =
RF[i] | DRF[i] | (RF_EN & (T00[i]|T10[i]|B[i])); R0_NXT[i] =
R0[i] | DR0[i] | (R0_EN & (T00[i]|T10[i]|B[i])); R1_NXT[i] =
R1[i] | DR1[i] | (R1_EN & (T01[i]|T11[i]|B[i])); INH_NXT[i] =
INH[i] | (INH_EN & (IID == i)); RDY_NXT[i] = RT_NXT[i] &
RF_NXT[i] & R0_NXT[i] & R1_NXT[i] & .sup.~INH_NXT[i];
end end endgenerate
[0138] Although there are four ready event input types (predicate
true (RT/DRT), false (RF/DRF), right operand/OP0 (R0/DR0), left
operand/OP1 (R1/DR1), by ensuring that predicate target events
never occur in the same cycle as operand target events, a single
target index bit suffices to distinguish false/OP0 targets from
true/OP1 targets. Thus, the processor control logic and/or the
compiler can ensure that a given instruction only targets other
instruction's predicates or only targets values/operands. Further
decoding is provided by using specific {RT/RF/R0/R1}_ENs enables.).
Therefore, for an instruction window with N=32 entries, T0 and T1
are six bits, comprising an input identifier (one bit) and the
instruction IID (5 bits). Thus, the target decoders T00, T01, T10,
T11 (target-0-input-0, etc.) are each mapped to one 6-input LUT, as
is the broadcast select decoder B. The next active ready state
logic folds together the target decoder outputs with current active
and decoded ready state. This uses another seven LUTs (two for
INH_NXT), for a total of 32*12=384 LUTs for this example logic and
target FPGA technology.
[0139] This mapping can be improved by splitting the 32-entry
scheduler into two 16-entry banks of even and odd instructions
(e.g., based on the least significant bit of the instruction's
IID). In the illustrated example, within a bank, a 4-bit bank-HD
suffices. Then T0, T1 narrow to five bits so T00, T01, T10, T11 fit
inti 5, 5-input LUTs, and INH_NXT in one 6-input LUT, or
2*16*(3+6)=288 LUTs in all for this example logic and target FPGA
technology.
[0140] Besides reducing the number of LUTs, a two bank instruction
scheduler provides two sets of T0, T1 ports and can sink two sets
of two events each cycle. This can be used to sustain wider issue
rates of two instructions per cycle (which may target four operands
per cycle). Yet-wider issue and yet-larger instruction windows may
even merit a four bank design.
[0141] The ready-issue-target-ready scheduling recurrence can be
the critical path of the IS-stage. A 32.fwdarw.5 priority encoder
reduces the RDY vector to an HD which selects the decoded
instruction. The decoded instruction's fields {_T0,_T1,_BID,_ENs}
are multiplexed into {T0,T1,BID,ENs} which update target
instructions' ready state, including RDY.
[0142] Many 32-bit priority encoder designs can be used, including
one-hot conversion with LUT or carry-logic OR-trees, carry-logic
zero-scan, and F7MAP/F8MAP multiplexers. The illustrated design can
be implemented using two 16.fwdarw.4 encoders, one per bank, which
complete in two LUT delays. In a one-issue processor, a subsequent
2:1 mux selects one of these encoder outputs. Different priority
schemes can be used. For example, the priority encoder can be
configured to select the instruction asserting its RDY signal that
has the lowest IID. It should be readily understood that other
priority selection schemes can be used, for example, by preferring
high- or low-latency instructions, predicated vs. non-predicated,
or other suitable selection scheme. Additional examples of priority
selection schemes that can be employed include, but are not limited
to, selecting a ready instruction at random, selecting the ready
instruction having the highest (or lowest) IID, or selecting the
first ready instruction having an IID following the last issued
IID. It should be noted that, knowledge of how a core selects a
ready instruction to issue can be exploited by a compiler, for
example, by ordering instructions in view of the priority selection
scheme, the compiler can determine which of a number of ready
instructions will issue first. In some examples, the priority
selection scheme used for a given instruction block can be signaled
in the instruction block header.
[0143] In the illustrated example, each 16-bit encoder input
I[15:0] is chunked into bundles as follows: I[15], I[14:10],
I[9:5], and I[4:0]. Each 5-bit group indexes a 32.times.4 LUT ROM
with the precomputed encoder output for that group. Together with
three, 5-bit zero comparator outputs, these feed a 4-bit, 3:1
selector which outputs 0'b1111 when all three groups are zero.
[0144] Disclosed parallel instruction schedulers can be adapted for
improved Technology mapping and floorplanning, depending on the
FPGA target. The example design illustrated in FIG. 9 uses an RPM
(relationally placed macro) methodology to improve area and
interconnect delays and to achieve a repeatable layout for easier
routing and timing closure under module composition and massive
replication. Structural RTL can be used instantiate modules and
tiles them into a scheduler. For example, when mapping to Xilinx
FPGAs, the XST annotation (*LUT_MAP="yes"*) on a .ltoreq.6-input
module will cause the Xilinx XST compiler to lock logic to one LUT;
the XST annotation (*RLOC="XxYy"*) packs FPGA primitives into logic
clusters and places logic clusters relative to each other.
[0145] FIG. 10 is a floorplan 1000 of a Xilinx Kinext-7 series
implementation of the example parallel instruction scheduler 900
including a scheduler slice 910, priority encoder 960, and decoded
instruction buffer 236, with the timing critical path 1010
indicated.
[0146] Each two horizontal rows of FPGA slices correspond to four
entries in the instruction window. Left to right are: [0147] pale
yellow: four 6-bit decoded ready state flip-flops; [0148]
yellow/green: B, T00, T01, T10, T11 target decoders; [0149] orange:
active ready state LUTs/FPs RT NXT/RT, etc.; [0150] purple: INH_NXT
and INH; [0151] red: RDY_NXT and RDY.
[0152] To the right are the synthesized priority encoders and muxes
(blue) and the decoded instructions buffer (white) implemented in
several 32.times.6-bit true dual port LUT RAMs.
[0153] Performance: In a Kintex-7-1-speed grade, the critical path
takes 5.0 ns, including RDY clock-to-out, priority encoder, mux,
decoded instructions LUT RAM, next readys logic and RDY setup.
Interconnect delay is 85% of the critical path, as all paths from
any RDY to any RDY must traverse a relatively large diameter
netlist.
[0154] Cycle time may be reduced to 2.9 ns by adding a pipeline
register halfway through the scheduler critical path (the output
port of the instruction buffer LUT RAM), however this will not
achieve back-to-back issue (in successive cycles) of a single
dependent chain of instructions.
[0155] In some examples using split-bank parallel schedulers, an
EDGE compiler does not guarantee that both targets of an
instruction are in disjoint scheduler banks, so there may be
scheduler bank conflicts. For example, an ADD instruction might
target an operand of instruction 10 and an operand of instruction
12. Since the parallel scheduler cannot update the active ready
state of the two even bank targets in the same cycle, one event is
processed and the other is queued for a later cycle.
XI. Example Block-Based Processor and Memory Configuration
[0156] FIG. 11 is a diagram 1100 illustrating an apparatus
comprising a block-based processor 1110, including a control unit
1120 configured to execute instruction blocks including
instructions for memory operations including memory synchronization
and memory locks. The control unit includes a core scheduler 1125
that controls allocation and de-allocation of cores for performing
instruction processing, control of input data and output data
between any of the cores, register files, memory interfaces and/or
I/O interfaces. The control unit 1120 can also include dedicated
registers for performing certain memory operations.
[0157] The block-based processor 1110 also includes one or more
processor cores 1130-1137 that are configured to fetch and execute
instruction blocks. Each of the cores includes an instruction
scheduler (e.g., parallel instruction scheduler 1141) that controls
the order in which instructions in an instruction block are
fetched, decoded, issued, and executed. The illustrated block-based
processor 1110 has up to eight cores, but in other examples there
could be 1, 2, 4, 64, 512, 1024, or other numbers of block-based
processor cores. The block-based processor 1110 is coupled to a
memory 1150 which includes a number of instruction blocks,
including instruction blocks A and B, which include instructions
(1155 and 1156, respectively) implementing disclosed memory
operations, and to a computer-readable storage media disc 1160 that
stores instructions 1165 for performing disclosed memory
operations.
XII. Example Method of Operating a Block-Based Processor
[0158] FIG. 12 is a flow chart 1200 outlining an example method of
selecting one or more block-based processor instructions to issue
with a parallel instruction scheduler, as can be performed in
certain examples of the disclosed technology. For example, the
block-based processor 100 discussed above regarding FIG. 1
including examples implemented using the microarchitecture 200
discussed above regarding FIG. 2 can be used to implement the
illustrated method.
[0159] At process block 1210, decoded ready state data is received
from an instruction decoder. In some examples, the instruction
decoder receives instructions that have been cached in an
instruction cache. The instruction decoder can generate signals
that are sent to a parallel instruction scheduler and to a decoded
instruction store. The decoder sends decoded ready state data to
the parallel instruction scheduler. For example, this can include
data indicating whether the referenced instruction is dependent
upon receiving a broadcast operand, and which channel the broadcast
operand will be received on, a predicate operand, and the value on
which the predicate operand is to evaluate in order to execute the
instruction, and a left and/or right operand. The decoder also
sends decoded instruction data to a decoded instruction store.
Signals can be generated for issuing and executing the respective
instructions according to the decoded signals in the decoded
instruction store.
[0160] The parallel instruction scheduler also maintains a store of
active ready state data. In some examples, the active ready state
data is initialized by copying the decoded ready state data as the
initial active ready state. Other signals in the active ready state
data, such as the ready signal and the inhibit signal, are also
initialized. Once the decoded ready state data and the active ready
state data have been initialized, the method can proceed to process
block 1220.
[0161] At process block 1220, the parallel instruction scheduler
receives event signals from processor execution units. For example,
signals indicating whether a broadcast operand on a particular
channel have been generated, targeted instruction identifiers (T1
and T0), and enable signals can be generated and received by the
parallel instruction scheduler as execution proceeds. The parallel
instruction scheduler also receives instruction identifiers as
instructions are issued according to the ready signals generated by
the parallel instruction scheduler.
[0162] At process block 1230, based on the decoded ready state data
and event signals received at process block 1220, active ready
state signals and ready signals are updated. For example, parallel
instruction scheduler illustrated in FIG. 9 can use logic in the
NEXT RDYS logic block to evaluate the incoming signals and existing
scheduler state in order to update the active ready state data and
to generate ready signals for any instruction whose dependencies
have been satisfied, and thus is ready to issue.
[0163] At process block 1240, one or more instructions are selected
to issue based on ready signals generated at process block 1230.
Sometimes there will be more than one instruction that has a ready
signal. In such examples, selection techniques such as using a
priority encoder can be employed to select the next instruction to
issue. In some examples, the priority encoder selects a next
instruction to issue based on comparing the instruction identifiers
for the instructions. In other examples, different criteria can be
used such as the type of instruction. For example, a selection
scheme can select predicated or non-predicated instructions with
higher priority, or select memory load/store or other types of
instructions to issue, depending on the configured scheme. Once the
instruction has been selected for issue, its inhibit bit is set in
the active ready state. This prevents the instruction from being
selected a second time for issue.
XIII. Example Method of Operating a Block-Based Processor with
Optional Bypass
[0164] FIG. 13 is a flow chart 1300 outlining an example method of
using a parallel instruction scheduler to select, issue, and
execute instructions according to certain examples of the disclosed
technology. For example, the block-based processor 100 discussed
above regarding FIG. 1, including those implementations that use a
microarchitecture 200 similar to that shown in FIG. 2, can be used
to perform the illustrated method. In some examples, the method is
performed using a custom or ASIC processor, while in other
examples, the method is performed using a soft processor formed
using reconfigurable logic such as in an FPGA.
[0165] At process block 1310, a parallel instruction scheduler,
such as that described above regarding FIG. 9, is initialized.
Ready state data for each instruction is initialized in the
instruction scheduler. The instruction scheduler includes one slice
of ready state data and ready state update logic per instruction.
Each slice can be addressed according to its corresponding
instruction identifier, which is encoded in the instruction block.
Thus, dependencies are identified using the instruction identifier
encoded in the instruction block and not based on varying
identifications of registers or virtual registers. In some
examples, the scheduler is initialized using previously decoded
data for a particular instruction block. Some examples, the first
time, or certain subsequent instances of executing an instruction
block, and instruction decoder generates the ready state data and
also generates decoded instruction control signals by decoding
instruction header and instruction information from instructions
stored in main memory and/or temporarily stored in an instruction
cache.
[0166] At process block 1320, ready state data and event signals
are evaluated to generate ready signals for those instructions that
have satisfied dependencies. For example, for the parallel
instruction scheduler described above regarding FIG. 9, when all
the bits of active ready state 940 have been set to 1, the
corresponding ready signal for the associated slice of an
instruction is set to 1. Control logic in the processor can select
from one or more of the instructions asserting ready signals and
issuing the instruction. The control logic then asserts the inhibit
active ready state data to prevent the instruction from
re-executing.
[0167] At process block 1330, one or more instructions are
selected, issued, and executed according to the ready signals
generated at process block 1320. In a single issue
microarchitecture, only one instruction at a time is issued. In
multiple issue microarchitectures, more than one instruction can be
issued and executed concurrently. In some examples, a priority
encoder is used to select the ready instruction having the lowest
instruction ID to issue next. In other examples, other schemas can
be used to identify the next instruction to issue.
[0168] At process block 1340, the operand buffer is bypassed for at
least one source operand of an executing instruction. For example,
because the parallel scheduler can indicate that more than one
instruction is ready to issue, thus the parallel instruction
scheduler can issue a first instruction in a first clock cycle of
the processor pipeline and generate a ready signal indicating that
a second instruction is ready to issue. The second instruction is
dependent on at least one operand generated by a first instruction.
The instruction scheduler contains logic that can be used to
identify this dependency and in the next clock cycle of the
processor pipeline, issue the second instruction. In some cases,
this can eliminate one or more cycles of pipeline stall, thereby
improving throughput of the processor pipeline. In some examples,
bypass logic in the data path allows for data operands from the
first execution instruction to be forwarded to the execution unit
of the processor without first being stored in the data operand
buffer. This allows for eliminating a pipeline clock cycle from
storing and retrieving the associated data operand in the data
operand buffer. Thus, the parallel instruction scheduler allows for
bypassing the operand buffer for at least one source operand of an
executing instruction.
[0169] At process block 1350, event signals are generated for
executing and retired instructions. For example, the event signals
can indicate that target operands are available for the target
operands of the executed instruction. Other event signals can
indicate that broadcast channel operands are available. In some
examples, other signals such as the availability of data fetched
from a registered file and/or memory can also be generated as event
signals. The event signals can be sent to a parallel instruction
scheduler for updating ready state data and issuing additional
instructions. After an instruction block is committed and retired,
another instruction block is executed. If the same instruction
block is re-executed as a new instance, the method proceeds to
process block 1310 and the parallel instruction scheduler is
refreshed. In other words, active ready state data in each slice of
the parallel instruction scheduler is reset according to the
decoded ready state previously generated for the instruction block.
On the other hand, if a new instruction block is fetched and
executed, the method proceeds to process block 1360.
[0170] At process block 1360, the instruction window ready state
for the instruction block is completely reset. New decoded ready
state data is generated either from an instruction decoder. The
instruction window of the processor is then reset by going back to
process block 1310 to execute the instruction block.
XIV. Example Method of Configuring a Reconfigurable Logic
Device
[0171] FIG. 14 is a flow chart 1400 outlining an example method of
configuring a reconfigurable logic device, as can be performed in
certain examples of the disclosed technology. For example, the FPGA
discussed above regarding FIG. 3 can be configured to implement the
block-based processor of FIG. 1 using the example microarchitecture
discussed above regarding FIG. 2, including parallel instruction
schedulers, including the instruction parallel scheduler discussed
above regarding FIG. 9.
[0172] At process block 1410, a description of block-based
processor components is mapped to reconfigure logic device
components of the FPGA. For example, a process designer can specify
a description of the block-based processor in the hardware
description language, such as SystemVerilog, SystemC, Verilog, or
any other suitable combination of hardware description languages.
In some examples, a description written in a traditional
programming language such as C or C++ are used to describe at least
a portion of the block-based processor. For example, Table 2 above
is an Verilog code listing that can be used to implement NEXT RDYS
logic in certain examples of a parallel instruction scheduler. The
description of the block-based processor can include any of the
novel components discussed above. In some examples, the designer
can specify specific FPGA cells to be targeted by elements of the
processor microarchitecture. For example, the designer may specify
that the instruction cache and/or the data cache are implemented
using block RAM resources of the FPGA. In some examples, the
programmer can use available macros provided by the FPGA vendor to
implement FIFO buffers, shift registers, and other components using
economical mappings for that FPGA.
[0173] At process block 1420, a configuration bitstream is produced
for implementing a circuit for the block-based processor that
includes a parallel instruction scheduler that uses ready state
data indexed by an instruction identifier. For example, a
description of a block-based processor expressed in a hardware
description language can be compiled to generate a netlist, and the
netlist in turn used to generate a bitstream file. The signals
indicated in the bitstream file can be applied to the configuration
interface of an FPGA in order to configure the FPGA to perform
functions for implementing a block-based processor according to the
disclosed techniques.
[0174] At process block 1430, the reconfigurable logic device is
configured using the bitstream generated at process block 1420. For
example, some FPGAs have a configuration port that is used to
serially stream data into configuration memory of the FPGA, thereby
configuring the FPGA. In some examples, configuration memory of the
FPGA is addressed through a parallel or other addressable port. In
some examples, a configurable logic device having a structure
similar to an FPGA can be configured once, but not reconfigured. In
other examples, the FPGA can be electrically erased and rewritten
to in order to provide a new configuration. In some examples, the
FPGA is re-configured whenever the integrated circuit is
re-powered, while in other examples, the FGPA configuration
maintains state across repeated power cycles.
XV. Experimental Results
[0175] Experimental results, including resource usage in an
exemplary Xilinx 7-Series FPGA, are discussed below. The
experimental results are based on a block-based processor design
incorporating a parallel instruction scheduler in comparison to a
processor design using a different, incremental instruction
scheduler. The results are provided for illustrative purposes, but
should not be taken as limiting the scope of the claims or
otherwise importing limitations to the present disclosure.
TABLE-US-00003 TABLE 3 Metric Parallel Incremental Units Area, 32
Entries 288 78 LUTs Area, total, 32 entries 340 150 LUTs Period 5.0
4.3 ns Period, pipelined 2.9 2.5 ns Area, total * period 1700 645
LUT*ns Broadcast flash iterative Event bank conflicts? typically
avoided sometimes Area, 4 events/cycle 288 156 LUTs Area, 64
entries 576 130 LUTs
[0176] Table 3 summarizes differences between the parallel dataflow
scheduler design discussed above and an example incremental
dataflow scheduler design. The parallel scheduler is larger than
the alternative incremental implementation but exhibits a number of
performance advantages. The processor with the parallel instruction
scheduler can process a broadcast event in a single cycle. The
parallel instruction scheduler is also not subject to even/odd
target bank conflicts, which may delay an instruction wake up.
[0177] Further, for wider issue and larger instruction windows, the
parallel scheduler does not grow when subdivided into more banks to
process twice as many events per cycle, whereas the alternative
incremental scheduler core area doubles. To grow the instruction
window to 64 entries, the parallel scheduler require twice as much
area.
XVI. Example Computing Environment
[0178] FIG. 15 illustrates a generalized example of a suitable
computing environment 1500 in which described embodiments,
techniques, and technologies, including configuring a block-based
processor, can be implemented. For example, the computing
environment 1500 can implement disclosed techniques for configuring
a processor to implement disclosed block-based processor
architectures and microarchitectures, and/or compile code into
computer-executable instructions and/or configuration bitstreams
for performing such operations including a parallel instruction
scheduler, as described herein.
[0179] The computing environment 1500 is not intended to suggest
any limitation as to scope of use or functionality of the
technology, as the technology may be implemented in diverse
general-purpose or special-purpose computing environments. For
example, the disclosed technology may be implemented with other
computer system configurations, including hand held devices,
multi-processor systems, programmable consumer electronics, network
PCs, minicomputers, mainframe computers, and the like. The
disclosed technology may also be practiced in distributed computing
environments where tasks are performed by remote processing devices
that are linked through a communications network. In a distributed
computing environment, program modules (including executable
instructions for block-based instruction blocks) may be located in
both local and remote memory storage devices.
[0180] With reference to FIG. 15, the computing environment 1500
includes at least one block-based processing unit 1510 and memory
1520. In FIG. 15, this most basic configuration 1530 is included
within a dashed line. The block-based processing unit 1510 executes
computer-executable instructions and may be a real or a virtual
processor. In a multi-processing system, multiple processing units
execute computer-executable instructions to increase processing
power and as such, multiple processors can be running
simultaneously. The memory 1520 may be volatile memory (e.g.,
registers, cache, RAM), non-volatile memory (e.g., ROM, EEPROM,
flash memory, etc.), or some combination of the two. The memory
1520 stores software 1580, images, and video that can, for example,
implement the technologies described herein. A computing
environment may have additional features. For example, the
computing environment 1500 includes storage 1540, one or more input
device(s) 1550, one or more output device(s) 1560, and one or more
communication connection(s) 1570. An interconnection mechanism (not
shown) such as a bus, a controller, or a network, interconnects the
components of the computing environment 1500. Typically, operating
system software (not shown) provides an operating environment for
other software executing in the computing environment 1500, and
coordinates activities of the components of the computing
environment 1500.
[0181] The storage 1540 may be removable or non-removable, and
includes magnetic disks, magnetic tapes or cassettes, CD-ROMs,
CD-RWs, DVDs, or any other medium which can be used to store
information and that can be accessed within the computing
environment 1500. The storage 1540 stores instructions for the
software 1580, plugin data, and messages, which can be used to
implement technologies described herein.
[0182] The input device(s) 1550 may be a touch input device, such
as a keyboard, keypad, mouse, touch screen display, pen, or
trackball, a voice input device, a scanning device, or another
device, that provides input to the computing environment 1500. For
audio, the input device(s) 1550 may be a sound card or similar
device that accepts audio input in analog or digital form, or a
CD-ROM reader that provides audio samples to the computing
environment 1500. The output device(s) 1560 may be a display,
printer, speaker, CD-writer, or another device that provides output
from the computing environment 1500.
[0183] The communication connection(s) 1570 enable communication
over a communication medium (e.g., a connecting network) to another
computing entity. The communication medium conveys information such
as computer-executable instructions, compressed graphics
information, video, or other data in a modulated data signal. The
communication connection(s) 1570 are not limited to wired
connections (e.g., megabit or gigabit Ethernet, Infiniband, Fibre
Channel over electrical or fiber optic connections) but also
include wireless technologies (e.g., RF connections via Bluetooth,
WiFi (IEEE 802.11a/b/n), WiMax, cellular, satellite, laser,
infrared) and other suitable communication connections for
providing a network connection for the disclosed methods. In a
virtual host environment, the communication(s) connections can be a
virtualized network connection provided by the virtual host.
[0184] Some embodiments of the disclosed methods can be performed
using computer-executable instructions implementing all or a
portion of the disclosed technology in a computing cloud 1590. For
example, disclosed compilers and/or block-based-processor servers
are located in the computing environment, or the disclosed
compilers can be executed on servers located in the computing cloud
1590. In some examples, the disclosed compilers execute on
traditional central processing units (e.g., RISC or CISC
processors).
[0185] Computer-readable media are any available media that can be
accessed within a computing environment 1500. By way of example,
and not limitation, with the computing environment 1500,
computer-readable media include memory 1520 and/or storage 1540. As
should be readily understood, the term computer-readable storage
media includes the media for data storage such as memory 1520 and
storage 1540, and not transmission media such as modulated data
signals.
XVII. Additional Examples of the Disclosed Technology
[0186] Additional examples of the disclosed subject matter are
discussed herein in accordance with the examples discussed above.
For example, aspects of the block-based processors discussed above
regarding FIGS. 1, 2, and 9 can be used to implement these
additional examples, including FPGAs such as those discussed above
regarding FIGS. 3 and 4.
[0187] In certain examples of the disclosed technology, all or a
portion of a block-based processor are implemented by configuring
an FPGA to include structures for executing programs expressed in
the block-based processor ISA. In some examples, the processor is
implemented in an embedded device such as for deploying in a
network of Internet of Things (IoT). In some examples, structures
such as caches, and storage used in the instruction scheduler, the
load store queue and/or the register file are implemented in
memories having a single write port or a single read port. In other
examples, one or more of these structures are implemented in
memories having multiple read and/or write ports. In some examples,
an instruction block header, and one or more instructions of the
instruction block can be fetched from memory and/or the instruction
cache, concurrently. In some examples, a bypass mechanism allows
for operations generated from the execution portion of the
microarchitecture pipeline to bypass operands, thereby allowing for
the back-to-back issue of instructions having a shared or chained
dependencies. In some examples, the bypass mechanism allows for the
avoidance of pipeline stall when there are more operands generated
during an execution clock cycle than write ports on the instruction
window operand buffer.
[0188] In some examples, the scheduler can use decoded or
previously decoded instruction dependencies to wake up and issue
instructions before they have been fetched. In some examples,
storage for the instruction scheduler can be split in to two or
more portions in order to map the storage to two or more physical
storage units of an FPGA. In some examples, the instruction
scheduler includes a parallel scheduler. In some examples, the
scheduler is configured to refresh some but not all of an
instructions ready state upon re-executing an instruction
block.
[0189] In some examples of the disclosed technology, an apparatus
includes a block-based processor having an instruction decoder
configured to generate ready state data for a set of instructions
in an instruction block, each of the set of instructions being
associated with a different instruction identifier encoded in the
instruction block, and a parallel instruction scheduler configured
to issue an instruction from the set of instructions based on the
decoded ready state data. In some examples, the parallel
instruction scheduler includes a scheduler slice for each
respective instruction in the set of instructions. In some
examples, the scheduler slice includes storage configured to store
ready state data for its respective instruction, and wherein the
scheduler slice is further configured to generate a ready signal
indicating that its respective instruction is ready to issue. In
some examples, the scheduler slice is configured to update active
ready state data based in part on event signals generated during
execution of the instruction block. In some examples, the scheduler
slice is configured to update active ready state data based in part
on receiving an instruction identifier indicating that the
scheduler slice's respective instruction has issued. In some
examples, the ready state data includes decoded ready state data
and active ready state data, the decoded ready state data being
invariant for an instruction in an instruction block, the active
ready state data being seeded using the decoded ready state data as
a mask. In some examples, the block-based processor is a soft core
processor implemented with a configurable logic device, for example
a reconfigurable logic device such as an FPGA.
[0190] In some examples, a parallel instruction scheduler is
configured to, in a first clock cycle of the processor, issue a
first instruction and generate a ready signal that a second
instruction is ready to issue, the second instruction being
dependent on the first instruction, and in the next clock cycle of
the processor, issue the second instruction. In some examples, the
processor further includes a data operand buffer configured to
store operand data for not more than one instruction per clock
cycle, and bypass logic that allows a data operand for a different
instruction to be forwarded to an execution unit of the processor
in the same clock cycle as different data operand is stored in the
data operand buffer.
[0191] In some examples of the disclosed technology, a
(re)configurable logic device is configured to execute a
block-based processor instruction set, the device including: a
plurality of lookup-tables (LUTs), an instruction decoder
configured to generate representations of dependencies for
instructions encoded in an instruction block, a parallel
instruction scheduler configured to generate a ready signal
indicating that dependencies for a respective instruction are
satisfied, and one or more execution units configured to perform
operations specified by the respective instruction after receiving
its ready signal. In some examples, the instruction scheduler is
split into two or more banks, each of the banks being assigned to a
different portion of the plurality of multi-input LUTs. In some
examples, the instruction scheduler is implemented with random
access memory (RAM) formed using a portion of the plurality of
LUTs. In some examples, the instruction scheduler is coupled to a
decoded instruction word memory configured to store decoded
instruction control data for at least a portion of the received
instructions and a plurality of operand buffers configured to store
operand data for executing the received instructions. In some
examples, the device is further configured to execute a subsequent
instance of an instruction block by refreshing and re-executing the
instruction block, and the ready state data includes decoded ready
state information, which is not cleared upon the refreshing and
active ready state data, which is cleared upon the refreshing. In
some examples the scheduler stores the ready state data for each
instruction in a set of flip-flops of the configurable logic device
that can be cleared and/or set with a single signal.
[0192] In some examples of the disclosed technology, a method of
forming a block-based processor with a configurable logic device
includes producing a configuration bitstream comprising
configuration information for implementing a circuit for the
block-based processor with a configurable logic device, the circuit
for the block-based processor including a parallel instruction
scheduler configured to issue instructions based on ready state
data stored in a memory indexed by an instruction identifier
uniquely identifying each respective instruction of a transactional
instruction block.
[0193] In some examples, the method of generating the configuration
bitstream includes using a logic compiler to map portions of the
scheduler having N or fewer inputs to lookup table memories of the
configurable logic device having N or fewer inputs. In some
examples, the method further includes using a logic compiler to map
portions of the scheduler to a first bank of logic resources of the
configurable logic device and other portions of the scheduler to a
second bank of logic resources of the configurable logic device. In
some examples, the method further includes applying the
configuration bitstream to a configuration port of an integrated
circuit comprising the configurable logic devices and executing one
or more instruction blocks with the block-based processor. In some
examples, the method includes storing the configuration bitstream
in a computer-readable storage device or memory.
[0194] In view of the many possible embodiments to which the
principles of the disclosed subject matter may be applied, it
should be recognized that the illustrated embodiments are only
preferred examples and should not be taken as limiting the scope of
the claims to those preferred examples. Rather, the scope of the
claimed subject matter is defined by the following claims. We
therefore claim as our invention all that comes within the scope of
these claims.
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