U.S. patent application number 15/429403 was filed with the patent office on 2017-06-22 for enhanced lateral cavity etch.
The applicant listed for this patent is Texas Instruments Incorporated. Invention is credited to Brian E. Goodlin, Karen H. R. Kirmse, Iqbal R. Saraf.
Application Number | 20170178916 15/429403 |
Document ID | / |
Family ID | 58360124 |
Filed Date | 2017-06-22 |
United States Patent
Application |
20170178916 |
Kind Code |
A1 |
Goodlin; Brian E. ; et
al. |
June 22, 2017 |
ENHANCED LATERAL CAVITY ETCH
Abstract
A cavity is formed in a semiconductor substrate wherein the
width of the cavity is greater than the depth of the cavity and
wherein the depth of the cavity is non uniform across the width of
the cavity. The cavity may be formed under an electronic device in
the semiconductor substrate. The cavity is formed in the substrate
by performing a first cavity etch followed by repeated cycles of
polymer deposition, cavity etch, and polymer removal.
Inventors: |
Goodlin; Brian E.; (Plano,
TX) ; Kirmse; Karen H. R.; (Richardson, TX) ;
Saraf; Iqbal R.; (Wappingers Falls, NY) |
|
Applicant: |
Name |
City |
State |
Country |
Type |
Texas Instruments Incorporated |
Dallas |
TX |
US |
|
|
Family ID: |
58360124 |
Appl. No.: |
15/429403 |
Filed: |
February 10, 2017 |
Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
|
|
14973904 |
Dec 18, 2015 |
9607847 |
|
|
15429403 |
|
|
|
|
Current U.S.
Class: |
1/1 |
Current CPC
Class: |
H01L 37/02 20130101;
G01J 5/0225 20130101; H01L 29/0657 20130101; H01L 21/3081 20130101;
H01L 28/10 20130101; H01L 29/04 20130101; H01L 21/31138 20130101;
H01L 21/3065 20130101; H01L 29/16 20130101; H01L 21/31058 20130101;
G01J 5/024 20130101; H01L 37/00 20130101; H01L 21/3083 20130101;
H01L 29/161 20130101 |
International
Class: |
H01L 21/3065 20060101
H01L021/3065; H01L 29/16 20060101 H01L029/16; H01L 29/06 20060101
H01L029/06; H01L 29/161 20060101 H01L029/161; H01L 37/02 20060101
H01L037/02; H01L 21/308 20060101 H01L021/308; H01L 21/3105 20060101
H01L021/3105; H01L 29/04 20060101 H01L029/04; H01L 49/02 20060101
H01L049/02 |
Claims
1. A semiconductor device comprising a cavity in a substrate
wherein the cavity is wider than it is deep and wherein a depth of
the cavity is non-uniform across a width of the cavity.
2. The semiconductor device of claim 1, wherein the substrate is
single crystal silicon.
3. The semiconductor device of claim 1, wherein the substrate is
single crystal silicon germanium.
4. The semiconductor device of claim 1, wherein the cavity
underlies an opening in an overlying masking layer.
5. The semiconductor device of claim 4, wherein the masking layer
comprises a layer of silicon nitride overlying a layer of silicon
dioxide.
6. The semiconductor device of claim 1, wherein the cavity is under
an inductor.
7. The semiconductor device of claim 1, wherein the cavity is under
a bolometer.
8. The semiconductor device of claim 1, wherein the cavity is under
an electronic device that is sensitive to capacitive coupling to
the substrate.
9. A semiconductor device comprising: a silicon substrate without
an etch stop layer within the silicon substrate; a cavity in the
silicon substrate wherein the cavity is at least twice as wide as
it is deep.
10. The semiconductor device of claim 9, wherein the silicon
substrate is single crystal silicon.
11. The semiconductor device of claim 9, wherein the silicon
substrate is single crystal silicon germanium.
12. The semiconductor device of claim 9, wherein the cavity is
under an inductor.
13. The semiconductor device of claim 9, wherein the cavity is
under a bolometer.
14. The semiconductor device of claim 9, wherein the cavity is
under an electronic device that is sensitive to capacitive coupling
to the substrate.
15. A semiconductor device comprising: a substrate of single
crystal silicon; a cavity in the substrate wherein the cavity is at
least twice as wide as it is deep, wherein single crystal silicon
forms a bottom surface and side surfaces of the cavity and wherein
a depth of the cavity is non-uniform across a width of the
cavity.
16. The semiconductor device of claim 15, wherein the cavity is
under an inductor.
17. The semiconductor device of claim 15, wherein the cavity is
under a bolometer.
18. The semiconductor device of claim 15, wherein the cavity is
under an electronic device that is sensitive to capacitive coupling
to the substrate.
Description
CROSS REFERENCE TO RELATED APPLICATIONS
[0001] This application is a divisional of U.S. Nonprovisional
Patent Application Ser. No. 14/973,904, filed Dec 18, 2015, the
contents of which are herein incorporated by reference in its
entirety.
FIELD OF THE INVENTION
[0002] This invention relates to the field of semiconductor devices
and more specifically to the formation of a cavity wherein the
width of the cavity exceeds the depth in a semiconductor
device.
BACKGROUND
[0003] Cavities are frequently formed in semiconductor circuits to
reduce coupling of a device such as an inductor, heater, or
bolometer to the substrate. Typically a cavity is etched into a
substrate material such silicon or SiGe through an opening in a
dielectric layer overlying the substrate using a substantially
isotropic etch. Typically the substantially isotropic etch, etches
the cavity vertically faster than it does laterally. Consequently a
very deep cavity may need to be formed to completely remove the
substrate laterally from under the device to reduce coupling. The
deep cavity may weaken the substrate resulting in breakage and
yield loss.
[0004] One method to avoid etching a deep cavity is to build an
etch stop layer into the substrate under the device with the
coupling issue. This method may add significant complexity, cycle
time, and cost to the manufacturing flow.
SUMMARY
[0005] The following presents a simplified summary in order to
provide a basic understanding of one or more aspects of the
invention. This summary is not an extensive overview of the
invention, and is neither intended to identify key or critical
elements of the invention, nor to delineate the scope thereof.
Rather, the primary purpose of the summary is to present some
concepts of the invention in a simplified form as a prelude to a
more detailed description that is presented later.
[0006] A cavity is formed in a semiconductor substrate wherein the
width of the cavity is greater than the depth of the cavity and
wherein the depth of the cavity is non uniform across the width of
the cavity. The cavity may be formed under an electronic device in
the semiconductor substrate. The cavity is formed in the substrate
by performing a first cavity etch followed by repeated cycles of
polymer deposition, cavity etch, and polymer removal.
DESCRIPTION OF THE VIEWS OF THE DRAWINGS
[0007] FIG. 1A through FIG. 1J are cross sections illustrating the
formation of a cavity in an integrated circuit in successive stages
of fabrication according to principles of the invention.
[0008] FIG. 2 is flow diagram for the steps in a process of forming
a cavity in a substrate according to principles of the
invention.
DETAILED DESCRIPTION OF EXAMPLE EMBODIMENTS
[0009] The present invention is described with reference to the
attached figures. The figures are not drawn to scale and they are
provided merely to illustrate the invention. Several aspects of the
invention are described below with reference to example
applications for illustration. It should be understood that
numerous specific details, relationships, and methods are set forth
to provide an understanding of the invention. One skilled in the
relevant art, however, will readily recognize that the invention
can be practiced without one or more of the specific details or
with other methods. In other instances, well-known structures or
operations are not shown in detail to avoid obscuring the
invention. The present invention is not limited by the illustrated
ordering of acts or events, as some acts may occur in different
orders and/or concurrently with other acts or events. Furthermore,
not all illustrated acts or events are required to implement a
methodology in accordance with the present invention.
[0010] A structure with a cavity that is etched according to
embodiments is illustrated in FIG. 1F. The cavity is etched into
the substrate 100 using an etch that is substantially isotropic.
The cavity is wider than it is deep. The cavity depth is non
uniform across the width of the cavity. The cavity is deepest under
the opening through which the cavity is etched.
[0011] The method for forming a cavity wherein the width of the
cavity is substantially wider than the depth of the cavity is
described in the process flow in FIG. 2 and in the cross sections
in FIGS. 1A through 1J.
[0012] FIG. 1A shows a substrate 100 that may be etched using an
etchant that etches substantially isotropically, that is, etches
laterally as well as vertically. A hard mask (layers 102 and 104)
overlies the substrate. The etchant may be introduced through an
opening 106 in the hard mask 102/104 to etch a cavity in the
substrate 100 (step 200 in FIG. 2). In an example embodiment, the
substrate 100 is single crystal silicon and the hard mask is
comprised of a layer of silicon nitride 104 which overlies a layer
of silicon dioxide 102. One layer of masking material (silicon
dioxide for example) may alternatively be used. Other masking
materials and other substrates may also be used. The opening 106 in
the example embodiment may be in the range of less than a micron to
many microns wide depending upon the details of the device being
manufactured. In an example embodiment opening 106 is about 25
microns wide.
[0013] In first cavity etch step 202 of FIG. 2, etchant is
introduced through opening 106 and etches the substrate 100 both
vertically and laterally to form a cavity with first cavity etch
sidewalls 108 as shown in FIG. 1B. In an example embodiment the
silicon substrate 100 is etched in a substantially isotropic manner
using a SF.sub.6 plasma etch. In the example embodiment, the
SF.sub.6 etches the silicon approximately twice as fast vertically
as laterally through the opening 106.
[0014] Example cavity etch process conditions are 225 mT pressure,
4000 Watts source power, 0 Watts bias power, 1000 sccm SF.sub.6,
and a temperature of 15.degree. C.
[0015] In step 204 of FIG. 2 polymer 110 is formed on the bottom
and sidewalls 108 of the first etched cavity as shown in FIG. 1C.
Typically the polymer 110 is thicker on the bottom of the cavity
under the opening 106 and gets thinner on the sidewalls 108 of the
cavity away from under the opening 106. The polymer deposition step
is typically performed using a plasma with a fluorocarbon gas,
C.sub.xH.sub.yF.sub.z, such as CH.sub.4, CHF.sub.3,
CH.sub.2F.sub.2, C.sub.2F.sub.6, C.sub.3F.sub.6, and
C.sub.4F.sub.8.
[0016] Example polymer deposition process conditions are 10 mT
pressure, 3800 Watts source power, 0 Watts bias power, 200 sccm
C.sub.4F.sub.8, and a temperature of 15.degree. C.
[0017] In step 206 of FIG. 2 an optional ashing step may be
performed to remove the polymer from the sidewalls 108 of the
cavity where the polymer is thin as shown in FIG. 1D. In some cases
so little polymer may be formed in the sidewalls that a separate
ashing step is unnecessary. Instead a breakthrough etch step to
remove minor amounts of polymer may be performed at the beginning
of the subsequent SF.sub.6 silicon etch. In the example embodiment
a plasma ashing step with oxygen is used.
[0018] Example ashing process conditions are 30 mT pressure, 2500
Watts source power, 0 Watts bias power, 200 sccm oxygen, and a
temperature of 15.degree. C.
[0019] In step 208 of FIG. 2, a second cavity etch is performed as
shown in FIG. 1E. The polymer 110 covering the bottom of the trench
prevents the cavity from being etched deeper into the substrate.
The etchant enlarges the cavity laterally forming second cavity
etch walls 112 that are spaced at a greater lateral distance from
the opening than the lateral walls 108 of the first cavity etch
(step 202).
[0020] In step 210 of FIG. 2 the polymer may be removed from the
cavity using an ashing step, as shown in FIG. 1F. This step is
optional if the final trench width has not been achieved. In the
example embodiment a plasma ashing step containing oxygen is used.
The ashing conditions are described previously.
[0021] In step 212 of FIG. 2, a determination may be made to see if
the target cavity width has been achieved. If the target cavity
width is achieved the wafers may be sent on to the next process
step in the manufacturing flow (step 214 in FIG. 2).
[0022] If, however, the target cavity width is not achieved, the
wafers may be returned to step 204 in FIG. 2 and the process of
polymer deposition followed by another cavity etch step may be
repeated until the target width is achieved.
[0023] A second polymer deposition step followed by a third cavity
etch is illustrated in FIGS. 1G through FIG. 1J. More than three
cycles of polymer deposition, cavity etch, and polymer removal may
be performed to achieve the desired cavity width without etching
the cavity deeper.
[0024] In FIG. 1G (step 204 of FIG. 2), polymer is deposited onto
the cavity sidewalls 108 and 112.
[0025] In FIG. 1H (step 206 of FIG. 2), an optional ashing step is
performed to remove the polymer 114 from the lateral sidewalls 112
of the cavity if it is needed.
[0026] In FIG. 1I (step 208 of FIG. 2), a third cavity etch is
performed. The polymer 114 on the bottom of the cavity walls 108
and 112 prevents the cavity from being etched deeper into the
silicon. The exposed second cavity etch walls 112 are etched
laterally away from the opening 106 to form third etch cavity walls
116.
[0027] In FIG. 1J, (step 210 of FIG. 2) the polymer is removed from
the cavity by ashing. As shown in FIG. 1J, the width of the cavity
is substantially wider than the depth of the cavity. As an example,
the width may be approximately twice the depth or more. This cavity
is formed without the addition of an etch stop layer in the
substrate which may add significant complexity and cost to the
manufacturing flow. Cavities formed when an etch stop layer is used
typically have a uniform depth across the width of the cavity. The
depth of the cavity formed using the embodiment process is not
uniform in depth across the width of the cavity as is illustrated
in FIG. 1F and FIG. 1J.
[0028] While various embodiments of the present invention have been
described above, it should be understood that they have been
presented by way of example only and not limitation. Numerous
changes to the disclosed embodiments can be made in accordance with
the disclosure herein without departing from the spirit or scope of
the invention. Thus, the breadth and scope of the present invention
should not be limited by any of the above described embodiments.
Rather, the scope of the invention should be defined in accordance
with the following claims and their equivalents.
* * * * *