U.S. patent application number 15/191628 was filed with the patent office on 2017-06-08 for nanowires for pillar interconnects.
The applicant listed for this patent is International Business Machines Corporation. Invention is credited to Charles L. Arvin, Jeffrey P. Gambino, Christopher D. Muzzy, Wolfgang Sauter.
Application Number | 20170162436 15/191628 |
Document ID | / |
Family ID | 58799251 |
Filed Date | 2017-06-08 |
United States Patent
Application |
20170162436 |
Kind Code |
A1 |
Arvin; Charles L. ; et
al. |
June 8, 2017 |
NANOWIRES FOR PILLAR INTERCONNECTS
Abstract
An embodiment of the invention may include a semiconductor
structure, and method of forming the semiconductor structure. The
semiconductor structure may include a first set of pillars located
on a first substrate. The semiconductor structure may include a
second set of pillars located on a second substrate. The
semiconductor structure may include a joining layer connecting the
first pillar to the second pillar. The semiconductor structure may
include an underfill layer located between the first and second
substrate.
Inventors: |
Arvin; Charles L.;
(Poughkeepsie, NY) ; Gambino; Jeffrey P.;
(Portland, OR) ; Muzzy; Christopher D.;
(Burlington, VT) ; Sauter; Wolfgang; (Burke,
VT) |
|
Applicant: |
Name |
City |
State |
Country |
Type |
International Business Machines Corporation |
Armonk |
NY |
US |
|
|
Family ID: |
58799251 |
Appl. No.: |
15/191628 |
Filed: |
June 24, 2016 |
Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
|
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14957684 |
Dec 3, 2015 |
|
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15191628 |
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Current U.S.
Class: |
1/1 |
Current CPC
Class: |
H01L 25/0657 20130101;
H01L 2224/03912 20130101; H01L 2224/81365 20130101; H01L 2224/92125
20130101; H01L 2224/05666 20130101; H01L 2224/11474 20130101; H01L
21/76838 20130101; H01L 23/3171 20130101; H01L 2224/05171 20130101;
H01L 2224/2919 20130101; H01L 2224/83102 20130101; H01L 2224/13124
20130101; H01L 2224/05666 20130101; H01L 2224/73204 20130101; H01L
24/16 20130101; H01L 2224/0401 20130101; H01L 2224/8112 20130101;
H01L 2224/81345 20130101; H01L 2224/03416 20130101; H01L 2224/0345
20130101; H01L 2224/81193 20130101; H01L 2225/06513 20130101; H01L
2924/00014 20130101; H01L 2924/00014 20130101; H01L 2924/00014
20130101; H01L 2924/01029 20130101; H01L 2924/00014 20130101; H01L
2924/00014 20130101; H01L 2924/01029 20130101; H01L 2924/069
20130101; H01L 2924/01074 20130101; H01L 2924/00012 20130101; H01L
2924/00012 20130101; H01L 2924/00014 20130101; H01L 2924/01024
20130101; H01L 2924/01074 20130101; H01L 2924/00012 20130101; H01L
2924/014 20130101; H01L 2924/00012 20130101; H01L 2924/00014
20130101; H01L 2924/00012 20130101; H01L 2924/01024 20130101; H01L
2924/00014 20130101; H01L 2924/01074 20130101; H01L 2924/00014
20130101; H01L 2924/00014 20130101; H01L 2924/00012 20130101; H01L
21/563 20130101; H01L 2224/11462 20130101; H01L 2224/81801
20130101; H01L 2924/20109 20130101; H01L 24/83 20130101; H01L
2224/13017 20130101; H01L 2224/13019 20130101; H01L 21/7684
20130101; H01L 2224/1145 20130101; H01L 2224/11464 20130101; H01L
2924/20106 20130101; H01L 2224/81801 20130101; H01L 2224/13026
20130101; H01L 2224/05147 20130101; H01L 25/50 20130101; H01L 24/11
20130101; H01L 2224/11452 20130101; H01L 2224/1146 20130101; H01L
2224/81815 20130101; H01L 24/13 20130101; H01L 2224/1147 20130101;
H01L 2924/00012 20130101; H01L 2924/00014 20130101; H01L 2924/00012
20130101; H01L 2224/13082 20130101; H01L 2224/81203 20130101; H01L
24/32 20130101; H01L 2224/13157 20130101; H01L 2224/05184 20130101;
H01L 2224/2919 20130101; H01L 2924/2011 20130101; H01L 2224/05571
20130101; H01L 2224/131 20130101; H01L 2224/13184 20130101; H01L
24/05 20130101; H01L 24/81 20130101; H01L 2224/05166 20130101; H01L
2224/05671 20130101; H01L 2224/1147 20130101; H01L 2224/13124
20130101; H01L 24/29 20130101; H01L 2224/13078 20130101; H01L
2224/81815 20130101; H01L 2224/83102 20130101; H01L 24/06 20130101;
H01L 24/03 20130101; H01L 2224/11452 20130101; H01L 2224/05647
20130101; H01L 2224/81203 20130101; H01L 21/56 20130101; H01L
2224/05647 20130101; H01L 2224/05671 20130101; H01L 2224/11462
20130101; H01L 2224/131 20130101; H01L 2224/03416 20130101; H01L
2224/13147 20130101; H01L 2224/0345 20130101; H01L 2224/13155
20130101; H01L 2224/1601 20130101; H01L 2224/05166 20130101; H01L
2224/11632 20130101; H01L 2224/13157 20130101; H01L 2224/13155
20130101; H01L 2224/1145 20130101; H01L 2224/11464 20130101; H01L
23/5283 20130101; H01L 2224/13184 20130101; H01L 2924/3511
20130101; H01L 2924/20107 20130101; H01L 2224/81385 20130101; H01L
2224/13147 20130101; H01L 2224/03452 20130101; H01L 2224/1601
20130101; H01L 2224/1146 20130101; H01L 2224/05666 20130101; H01L
2224/03452 20130101; H01L 2924/20108 20130101 |
International
Class: |
H01L 21/768 20060101
H01L021/768; H01L 23/31 20060101 H01L023/31; H01L 23/00 20060101
H01L023/00; H01L 23/528 20060101 H01L023/528; H01L 21/56 20060101
H01L021/56 |
Claims
1-9. (canceled)
10. A method of forming a semiconductor structure comprising:
forming a plurality of first conductive pillars on a first
substrate, wherein forming the plurality of first conductive
pillars comprises: forming a masking layer on a masked region of a
first substrate, and wherein an unmasked region of the first
substrate comprises a plurality of electrical connections; and
forming a conductive material in the unmasked region, forming the
plurality of first conductive pillars on the first substrate;
forming a first set of conductive nanowires on a first surface of
the plurality of first conductive pillars, wherein forming a first
set of conductive nanowires comprises: forming a porous layer on a
surface of the plurality of first conductive pillars, wherein the
porous layer comprises a plurality of pores extending from an
exposed surface of the porous layer to the surface of the plurality
of the first conductive pillars; and forming a conductive material
in the plurality of pores; following the formation of the first set
of conductive nanowires, removing the masking layer and porous
layer using laser ablation, wherein laser ablation selectively
removes the masking layer and porous layer with respect to the
first set of conductive nanowires; forming a plurality of second
conductive pillars on a second substrate; forming a second set of
conductive nanowires on a second surface of the plurality of second
conductive pillars; and forming an electrical connection between
the first pillar and the second pillar by joining the first set of
conductive nanowires with the second set of conductive
nanowires.
11. The method of claim 10, wherein the porous layer has a
concentration of 4 pores/(m).sup.2 to 400 pores/(m).sup.2.
12. The method of claim 10, wherein forming an electrical
connection between the first pillar and the second pillar
comprises: aligning the first set of conductive nanowires with the
second set of conductive nanowires; and performing thermal
compression to join the first set of conductive nanowires to the
second set of conductive nanowires.
13. The method of claim 12, wherein thermal compression is
performed at a temperature of about 150.degree. C. to about
230.degree. C.
14. The method of claim 10, further comprising depositing an
underfill layer between the first substrate and the second
substrate.
15. The method of claim 10, further comprising forming a seed layer
above the first substrate, wherein the seed layer comprises a
material selected from the group consisting of: titanium, titanium
tungsten, and titanium tungsten chrome copper; and wherein the
forming a conductive material in the unmasked region, comprises
forming the plurality of first conductive pillars on seed layer
located on the first substrate.
16. The method of claim 15, wherein removing the masking layer
using laser ablation further comprises removing the seed layer
using laser ablation.
Description
CROSS REFERENCE TO RELATED APPLICATION
[0001] This application is a Continuation-in-Part Application of
pending U.S. patent application Ser. No. 14/957,684 filed Dec. 3,
2015.
BACKGROUND
[0002] The present invention relates generally to semiconductor
structures and methods of manufacture and, more particularly, to
connect interconnect structures with copper nanowires.
[0003] New integrated circuit technologies include
three-dimensional integrated circuits. One type of 3D integrated
circuit may include two or more layers of active electronic
components stacked vertically and electrically joined with
through-substrate vias and solder bumps. The 3D integrated circuit
may provide numerous benefits such as increased package density
yielding a smaller footprint, and improved bandwidth due to the
short connection lengths made possible by the use of
through-silicon-vias. The 3D integrated circuit described above may
be fabricated in any number of known methods. Some 3D integrated
circuits may include a silicon interposer which may be used to
re-direct circuitry between a ship carrier and one or more top
chips.
[0004] Copper pillars are a chip-to-chip interconnect technology
used to enhance electromigration performance, to reduce the pitch
of interconnects, and to provide for a larger gap, or standoff,
between individual chips for underfill flow over conventional
solder controlled collapse chip connections (C4 connections). In
copper pillar technology, a small amount of solder is still
required to connect and join the copper pillars of one chip to a
pad of another chip or substrate.
BRIEF SUMMARY
[0005] An embodiment of the invention may include a method of
forming a semiconductor structure. The method may include forming a
plurality of first conductive pillars on a first substrate. The
method may include forming a first set of conductive nanowires on a
first surface of the plurality of first conductive pillar. The
method may include forming a plurality of second conductive pillars
on a second substrate. The method may include forming a second set
of conductive nanowires on a second surface of the plurality of
second conductive pillar. The method may include forming an
electrical connection between the first pillar and the second
pillar by joining the first set of conductive nanowires with the
second set of conductive nanowires.
[0006] An embodiment of the invention may include a method of
forming a semiconductor structure. The method may include forming a
plurality of first conductive pillars on a first substrate. The
method may include forming a plurality of conductive nanowires on a
first surface of the plurality of first conductive pillar. The
method may include forming a plurality of second conductive pillars
on a second substrate. The method may include forming a solder bump
on a second surface of the plurality of second conductive pillar.
The method may include forming an electrical connection between the
first pillar and the second pillar by joining the plurality of
conductive nanowires with the solder bump.
[0007] An embodiment of the invention may include a semiconductor
structure. The semiconductor structure may include a first set of
pillars located on a first substrate. The semiconductor structure
may include a second set of pillars located on a second substrate.
The semiconductor structure may include a joining layer connecting
the first pillar to the second pillar. The semiconductor structure
may include an underfill layer located between the first and second
substrate.
BRIEF DESCRIPTION OF THE DRAWINGS
[0008] The following detailed description, given by way of example
and not intended to limit the invention solely thereto, will best
be appreciated in conjunction with the accompanying drawings, in
which not all structures may be shown.
[0009] FIG. 1 represents a cross sectional view depicting a bond
pad on a substrate, according to an example embodiment;
[0010] FIG. 2 represents a cross sectional view depicting forming a
seed layer and patterning a photoresist, according to an example
embodiment;
[0011] FIG. 3 represents a cross sectional view depicting forming a
conductive pillar, according to an example embodiment;
[0012] FIG. 4 represents a cross sectional view depicting forming a
porous layer above the conductive pillar, according to an example
embodiment;
[0013] FIG. 5 represents a cross sectional view depicting forming
conductive nanowires on the conductive pillar, and removing the
porous layer and photoresist, according to an example
embodiment;
[0014] FIG. 6 represents a cross sectional view depicting joining
the structure of FIG. 5 to a second substrate, according to an
example embodiment;
[0015] FIG. 7 represents a cross sectional view depicting forming
an underfill between the two substrates, according to an example
embodiment;
[0016] FIG. 8 represents a cross sectional view depicting joining
the structure of FIG. 5 to a third substrate, according to an
example embodiment; and
[0017] FIG. 9 represents a cross sectional view depicting forming
an underfill between the two substrates, according to an example
embodiment.
[0018] The drawings are not necessarily to scale. The drawings are
merely schematic representations, not intended to portray specific
parameters of the invention. The drawings are intended to depict
only typical embodiments of the invention. In the drawings, like
numbering represents like elements.
DETAILED DESCRIPTION
[0019] Detailed embodiments of the claimed structures and methods
are disclosed herein; however, it can be understood that the
disclosed embodiments are merely illustrative of the claimed
structures and methods that may be embodied in various forms. This
invention may, however, be embodied in many different forms and
should not be construed as limited to the exemplary embodiments set
forth herein. Rather, these exemplary embodiments are provided so
that this disclosure will be thorough and complete and will fully
convey the scope of this invention to those skilled in the art.
[0020] For purposes of the description hereinafter, the terms
"upper", "lower", "right", "left", "vertical", "horizontal", "top",
"bottom", and derivatives thereof shall relate to the disclosed
structures and methods, as oriented in the drawing figures. It will
be understood that when an element such as a layer, region, or
substrate is referred to as being "on", "over", "beneath", "below",
or "under" another element, it may be present on or below the other
element or intervening elements may also be present. In contrast,
when an element is referred to as being "directly on", "directly
over", "directly beneath", "directly below", or "directly
contacting" another element, there may be no intervening elements
present. Furthermore, the terminology used herein is for the
purpose of describing particular embodiments only and is not
intended to be limiting of the invention. As used herein, the
singular forms "a," "an," and "the" are intended to include the
plural forms as well, unless the context clearly indicates
otherwise.
[0021] In the interest of not obscuring the presentation of
embodiments of the present invention, in the following detailed
description, some processing steps or operations that are known in
the art may have been combined together for presentation and for
illustration purposes and in some instances may have not been
described in detail. In other instances, some processing steps or
operations that are known in the art may not be described at all.
It should be understood that the following description is rather
focused on the distinctive features or elements of various
embodiments of the present invention.
[0022] Semiconductor processing generally requires electrically
connecting the semiconductor structures on a substrate to those of
other substrates, as in 3-D chip fabrication, or to electrical
connections on dies used for back end of the line connections.
Solder interconnects have traditionally been used to form these
connections, however the temperatures required to form the
connections may create warping due to differing thermal expansion
coefficients of the substrates to be joined. Additionally, as the
electrical connections become increasingly small and close
together, misalignment of the connections may cause the solder
interconnections to block the path of underfill used to
mechanically join and seal the component from the environment, thus
leading to decreased chip performance.
[0023] In the following paragraphs, a process and device are
described using conductive nanowires on a conductive pillar, such
as copper nanowires on a copper pillar, as a mechanism to reduce
the temperature necessary to form an electromechanical connection
between conductive portions of two substrates. In one embodiment,
conductive nanowires are used on both substrates, and the fusion of
the nanowires forms the electromechanical connection between the
substrates, and eliminates the need for traditional soldering
techniques. In another embodiment, conductive nanowires on one
substrate reduce the amount of solder on the other substrate
necessary to form an electromechanical connection, thus reducing
the amount of solder that may impede underfill material from
entering the spaces between the two substrates.
[0024] Referring now to FIGS. 1-3, cross section views illustrating
the preliminary process steps of forming of a pillar structure 100
are shown. In particular, FIG. 1 illustrates a bond pad 110 and
passivation layer 120 located on a first substrate 100. The first
substrate 100 may be either a dielectric layer formed above a
device (not shown) or a semiconductor substrate. Further, the first
substrate 100 may contain semiconductor structures electrically
connected to bond pad 110. The bond pad 110 may be any electrically
conductive material that leads to underlying structures on the
device. For example, the bond pad 110 may include, for example,
copper, aluminum, or tungsten. Passivation layer 120 may be any
electrical insulating material, isolating each bond pad 110 from
the others. Passivation layer 120 may include any suitable
dielectric material, for example, silicon nitride
(Si.sub.3N.sub.4), silicon carbide (SiC), silicon carbon nitride
(SiCN), hydrogenated silicon carbide (SiCH).
[0025] Referring to FIG. 2, a seed layer 130 and a photoresist
material 140 may be formed above the bond pad 110 and passivation
layer 120. The seed layer 130 may be deposited on the bond pad 110
and passivation layer 120 using any conventional deposition
technique known in the art, such as, for example, atomic layer
deposition (ALD), chemical vapor deposition (CVD), low pressure CVD
(LPCVD), physical vapor deposition (PVD), molecular beam deposition
(MBD), pulsed laser deposition (PLD), liquid source misted chemical
deposition (LSMCD), sputtering, or spin-on deposition.. The seed
layer 130 may encourage the adhesion of a conductive pillar 150 to
the bond pad 110. The seed layer 130 may be composed of a metal or
metal alloy, such as, for example, titanium, titanium tungsten, or
titanium tungsten chrome copper. While the current embodiment shows
the use of a seed layer 130, additional embodiments may use
materials or methods that do not require the seed layer 130.
[0026] A photoresist material 140 may be deposited on passivation
layer 120 using any conventional deposition technique, such as
those listed above. In an embodiment, the photoresist material 140
may be deposited, for example, using a dry film lamination
technique or spin on liquid resist technique. The photoresist
material 140 may then be subjected to a conventional lithographic
techniques (i.e., light exposure and development) to solidify the
photoresist material and form an opening 145.
[0027] Referring to FIG. 3, a conductive pillar 150 may be formed
in the opening 145 and in contact with seed layer 130 by depositing
a conductive material in the opening. In an embodiment, the
conductive material may be copper or an alloy thereof. In another
embodiment, a different metal/metal alloy may be used for the
conductive pillar 150 such as, for example, cobalt or nickel.
Although other metals are contemplated by the invention, copper or
copper alloys will be referred to hereinafter as the material used
with the invention, but this should not be considered a limiting
feature. The conductive pillar 150 may have a height ranging from
approximately 20 .mu.m to approximately 60 .mu.m.
[0028] Referring to FIG. 4, a porous layer 160 may be formed above
photoresist material 140 and the conductive pillar 150. The porous
layer 160 contains one or more pores that extend from the bottom
surface of the porous layer SB to the top surface of the porous
layer S.sub.T. In a preferred embodiment, the pores may range in
diameter from 25 to 500 nm, and may be in a concentration of 4 to
400 pores/(.mu.m).sup.2. The porous layer 160 may have a thickness
of 50 to 1000 nm. In one embodiment, the porous layer 160 may be
formed using a polymerization process that results in a porous
material, such as, for example, forming a polycarbonate membrane.
In another example, an anodized alumina oxide membrane may be
formed.
[0029] Referring to FIG. 5, first conductive nanowires 170 are
formed on the top surface of the conductive pillar 150, and porous
layer 160 and photoresist material 140 are removed. During
formation of the first conductive nanowires 170, the material may
take the shape of the pores of porous layer 160, and may only join
with the top surface of conductive pillar 150. The first conductive
nanowires 170 may contain, for example, copper, nickel, aluminum,
or tungsten. In an example embodiment, the conductive nanowires 170
and conductive pillar 150 may be formed using the same material.
The first conductive nanowires 170 may be formed using a filing
technique such as electroplating, electrophoresis, electroless
plating, chemical vapor deposition, physical vapor deposition or a
combination of methods.
[0030] Still referring to FIG. 5, the porous layer 160, the
photoresist material 140 and seed layer 130 beneath the photoresist
material 140 may be removed to leave the final pillar structure,
first conductive nanowires 170 and pillar seed layer 135. In an
embodiment, the photoresist material 140 may be stripped selective
to the conductive pillar 150 and passivation layer 120 using laser
ablation. Laser ablation is a technique in which a laser beam
irradiates the surface of a material to evaporate or sublimate the
material away, and thus leaving the underlying structures. By
selecting the right wavelengths of light, and pulses of the laser
light, laser ablation may only heat and remove the desired material
without unnecessarily heating surrounding materials. Laser ablation
selectively removes the unnecessary materials, without damaging (or
with minimal damage) to the first conductive nanowires 170, as
compared to traditional wet or dry etching techniques that would
dissolve the conductive nanowires 170 due to the narrow diameters
involved.
[0031] FIGS. 6 and 7 shows a first embodiment of joining the
structure pictured in FIG. 5 to another substrate. Referring to
FIGS. 6 and 7, the conductive pillars 150 and first conductive
nanowires 170 may be joined to a first conductive structure 210,
located on a second substrate 200, using a second conductive
nanowire 220. The processes for making the first conductive
structure 210 and the second conductive nanowire 220 may be the
same as those for the conductive pillars 150 and first conductive
nanowires, respectively. Additionally, the second substrate 200 may
contain additional semiconductor structures, similar to those
located on the first substrate 100. Further, the space between the
first substrate 100 and second substrate 200 may be filled with an
underfill layer 250.
[0032] Still referring to FIG. 6, the first substrate 100 may be
joined to the second substrate 200 using thermal compression to
create an electrical connection between conductive pillar 150 and
conductive structure 210. A thermal compression tool, such as a
flip-chip bonder, may be used to apply the temperature and the
pressure, and form the electrical connection by fusing the first
conductive nanowires 170 with the second conductive nanowires 220,
forming a nanowire fused connection 230 (FIG. 7) between the two
structures. This may allow for semiconductor structures on the
first substrate 100 to be electrically connected to features or
structures located on the second substrate 200. During bonding,
temperatures below the reflow temperature of material of the first
conductive nanowires 170 and the second conductive nanowires 220
may fuse the two structures together as the increased surface area
of the nanowires enables a phase transition, or reorganization of
the structure of the adjoining materials, at a temperature much
lower than the bulk melting point of the material, thus creating an
electromechanical connection between the two structures. The
temperatures may range from about 150.degree. C. to about
230.degree. C., and more preferably from about 150.degree. C. to
about 200.degree. C., and the temperatures used in the thermal
compression tool may range from about 200.degree. C. to about
400.degree. C. The applied temperatures of the thermal compression
tool may depend on the interconnect material and chip size. A
pressure ranging from about 6.0.times.10.sup.4 Pa to about
6.0.times.10.sup.5 Pa may be applied during the assembly using the
thermal compression tool, although this pressure may be adjusted
based on the contact area and materials to be interconnected. In
one embodiment, a force ranging from about 5 N to about 50 N may be
applied. The force too may be adjusted based on the contact area
and materials to be interconnected. In some cases, there may be
between 1,000 and 170,000 connections between components.
[0033] Referring to FIG. 7, the space created between the first
substrate 100 and the second substrate 200 is then underfilled,
with underfill layer 250, in order to strengthen the
interconnections. A curable non-conductive polymeric underfill
material is dispensed onto the substrate adjacent to the chip and
is drawn into the gap by capillary action, forming underfill layer
250. The underfill material provides environmental protection, and
mechanically locks together the first substrate 100 and the second
substrate 200 so that differences in thermal expansion of the two
materials do not break the nanowire fused connection 230. The
underfill material may comprise one or more polymerizable monomers,
polyurethane prepolymers, constituents of block copolymers,
constituents of radial copolymers, initiators, catalysts,
cross-linking agents, stabilizers, and the like. Such materials
polymeric materials contain molecules that are chained or
cross-linked to form a strong bonding material as they are cured
and hardened.
[0034] A resultant semiconductor structure is created, where an
electrical connection is formed between the first substrate 100 and
second substrate 200 through the fused connection 230. The fused
connection 230 represents an electrically conductive region formed
by the first conductive nanowires 170 and the second conductive
nanowires 220, thus allowing structures or devices on the first
substrate 100 to be electrically connected, and thus send signals,
to structures or devices located on the second substrate 200.
[0035] FIGS. 8 and 9 shows a second embodiment of joining the
structure pictured in FIG. 5 to another substrate. Referring to
FIGS. 8 and 9, the conductive pillars 150 and first conductive
nanowires 170 may be joined to a second conductive structure 310,
located on a third substrate 300, using a solder bump 320. The
processes for making the second conductive structure 310 may be the
same as those for the conductive pillars 150. Additionally, the
third substrate 300 may contain additional semiconductor
structures, similar to those located on the first substrate 100.
Further, the space between the first substrate 100 and third
substrate 300 may be filled with an underfill layer 350.
[0036] Still referring to FIG. 8, the first substrate 100 may be
joined to the third substrate 300 using thermal compression to
create an electrical connection between conductive pillar 150 and
second conductive structure 310. A thermal compression tool, such
as a flip-chip bonder, may be used to apply the temperature and the
pressure, and form the electrical connection using, for example,
the first conductive nanowire 170 and the solder bump 320. A
temperature just below the reflow temperature of the solder may be
used to form the requisite electromechanical connection, as the
increased surface area of the first conductive nanowire 170 may
reduce the temperature necessary to achieve a structural
reorganization of the solder and the copper to create an
electromechanical connection, referred to as solder fused
connection 330, between the first conductive nanowire 170 and the
solder bump 320. The reflow temperatures of common lead-free solder
bumps may range from about 210.degree. C. to about 250.degree. C.,
and the temperatures used in the thermal compression tool may range
from about 230.degree. C. to about 400.degree. C. The applied
temperatures of the thermal compression tool may depend on the
interconnect material and chip size. A pressure ranging from about
6.0.times.10.sup.4 Pa to about 6.0.times.10.sup.5 Pa may be applied
during the 3D assembly using the thermal compression tool, although
this pressure may be adjusted based on the contact area and
materials to be interconnected. In one embodiment, a force ranging
from about 5 N to about 50 N may be applied. The force too may be
adjusted based on the contact area and materials to be
interconnected. In some cases, there may be between 1,000 and
170,000 connections between components.
[0037] Referring to FIG. 9, the space created between the first
substrate 100 and the third substrate 300 is then underfilled, with
underfill layer 350, in order to strengthen the interconnections. A
curable non-conductive polymeric underfill material is dispensed
onto the substrate adjacent to the chip and is drawn into the gap
by capillary action, forming underfill layer 350. The underfill
material provides environmental protection, and mechanically locks
together the first substrate 100 and the second substrate 200 so
that differences in thermal expansion of the two materials do not
break the solder fused connection 330. The underfill material may
comprise one or more polymerizable monomers, polyurethane
prepolymers, constituents of block copolymers, constituents of
radial copolymers, initiators, catalysts, cross-linking agents,
stabilizers, and the like. Such materials polymeric materials
contain molecules that are chained or cross-linked to form a strong
bonding material as they are cured and hardened.
[0038] A resultant semiconductor structure is created, where an
electrical connection is formed between the first substrate 100 and
third substrate 300 through the solder fused connection 330. The
solder fused connection 330 represents an electrically conductive
region formed by the first conductive nanowires 170 and the solder
bump 320, thus allowing structures or devices on the first
substrate 100 to be electrically connected, and thus send signals,
to structures or devices located on the second substrate 200.
[0039] The descriptions of the various embodiments of the present
invention have been presented for purposes of illustration, but are
not intended to be exhaustive or limited to the embodiments
disclosed. Many modifications and variations will be apparent to
those of ordinary skill in the art without departing from the scope
and spirit of the described embodiments. The terminology used
herein was chosen to best explain the principles of the embodiment,
the practical application or technical improvement over
technologies found in the marketplace, or to enable others of
ordinary skill in the art to understand the embodiments disclosed
herein.
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