U.S. patent application number 14/883638 was filed with the patent office on 2017-04-20 for ic device having patterned, non-conductive substrate.
The applicant listed for this patent is FREESCALE SEMICONDUCTOR, INC.. Invention is credited to Poh Leng Eu, KAI YUN YOW.
Application Number | 20170110339 14/883638 |
Document ID | / |
Family ID | 58524216 |
Filed Date | 2017-04-20 |
United States Patent
Application |
20170110339 |
Kind Code |
A1 |
YOW; KAI YUN ; et
al. |
April 20, 2017 |
IC DEVICE HAVING PATTERNED, NON-CONDUCTIVE SUBSTRATE
Abstract
A patterned, non-conductive substrate for an integrated circuit
(IC) package has a die side configured to receive a die and a lead
side opposite the die side. A pattern formed in the substrate
defines openings (e.g., holes, steps, grooves, and/or cavities)
that extend between the die side and the lead side of the
substrate. In the IC package, the openings are filled with
conductive material (e.g., solder) that supports electrical
connections between bond pads on the die and leads formed from the
conductive material. The substrate can be used to form a relatively
inexpensive, quad flat no-lead (QFN) IC package without using a
metal lead frame and without bond wires.
Inventors: |
YOW; KAI YUN; (Petaling
Jaya, MY) ; Eu; Poh Leng; (Petaling Jaya,
MY) |
|
Applicant: |
Name |
City |
State |
Country |
Type |
FREESCALE SEMICONDUCTOR, INC. |
Austin |
TX |
US |
|
|
Family ID: |
58524216 |
Appl. No.: |
14/883638 |
Filed: |
October 15, 2015 |
Current U.S.
Class: |
1/1 |
Current CPC
Class: |
H01L 24/92 20130101;
H01L 2224/48247 20130101; H01L 23/49866 20130101; H01L 2224/244
20130101; H01L 2224/244 20130101; H01L 2224/245 20130101; H01L
2224/48091 20130101; H01L 2224/83192 20130101; H01L 2924/181
20130101; H01L 2224/73265 20130101; H01L 2224/2405 20130101; H01L
23/49805 20130101; H01L 21/486 20130101; H01L 2224/24227 20130101;
H01L 2224/241 20130101; H01L 2224/244 20130101; H01L 2224/73265
20130101; H01L 2224/32225 20130101; H01L 2224/2919 20130101; H01L
2224/32245 20130101; H01L 24/32 20130101; H01L 2224/83191 20130101;
H01L 2224/73217 20130101; H01L 2224/82385 20130101; H01L 2224/8385
20130101; H01L 2224/244 20130101; H01L 2224/29036 20130101; H01L
2924/15313 20130101; H01L 23/49811 20130101; H01L 24/82 20130101;
H01L 2924/181 20130101; H01L 24/83 20130101; H01L 24/24 20130101;
H01L 2224/245 20130101; H01L 2224/8385 20130101; H01L 2924/1433
20130101; H01L 2924/00014 20130101; H01L 2924/01028 20130101; H01L
2924/01028 20130101; H01L 2224/32245 20130101; H01L 2924/01029
20130101; H01L 2924/00 20130101; H01L 2924/01028 20130101; H01L
2924/01029 20130101; H01L 2924/01079 20130101; H01L 2924/00012
20130101; H01L 2924/01079 20130101; H01L 2924/00014 20130101; H01L
2924/01046 20130101; H01L 2924/01079 20130101; H01L 2224/48247
20130101; H01L 2924/00014 20130101; H01L 2924/00014 20130101; H01L
2924/01046 20130101; H01L 2924/00012 20130101; H01L 2224/244
20130101; H01L 2924/014 20130101; H01L 2224/48091 20130101; H01L
2224/92144 20130101; H01L 23/3121 20130101; H01L 24/73 20130101;
H01L 2224/82104 20130101; H01L 21/4853 20130101; H01L 2224/241
20130101; H01L 23/49827 20130101; H01L 2224/244 20130101 |
International
Class: |
H01L 21/48 20060101
H01L021/48; H01L 23/498 20060101 H01L023/498 |
Claims
1. An integrated circuit package, comprising: a non-conductive
substrate having a die side configured to receive an IC die and a
lead side opposite the die side, a pattern formed on the substrate,
wherein the pattern defines openings that extend between the die
side and the lead side of the substrate, and wherein the openings
comprise a plurality of holes that extend vertically from the lead
side to the die side; an IC die having an active side with bond
pads, wherein the die is mounted on the die side of the substrate
such that the bond pads contact the holes; and a conductive
material that fills the openings in the substrate and defines leads
on the lead side of the substrate, and forms electrical connections
between the die bond pads and the leads.
2. The integrated circuit package of claim 1, wherein the active
side of the die faces the die side of the substrate.
3. The integrated circuit package of claim 2, wherein no bond wires
connect the die bond pads and the leads of the IC package.
4. The integrated circuit package of claim 2, further comprising a
molding compound that covers the die and the die side of the
substrate.
5. The integrated circuit package of claim 2, further comprising
conductive bumps formed on the die bond pads, wherein the
conductive bumps support electrical connection between the bond
pads and corresponding ones of the leads.
6. The integrated circuit package of claim 2, wherein no conductive
bumps are formed on the die bond pads.
7. The integrated circuit package of claim 1, wherein the openings
in the substrate comprise a plurality of cavities on the lead side
of the substrate filled with the conductive material to form the
leads of the IC package.
8. The integrated circuit package of claim 7, wherein: the openings
in the substrate further comprise a plurality of grooves, each
groove connecting a hole with a corresponding cavity; the die bond
pads coincide with the holes such that the conductive material
filling the holes forms electrical connections to the die bond
pads; and the grooves are filled with the conductive material to
support the electrical connections between the die bond pads and
the package leads.
9. The integrated circuit package of claim 7, wherein: each hole
coincides with a corresponding cavity; and conductive traces are
formed on the substrate die side electrically connecting the die
bond pads and the conductive material filling the corresponding
holes.
10. The integrated circuit package of claim 7, wherein: the die
bond pads coincide with the holes that the conductive material
filling the holes forms electrical connections to the die bond
pads; and conductive traces are formed on the substrate lead side
electrically connecting the conductive material filling the holes
and the package leads.
11. The integrated circuit package of claim 1, wherein the
conductive material comprises solder.
12. A method for assembling an integrated circuit (IC) package,
comprising: (a) providing a substrate having a die side configured
to receive an IC die and a lead side opposite the die side, wherein
a pattern is formed on the substrate that defines openings that
extend between the die side and the lead side; (b) mounting an IC
die on the substrate die side, wherein bond pads on an active
surface of the die are facing the substrate die side; and (c)
applying a conductive material to fill the openings and form
package leads.
13. The method of claim 12, further comprising applying a molding
compound to the substrate die side to encapsulate the die.
14. The method of claim 12, wherein step (c) comprises: applying a
coating of a first material in the openings in the substrate; and
applying the conductive material over the coating of the first
material.
15. The method of claim 14, wherein applying the conductive
material comprises screen printing solder over the coating of the
first material.
16. The method of claim 12, wherein: the openings in the substrate
comprise a plurality of cavities on the lead side of the substrate
and a plurality of holes on the die side of the substrate; and step
(c) comprises: (c1) filling the cavities with the conductive
material to form the package leads; and (c2) filling the holes with
the conductive material to form electrical connections between the
die bond pads and the package leads.
17. The method of claim 16, wherein: the openings in the substrate
further comprise a plurality of grooves, each groove connecting a
hole and a corresponding cavity; the die bond pads coincide with
the holes on the substrate die side; and step (c2) comprises:
filling the holes with the conductive material to form electrical
connections to the die bond pads; and filling the grooves with the
conductive material to form the electrical connections between the
die bond pads and the package leads.
18. The method of claim 16, wherein: each hole coincides with a
corresponding cavity; and further comprising forming conductive
traces on the substrate die side to electrically connect the die
bond pads to the conductive material filling the corresponding
holes.
19. The method of claim 16, wherein: the die bond pads coincide
with the holes on the substrate die side; step (c2) comprises
filling the holes with the conductive material to form electrical
connections to the die bond pads; and further comprising forming
conductive traces on the substrate lead side to electrically
connect the conductive material filling the holes and the package
leads.
20. The method of claim 12, wherein: the openings in the substrate
comprise a plurality of cavities on the substrate lead side and a
plurality of steps on the substrate die side; and step (c)
comprises: filling the cavities with the conductive material to
form the package leads; and filling the steps with the conductive
material to form the electrical connections between the die bond
pads and the package leads.
Description
BACKGROUND
[0001] The present invention relates to integrated circuit (IC)
packaging and, more particularly, an IC package assembled using a
preprinted substrate.
[0002] FIG. 1 is a cross-sectional side view of a conventional,
quad-flat no-lead (QFN), packaged IC device 100. The IC package 100
includes an IC die 102 mounted on a die pad 112 of a metal lead
frame 110 using a suitable die-attach material 104 (e.g., tape or
epoxy). The die 102 is connected to leads 114 of the lead frame 110
with bond wires 106. The die 102, bond wires 106, and upper
surfaces of the lead frame 110 are encapsulated with a
non-conductive molding compound 108. The leads 114 are partially
exposed for electrical connection to another device or a printed
circuit board. Although the design of the IC package 100 is
satisfactory for many applications, it is desirable to design an
alternative IC package that is less expensive to assemble, while
providing the same functionality as the IC package 100.
BRIEF DESCRIPTION OF THE DRAWINGS
[0003] Embodiments of the invention will become more fully apparent
from the following detailed description, the appended claims, and
the accompanying drawings in which like reference numerals identify
similar or identical elements.
[0004] FIG. 1 is a cross-sectional side view of a conventional IC
package;
[0005] FIG. 2A is an X-ray, top plan view of a QFN IC package
according to one embodiment of the invention;
[0006] FIG. 2B is a cross-sectional side view of the IC package of
FIG. 2A along line 2B-2B;
[0007] FIG. 3A is an X-ray, top plan view of the patterned,
non-conductive substrate of FIG. 2;
[0008] FIG. 3B is a cross-sectional side view of the substrate of
FIG. 3A along line 3B-3B;
[0009] FIG. 3C is an cross-sectional side view of the substrate of
FIG. 3A;
[0010] FIG. 4A is an X-ray, top plan view of a sub-assembly that
exists after a die has been mounted active-side-down on a die side
of the substrate of FIG. 2;
[0011] FIG. 4B is a cross-sectional side view of the sub-assembly
of FIG. 4A along line 4B-4B;
[0012] FIG. 5A is an X-ray, top plan view of a sub-assembly that
exists after the sub-assembly of FIG. 4 has been flipped over and
conductive material has been applied to fill holes, grooves, and
cavities of the patterned substrate;
[0013] FIG. 5B is a cross-sectional side view of the sub-assembly
of FIG. 5A along line 5B-5B;
[0014] FIG. 6A is an X-ray, top plan view of a substrate according
to an alternative embodiment of the invention;
[0015] FIG. 6B is a cross-sectional side view of the substrate of
FIG. 6A along line 6B-6BA;
[0016] FIG. 7 is a cross-sectional side view of an IC package
according to another embodiment of the invention;
[0017] FIG. 8A is a top plan view of an active side of the die of
FIG. 7;
[0018] FIG. 8B is a cross-sectional side view of the die of FIG. 8A
along line of FIGS. 8B-8B;
[0019] FIG. 9 is a cross-sectional side view of an IC package
according to another embodiment of the invention;
[0020] FIG. 10 is a cross-sectional side view of an IC package
according to another embodiment of the invention;
[0021] FIG. 11 is a cross-sectional side view of an IC package
according to another embodiment of the invention;
[0022] FIG. 12A is an X-ray, top plan view of an IC package
according to another embodiment of the invention; and
[0023] FIG. 12B is a cross-sectional side view of the IC package of
FIG. 12A along line 12B-12BA.
DETAILED DESCRIPTION
[0024] Detailed illustrative embodiments of the present invention
are disclosed herein. However, specific structural and functional
details disclosed herein are merely representative for purposes of
describing example embodiments of the present invention. The
present invention may be embodied in many alternate forms and
should not be construed as limited to only the embodiments set
forth herein. Further, the terminology used herein is for the
purpose of describing particular embodiments only and is not
intended to be limiting of example embodiments of the
invention.
[0025] As used herein, the singular forms "a," "an," and "the," are
intended to include the plural forms as well, unless the context
clearly indicates otherwise. It further will be understood that the
terms "comprises," "comprising," "includes," and/or "including,"
specify the presence of stated features, steps, or components, but
do not preclude the presence or addition of one or more other
features, steps, or components. It also should be noted that in
some alternative implementations, the functions/acts noted may
occur out of the order noted in the figures. For example, two
figures shown in succession may in fact be executed substantially
concurrently or may sometimes be executed in the reverse order,
depending upon the functionality/acts involved.
[0026] In one embodiment, the present invention provides a packaged
integrated circuit comprising a patterned, non-conductive
substrate. The substrate has a die side configured to receive a die
and a lead side opposite the die side. The pattern of the substrate
defines openings that extend between the die side and the lead side
of the substrate. The openings are filled with conductive material,
such as solder, that supports electrical connections between bond
pads on the die and leads formed from the conductive material.
[0027] In another embodiment, the present invention provides a
method for assembling an IC package. The method comprises (a)
providing a substrate having a die side configured to receive a die
and a lead side opposite the die side, wherein the substrate is
patterned and the pattern defines openings that extend between the
die side and the lead side; (b) mounting a die on the substrate die
side, wherein bond pads of the die face the substrate die side; and
(c) applying a conductive material to fill in the openings to form
leads of the IC package and to connect the leads with the die bond
pads.
[0028] Referring now to FIG. 2A, an X-ray, top plan view of a QFN
IC package 200 according to one embodiment of the invention is
shown. FIG. 2B is a cross-sectional side view of the IC package 200
along the corresponding cut-line of FIG. 2A. The IC package 200 may
function in a substantially identical manner as the IC package 100
of FIG. 1, but, as described further below, can be assembled less
expensively than the IC package 100.
[0029] The IC package 200 comprises an IC die 202 mounted onto the
die side of a patterned, non-conductive substrate 210 using a
suitable die-attach material 204 (e.g., tape or epoxy). The
patterned substrate 210 has eight conductive (e.g., metal) elements
220 formed within holes, grooves, and cavities in the patterned
substrate 210. Each conductive element 220 comprises a vertical via
structure 222 connected to a horizontal routing structure 224
connected to a lead structure 226 that functions as an exposed lead
of the QFN IC package 200. Conductive (e.g., copper or other metal)
bumps 205 provide electrical interconnections between bond pads 203
on the active surface of the IC die 202 and the via structures 222
of the conductive elements 220. The die 202 and the top surface (as
shown in FIG. 2B) of the substrate 210 are encapsulated within a
suitable, non-conducting, molding compound 208.
[0030] The die 202 may comprise any type of integrated circuit,
such as an application specific IC (ASIC), a microprocessor, a
sensor, etc., and the present invention is not limited by the type
of die.
[0031] In certain implementations, the substrate 210 is made of a
suitable plastic, such as Bismaleimide Triazine (BT) resin,
Polyimide, or a pre-molded compound such as G770HC or G700LTD
molding compound from Sumitomo Corporation of Japan. The conductive
elements 220 are made of a suitable metal, such as SW100 solder
from Tatsuta Electronic Materials of Taiwan. The die attach
material 204 is made of a suitable adhesive, such as tape, FH-9011
Die Attach Film (DAF) from Hitachi, Ltd., of Japan, or Ablebond
2025JR epoxy from Henkel Electronics Materials of Belgium. The
conductive bumps 205 are made of a suitable metal, such as copper.
The die bond pads 203 are made of a suitable metal, such as NiPdAu
or copper. The molding compound 208 is made of a suitable
insulating material, such as epoxy.
[0032] Because the IC package 200 is assembled without a
conventional metal lead frame, such as lead frame 110 of FIG. 1,
and without conventional bond wires, such as bond wires 106 of FIG.
1, the IC package 200 can be assembled less expensively than the IC
package 100 of FIG. 1.
[0033] FIGS. 3-5 illustrate a method of assembling the IC package
200 of FIG. 2 in accordance with a preferred embodiment of the
invention.
[0034] FIG. 3A is an X-ray, top plan view of the patterned,
non-conductive substrate 210 of FIG. 2. FIG. 3B is a
cross-sectional side view of the substrate 210 along the
corresponding cut-line of FIG. 3A, and FIG. 3C is an X-ray, side
view of the corresponding side of the substrate 210 of FIG. 3A. As
shown in FIGS. 3A-3C, the substrate 210 has a pattern of holes 312,
grooves 314, and cavities 316 respectively corresponding to the via
structures 222, the routing structures 224, and the lead structures
226 of the patterned substrate 210 of FIG. 2. The patterned,
non-conductive substrate 210 may be fabricated using any suitable
technique, such as by molding, micro drilling, or mechanical
routing.
[0035] FIG. 4A is an X-ray, top plan view of a sub-assembly 400
that exists after the die 202 has been mounted active-side-down
onto the die side of the substrate 210 of FIG. 2. FIG. 4B is a
cross-sectional side view of the sub-assembly 400 along the
corresponding cut-line of FIG. 4A. Note that the die 202 already
has the bumps 205 formed on the die's bond pads 203 before the die
202 is mounted onto the substrate 210. As shown in FIG. 4B, the
bond pads 203 and bumps 205 coincide with the holes 312 in the
substrate 210.
[0036] FIG. 5A is an X-ray, top plan view of a sub-assembly 500
that exists after the sub-assembly 400 of FIG. 4 has been flipped
over and conductive material (e.g., solder) has been applied (e.g.,
by screen printing) to fill the holes 312, the grooves 314, and the
cavities 316 of the patterned substrate 210, thereby respectively
forming the via structures 222, the routing structures 224, and the
lead structures 226 of the conductive elements 220 of FIG. 2. Note
that the bumps 205 help to prevent the solder from flowing onto the
die side of the substrate 210. When the bond pads 203 are made of a
solder-resistant material, such as aluminum, using copper or gold
for the bumps 205 supports solder attachment.
[0037] FIGS. 2A and 2B represents the final assembly of the IC
package 200 after the sub-assembly 500 of FIG. 5 has been flipped
over, and the molding compound 208 has been applied over the die
side of the substrate 210 to encapsulate the die 202.
[0038] FIG. 6A is an X-ray, top plan view of the patterned,
non-conductive substrate 610 according to an alternative embodiment
of the invention. FIG. 6B is a cross-sectional side view of the
substrate 610 along the corresponding cut-line of FIG. 6A.
Substrate 610 is analogous to substrate 210 of FIGS. 2-5 with
analogous elements having analogous labels. In addition, for each
corresponding set of a hole 612, a groove 614, and a cavity 616,
substrate 610 also has an additional hole 618 extending from the
cavity 616 to a relatively wide opening 619 at the other side of
the substrate 610. These additional holes 618 with their wide
openings 619 enable conductive elements (analogous to the
conductive elements 220 of FIG. 2) to be formed for the resulting
IC packages that are more securely anchored within the substrate
610. In particular, when filled with solder to form one of the
conductive elements, the portion of the solder filling the
relatively wide opening 619 helps to anchor the conductive element
within the substrate 610. Those skilled in the art will understand
that other suitable designs for cavities will also provide a
similar anchoring or retention function.
[0039] FIG. 7 is a cross-sectional side view of an IC package 700
according to another embodiment of the invention. IC package 700 is
similar to IC package 200 of FIG. 2 with analogous elements labeled
analogously, except that, in IC package 700, there are no
conductive bumps, analogous to bumps 205 of FIG. 2, mounted onto
the die pads 703 of the die 702. Instead, in IC package 700, the
substrate via structures 722 directly contact the die's bond pads
703. In order to support solder attachment, the bond pads 703 are
formulated with a top layer of a suitable material, such as
(without limitation) NiAu, Cu, or NiPdCu.
[0040] FIG. 8A is a top plan view of the die 702 of FIG. 7, and
FIG. 8B is a cross-sectional side view of the die 702 along the
corresponding cut-line of FIG. 8A. As shown in the figures, the die
pads 703 of the die 702 have no conductive bumps. FIG. 8B also
shows the die-attach material 704 used to secure the die 702 onto
the substrate 710 of FIG. 7.
[0041] FIG. 9 is a cross-sectional side view of an IC package 900
according to another embodiment of the invention. In this
embodiment, the conductive elements 920 are formed by sequentially
applying two different materials onto and into the patterned
substrate 910: first, a layer of paste, such as SW100 conductive
paste by Tatsuta Electronic Materials of Taiwan, is applied to form
a relatively thin coating 921 on the surfaces of the holes,
grooves, and cavities before filling the rest of those volumes with
solder 923. The thin coating of paste may improve the retention of
the conductive elements 920 within the substrate 910 by improving
the bonding between the solder 923 and the substrate 910. Still
other embodiments may involve the sequential application of three
or more different materials to form the conductive elements.
[0042] FIG. 10 is a cross-sectional side view of an IC package 1000
according to another embodiment of the invention. IC package 1000
is similar to IC package 200 of FIG. 2 with analogous elements
labeled analogously, except that, in IC package 1000, (i) the via
structures 1022 and the routing structures 1024 are formed of
conductive paste, while the lead structures 1026 are formed by
applying solder over a coating of the conductive paste, (ii) the
via structures 1022 are connected between the corresponding lead
structures 1026 and the corresponding routing structures 1024,
(iii) the routing structures 1024 are applied on top of the die
side of the substrate 1010, and (iv) the routing structures 1024
are directly connected to the conductive bumps 1005. Note that,
since the bumps 1005 do not coincide with the via structures 1022,
the die 1002 sits higher above the die side of the substrate 1010
and the die-attach material 1004 is thicker than the analogous
elements of IC package 200.
[0043] FIG. 11 is a cross-sectional side view of an IC package 1100
according to another embodiment of the invention. IC package 1100
is similar to IC package 700 of FIG. 7 with analogous elements
labeled analogously, except that, in IC package 1100, (i) the via
structures 1122 and the routing structures 1124 are formed of
conductive paste, while the lead structures 1126 are formed of
solder and (ii) the routing structures 1124 are applied onto the
lead side of the substrate 1110. Also, in IC package 1100, the die
attach material 1104 resides in a recess 1111 on the die side of
the substrate 1110, such that the die 1102 sits lower onto the die
side of the substrate 1110.
[0044] FIG. 12A is an X-ray, top plan view of an IC package 1200,
according to one embodiment of the invention. FIG. 12B is a
cross-sectional side view of the IC package 1200 along the
corresponding cut-line of FIG. 12A. IC package 1200 is similar to
IC package 1000 of FIG. 10 with analogous elements labeled
analogously, except that, in IC package 1200, there are no via
structures analogous to structures 1022 of FIG. 10. Instead, IC
package 1200 has small (conductive paste) step structures 1228 that
provide the electrical connections between the corresponding
(solder) lead structures 1226 and the corresponding (conductive
paste) routing structures 1224.
[0045] Although the invention has been described in the context of
specific embodiments, the invention is not so limited. Those
skilled in the art will understand that the invention also includes
other embodiments having different combinations of some or all of
the following feature options. The IC package may be with or
without conductive bumps on the die bond pads. The routing
structures may be located within grooves in the substrate or on the
surface of the substrate, and either on the die side or the lead
side. The substrate may be with or without vertical via structures
that extend therethrough. The IC package may have die-attach
material applied on the die side of the substrate or within a
recess on the die side of the substrate. Conductive elements may be
with or without solder-anchoring structures, and the conductive
elements may be formed from a single conductive material or by
sequentially applying two or more different materials.
[0046] Although the invention has been described in the context of
IC packages having eight leads for a single die having eight bond
pads, it will be understood that the invention can be implemented
in the context of IC packages having one or more dies having any
suitable numbers of leads and die bond pads.
[0047] It will be further understood that various changes in the
details, materials, and arrangements of the parts which have been
described and illustrated in order to explain embodiments of this
invention may be made by those skilled in the art without departing
from embodiments of the invention encompassed by the following
claims.
[0048] In this specification including any claims, the term "each"
may be used to refer to one or more specified characteristics of a
plurality of previously recited elements or steps. When used with
the open-ended term "comprising," the recitation of the term "each"
does not exclude additional, unrecited elements or steps. Thus, it
will be understood that an apparatus may have additional, unrecited
elements and a method may have additional, unrecited steps, where
the additional, unrecited elements or steps do not have the one or
more specified characteristics.
[0049] It should be understood that the steps of the exemplary
methods set forth herein are not necessarily required to be
performed in the order described, and the order of the steps of
such methods should be understood to be merely exemplary. Likewise,
additional steps may be included in such methods, and certain steps
may be omitted or combined, in methods consistent with various
embodiments of the invention.
[0050] Although the elements in the following method claims, if
any, are recited in a particular sequence with corresponding
labeling, unless the claim recitations otherwise imply a particular
sequence for implementing some or all of those elements, those
elements are not necessarily intended to be limited to being
implemented in that particular sequence.
[0051] Reference herein to "one embodiment" or "an embodiment"
means that a particular feature, structure, or characteristic
described in connection with the embodiment can be included in at
least one embodiment of the invention. The appearances of the
phrase "in one embodiment" in various places in the specification
are not necessarily all referring to the same embodiment, nor are
separate or alternative embodiments necessarily mutually exclusive
of other embodiments. The same applies to the term
"implementation."
* * * * *