U.S. patent application number 14/827683 was filed with the patent office on 2017-02-23 for hermetically-sealed mems device and its fabrication.
The applicant listed for this patent is Texas Instruments Incorporated. Invention is credited to Virgil Cotoco Ararao, John Charles Ehmke.
Application Number | 20170050844 14/827683 |
Document ID | / |
Family ID | 57964226 |
Filed Date | 2017-02-23 |
United States Patent
Application |
20170050844 |
Kind Code |
A1 |
Ehmke; John Charles ; et
al. |
February 23, 2017 |
HERMETICALLY-SEALED MEMS DEVICE AND ITS FABRICATION
Abstract
A hermetic package comprising a substrate (110) having a surface
with a MEMS structure (101) of a first height (101a), the substrate
hermetically sealed to a cap (120) forming a cavity over the MEMS
structure; the cap attached to the substrate surface by a vertical
stack (130) of metal layers adhering to the substrate surface and
to the cap, the stack having a continuous outline surrounding the
MEMS structure while spaced from the MEMS structure by a distance
(140); the stack having a bottom first metal seed film (131a)
adhering to the substrate and a bottom second metal seed film
(131b) adhering to the bottom first seed film, both seed films of a
first width (131c) and a common sidewall (138); further a top first
metal seed film (132a) adhering to the cap and a top second metal
seed film (132b) adhering to the top first seed film, both seed
films with a second width (132c) smaller than the first width and a
common sidewall (139); the bottom and top metal seed films tied to
a metal layer (135) including gold-indium intermetallic compounds,
layer (135) having a second height (133a) greater than the first
height and encasing the seed films and common sidewalls.
Inventors: |
Ehmke; John Charles;
(Garland, TX) ; Ararao; Virgil Cotoco; (McKinney,
TX) |
|
Applicant: |
Name |
City |
State |
Country |
Type |
Texas Instruments Incorporated |
Dallas |
TX |
US |
|
|
Family ID: |
57964226 |
Appl. No.: |
14/827683 |
Filed: |
August 17, 2015 |
Current U.S.
Class: |
1/1 |
Current CPC
Class: |
H01L 2224/05138
20130101; H01L 2224/05166 20130101; H01L 2224/2747 20130101; H01L
2224/29144 20130101; H01L 2224/29144 20130101; H01L 2924/01006
20130101; H01L 2924/01013 20130101; B81C 2201/053 20130101; B81C
2203/0109 20130101; G02B 26/001 20130101; B81B 2203/0315 20130101;
H01L 2224/29109 20130101; H01L 2224/94 20130101; B81C 2203/019
20130101; G02B 6/4208 20130101; H01L 2224/0517 20130101; H01L
2224/83121 20130101; B81C 1/00293 20130101; H01L 2224/29023
20130101; H01L 2224/039 20130101; H01L 24/29 20130101; H01L 24/32
20130101; H01L 2224/27462 20130101; H01L 2924/01074 20130101; H01L
2224/05166 20130101; B81B 7/0038 20130101; H01L 2224/8381 20130101;
G02B 6/4204 20130101; G02B 26/0833 20130101; H01L 2224/05109
20130101; H01L 2224/0517 20130101; H01L 2224/2747 20130101; B81C
2203/0118 20130101; H01L 2224/05163 20130101; B81C 2201/0108
20130101; H01L 2224/29144 20130101; G02B 6/4248 20130101; H01L
2224/039 20130101; H01L 2224/83193 20130101; H01L 2224/0517
20130101; H01L 2924/164 20130101; B81C 2201/0188 20130101; B81C
2201/0198 20130101; H01L 2224/05163 20130101; H01L 2224/05166
20130101; H01L 2224/29011 20130101; B81C 2201/013 20130101; H01L
24/94 20130101; H01L 2224/05163 20130101; H01L 2224/03462 20130101;
H01L 2924/00014 20130101; H01L 2924/00014 20130101; H01L 2924/01004
20130101; H01L 2924/01042 20130101; H01L 2924/01024 20130101; H01L
2224/0345 20130101; H01L 2924/01042 20130101; H01L 2924/01072
20130101; H01L 2924/01074 20130101; H01L 2224/0361 20130101; H01L
2224/03462 20130101; H01L 2924/01072 20130101; H01L 2924/00014
20130101; H01L 2924/01049 20130101; H01L 2924/00014 20130101; H01L
2924/01024 20130101; H01L 2924/00014 20130101; H01L 2924/01074
20130101; H01L 2224/03 20130101; H01L 2924/01042 20130101; H01L
2224/0345 20130101; H01L 2924/00014 20130101; H01L 2924/00014
20130101; H01L 2924/00014 20130101; H01L 2924/00014 20130101; H01L
2224/83 20130101; H01L 2924/01072 20130101; H01L 2224/27462
20130101; H01L 2924/01024 20130101; H01L 2224/0361 20130101; H01L
2924/00014 20130101; H01L 2924/00014 20130101; H01L 2924/01074
20130101; B81C 1/00269 20130101; H01L 2224/279 20130101; H01L
2224/32227 20130101; H01L 24/83 20130101; H01L 2924/01024 20130101;
B81C 2203/035 20130101; H01L 2224/03614 20130101; H01L 2224/05083
20130101; H01L 2224/05109 20130101; H01L 2224/05166 20130101; H01L
2224/27462 20130101; H01L 2924/0102 20130101; H01L 2924/1461
20130101; H01L 24/03 20130101; H01L 2224/03614 20130101; H01L
2224/05123 20130101; H01L 2224/29109 20130101; H01L 2224/32058
20130101; H01L 2224/83121 20130101; H01L 2224/94 20130101; B82Y
30/00 20130101; H01L 24/05 20130101; H01L 24/27 20130101; H01L
2224/0517 20130101; H01L 2224/94 20130101; H01L 2224/05123
20130101; H01L 2224/05138 20130101; H01L 2224/8381 20130101; H01L
2224/83825 20130101; H01L 2924/0002 20130101; H01L 2224/279
20130101; H01L 2224/05562 20130101; H01L 2224/29006 20130101; B81C
1/00285 20130101; H01L 2224/03612 20130101; H01L 2224/05163
20130101; H01L 2224/03612 20130101; H01L 2224/04026 20130101 |
International
Class: |
B81C 1/00 20060101
B81C001/00; B81B 7/00 20060101 B81B007/00 |
Claims
1. A method for fabricating a MEMS device comprising the steps of:
providing a substrate including a MEMS structure having at least a
portion raised to a first height above a substrate surface, the
structure protected by a sacrificial polymer; depositing a first
seed layer including a Group IVA-metal over the substrate surface;
depositing a second seed layer including a metal of high
conductivity over the first seed layer, forming a first vertical
pile; forming a first mask layer over a region of the second seed
layer, the region having a first width and a contour continuously
peripherally surrounding the MEMS structure and laterally spaced
from the MEMS structure; etching the first pile un-covered by the
first mask layer, leaving the first pile of first width un-etched
while creating sidewalls for the first pile, then removing the
first mask layer; plating a first vertical stack of one or more
metal layers over the width and sidewalls of the first pile, the
first stack including a top layer of a first metal having a height
equal to or greater than the first height; removing the sacrificial
polymer; dispensing a getter and passivation material; providing a
cap having a surface with a second pile of seed layers with
sidewalls and a lateral continuous contour similar to but of lesser
or greater lateral width than the contour of the first pile, and
further with a second stack of one or more metal layers over the
width and sidewalls of the second pile, the second stack including
a top layer of a second metal; aligning the cap and the substrate
to bring the top layer of the second metal into contact with the
top layer of the first metal, with a greater lateral spacing of the
first or second metal of the top layer of lesser lateral width than
the lateral spacing of the second or first metal of the top layer
of greater lateral width from the MEMS structure; and applying
thermal energy to the one of the first and second metals having a
lower melting temperature to liquefy and dissolve the one of the
first and second metal into the other of the first and second
metals by forming one or more intermetallic compounds of the first
and second metals.
2. The method of claim 1 wherein the Group IVA-metal is selected
from a group including titanium, zirconium, hafnium, and alloys
thereof with chromium, molybdenum, and tungsten.
3. The method of claim 2 wherein the metal of high conductivity is
selected from a group having high electrical conductivity and low
cost, including copper, aluminum, beryllium, magnesium, silver and
gold.
4. The method of claim 1 wherein the one or more intermetallic
compounds have melting temperatures greater than the melting
temperature of the one of the first and second metals and less than
the melting temperature of the other of the first and second
metals.
5. The method of claim 1 wherein melting temperatures of the other
of the first and second metals and of the one or more intermetallic
compounds are greater than 260.degree. C.
6. The method of claim 5 wherein the melting temperature of the one
or the first and second metals is less than 260.degree. C.
7. The method of claim 1 wherein the one of the first and second
metals is indium and the other of the first and second metals is
gold.
8. The method of claim 1 wherein the steps of depositing comprise
the method of electrolytic plating.
9. The method of claim 1 wherein the step of providing a cap
includes the steps of: providing a cap material element; depositing
a third seed layer including a Group IVA-metal over a surface of
the cap material element; depositing a fourth seed layer including
a metal of high conductivity over the third seed layer, forming a
second vertical pile; covering a region of the second pile with a
second mask layer, the region having the lateral continuous contour
similar to but of lesser or greater lateral width than the contour
of the etched first pile; etching the second pile un-covered by the
second mask layer, leaving the second pile of second width
un-etched while creating sidewalls for the second pile, then
removing the second mask layer; and plating a second vertical stack
of one or more metal layers over the width and sidewalls of the
second pile, the second stack including a top layer of a second
metal having a height equal to or greater than the first
height.
10. A method for fabricating a MEMS device comprising the steps of:
providing a substrate including a MEMS structure having at least a
portion raised to a first height above a substrate surface, the
structure protected by a sacrificial polymer; depositing a first
seed layer including a Group VA-metal over the substrate surface;
depositing a second seed layer including a metal of high
conductivity over the first seed layer; forming a first mask layer
over a region of the second seed layer, the region having a first
width and a contour continuously peripherally surrounding the MEMS
structure and laterally spaced from the MEMS structure; etching the
second seed layer un-covered by the first mask layer, leaving the
second seed layer of first width and the first seed layer un-etched
while creating sidewalls for the first seed layer, then removing
the first mask layer; forming a second mask layer over a region of
the substrate including the first seed layer, the mask layer having
a thickness greater than the first height; patterning the second
mask layer with an opening greater than the first width to expose
an underlying portion of the first seed layer, the opening having a
lateral continuous contour similar to but of greater lateral width
than the contour of the un-etched second seed layer; plating a
first vertical stack of one or more metal layers over the width and
sidewalls of the second seed layer and the first seed layer within
the opening, the first stack including a top layer of a first metal
having a height equal to or greater than the first height, then
removing the second mask layer; etching the first seed layer
un-covered by the first vertical metal stack; removing the
sacrificial polymer; dispensing a getter and passivation material;
providing a cap having a surface with a second pile of seed layers
with sidewalls and a lateral continuous contour similar to but of
lesser or greater lateral width than the contour of the first pile,
and further with a second stack of one or more metal layer over the
width and sidewalls of the second pile, the second stack including
a top layer of a second metal; aligning the cap and the substrate
to bring the top layer of the second metal into contact with the
top layer of the first metal, with a greater lateral spacing of the
first or second metal of the top layer of lesser lateral width than
the lateral spacing of the second or first metal of the top layer
of greater lateral width from the MEMS structure; and applying
thermal energy to the one of the first and second metals having a
lower melting temperature to liquefy and dissolve the one of the
first and second metal into the other of the first and second
metals by forming one or more intermetallic compounds of the first
and second metals.
11. The method of claim 10 wherein the Group VA-metal is selected
from a group including vanadium, niobium, tantalum, and alloys and
compounds thereof.
12. The method of claim 10 wherein the metal of high conductivity
is selected from a group having high electrical conductivity and
low cost, including copper, aluminum, beryllium, magnesium, silver
and gold.
13. The method of claim 10 wherein the one or more intermetallic
compounds have melting temperatures greater than the melting
temperature of the one of the first and second metals and less than
the melting temperature of the other of the first and second
metals.
14. The method of claim 10 wherein melting temperatures of the
other of the first and second metals and of the one or more
intermetallic compounds are greater than 260.degree. C.
15. The method of claim 14 wherein the melting temperature of the
one or the first and second metals is less than 260.degree. C.
16. The method of claim 10 wherein the one of the first and second
metals is indium and the other of the first and second metals is
gold.
17. The method of claim 10 wherein the steps of depositing comprise
the method of electrolytic plating.
18. The method of claim 10 wherein the step of providing a cap
includes the steps of: providing a cap material element; depositing
a third seed layer including a Group VA-metal over a surface of the
cap material element; depositing a fourth seed layer including a
metal of high conductivity over the third seed layer; forming a
second vertical pile; covering a region of the second pile with a
second mask layer, the region having the lateral continuous contour
similar to but of lesser or greater lateral width than the contour
of the etched first pile; etching the second pile un-covered by the
second mask layer, leaving the second pile of second width
un-etched while creating sidewalls for the second pile, then
removing the second mask layer; and plating a second vertical stack
of one or more metal layers over the width and sidewalls of the
second pile, the second stack including a top layer of a second
metal having a height equal to or greater than the first
height.
19. A hermetic package of a microelectromechanical system (MEMS)
structure comprising: a substrate having a surface with a MEMS
structure of a first height, the substrate hermetically sealed to a
cap forming a cavity over the MEMS structure; the cap attached to
the substrate surface by a vertical stack of metal layers adhering
to the substrate surface and to the cap, the stack having a
continuous outline surrounding the MEMS structure while spaced from
the MEMS structure by a distance; and the stack having a bottom
first metal seed film adhering to the substrate and a bottom second
metal seed film adhering to the bottom first seed film, both seed
films of a first width and a first common sidewall, and further a
top first metal seed film adhering to the cap and a top second
metal seed film adhering to the top first seed film, both seed
films with a second width smaller than the first width and a second
common sidewall, the bottom and top metal seed films tied to a
metal layer including gold-indium intermetallic compounds, the
metal layer encasing the seed films and the first and second common
sidewalls and having a second height greater than the first
height.
20. The package of claim 19 wherein the bottom and top first metal
seed films are selected from the IVA Group of the Periodic Table of
Elements including titanium, zirconium, hafnium and alloys thereof
with chromium, molybdenum, and tungsten.
21. The package of claim 19 wherein the bottom and top second metal
seed films are selected from a group including copper, aluminum,
beryllium, magnesium, and alloys thereof.
22. A hermetic package of a microelectromechanical system (MEMS)
structure comprising: a substrate having a surface with a MEMS
structure of a first height, the substrate hermetically sealed to a
cap forming a cavity over the MEMS structure; the cap attached to
the substrate surface by a vertical stack of metal layers adhering
to the substrate surface and to the cap, the stack having a
continuous outline surrounding the MEMS structure while spaced from
the MEMS structure by a distance; and the stack having a bottom
first metal seed film adhering to the substrate and a bottom second
metal seed film adhering to the bottom first seed film, the first
bottom seed film having a first width and the second bottom seed
film having a second width greater than the first width, and
further a top first metal seed film adhering to the cap and a top
second metal seed film adhering to the top first seed film, both
the top first and top second seed films with a third width smaller
than the first width and a common sidewall, the bottom and top
metal seed films tied to a metal layer including gold-indium
intermetallic compounds, the metal layer having a width equal to
the second width and a second height greater than the first height,
the metal layer encasing the first bottom seed film and the first
and second top seed films and common sidewalls.
23. The package of claim 22 wherein the bottom and top first metal
seed films are selected from the VA Group of the Periodic Table of
Elements including vanadium, niobium, tantalum and alloys
thereof.
24. The package of claim 22 wherein the bottom and top second metal
seed films are selected from a group including copper, aluminum,
beryllium, magnesium, and alloys thereof.
Description
FIELD OF THE INVENTION
[0001] The present invention relates to semiconductor devices and
processes, and more specifically to the structure and fabrication
of hermetically sealed microelectromechanical system (MEMS)
devices.
DESCRIPTION OF RELATED ART
[0002] The wide variety of products collectively called
Micro-Electro-Mechanical devices (MEMS) are small, low weight
devices on the micrometer to millimeter scale, which may have
mechanically moving parts and often movable electrical power
supplies and controls, or they may have parts sensitive to thermal,
acoustic, or optical energy. MEMS have been developed to sense
mechanical, thermal, chemical, radiant, magnetic, and biological
quantities and inputs, and produce signals as outputs. Because of
the moving and sensitive parts, MEMS have a need for physical and
atmospheric protection. Consequently, MEMS are placed on or in a
substrate and have to be surrounded by a housing or package, which
has to shield the MEMS against ambient and electrical disturbances,
and against stress.
[0003] A typical MEMS device integrates mechanical elements,
sensors, actuators, and electronics on a common substrate. The
manufacturing approach of a MEMS aims at using batch fabrication
techniques similar to those used for microelectronics devices. MEMS
can thus benefit from mass production and minimized material
consumption to lower the manufacturing cost, while simultaneously
realizing the benefits well-controlled integrated circuit
processing technology.
[0004] Example MEMS devices include devices without moving parts
and devices with moving parts. Examples of MEMS devices without
moving parts are ink jet print heads mechanical sensors, strain
gauges, pressure sensors with microphone membranes, and inertial
sensors such as accelerometers coupled with the integrated
electronic circuit of the chip. Among the MEMS devices with moving
parts but without rubbing or impacting surfaces, are gyros, comb
devices, resonators and filters. In other classes, the moving parts
may impact surfaces, such as in digital mirror devices (DMDs),
relays, valves, and pumps; or the moving parts may impact and rub
surfaces, such as in optical switches, shutters, scanners, locks,
discriminators, and variable electrostatic actuators (VEAs). In
MEMS devices with moving parts, the mechanically moving parts are
fabricated together with the sensors and actuators in the process
flow of the electronic integrated circuit (IC) on a semiconductor
chip. The mechanically moving parts may be produced by an
undercutting etch or removal of a sacrificial layer at some step
during the IC fabrication. Examples of specific bulk micromachining
processes employed in MEMS sensor production to create the movable
elements and the cavities for their movements are anisotropic wet
etching and deep reactive ion etching.
[0005] While the fabrication of these MEMS devices can benefit from
wafer-level processes, their packages do not have to be fully
hermetic, i.e. impermeable to water molecules. Consequently, they
may use sealants made of polymeric compounds typically used in
adhesive bonding. On the other hand, DMDs require substantially
fully hermetic packages, since they may include torsion hinges,
cantilever hinges, and flexure hinges. Each movable mirror element
of all three types of hinge DMD includes a relatively thick metal
reflector supported in a normal, undeflected position by an
integral, relatively thin metal hinge. In the normal position, the
reflector is spaced from a substrate-supported, underlying control
electrode, which may have a voltage selectively impressed thereon
by an addressing circuit. A suitable voltage applied to the
electrode can electrostatically attract the reflector to move or
deflect it from its normal position toward the control electrode
and the substrate. Such movement or deflection of the reflector
causes deformation of its supporting hinge which stores potential
energy that mechanically biases the reflector for movement back to
its normal position when the attracting voltage is removed. The
deformation of a cantilever hinge comprises bending about an axis
normal to a hinge axis. The deformation of a torsion hinge
comprises deformation by twisting about an axis parallel to the
hinge axis. The deformation of a flexure hinge, which is a
relatively long cantilever hinge connected to the reflector by a
relatively short torsion hinge, comprises both types of
deformation, permitting the reflector to move in piston-like
fashion.
[0006] An example DMD (digital mirror device) MEMS is a spatial
light modulator such as a DLP.TM. DMD device available from Texas
Instruments. A typical DMD includes an array of individually
addressable light modulating pixel element micromirrors, the
reflectors of each of which are selectively positioned to reflect
or not to reflect light to a desired site. In order to avoid an
accidental engagement of a reflector and its control electrode, a
landing electrode may be added for each reflector. It has been
found, though, that there is a risk that a deflected reflector may
stick to or adhere to its associated landing electrode. It is
postulated that such stiction (static friction that needs to be
overcome to enable relative movement) effect may be caused by
intermolecular attraction between the reflector and the landing
electrode or by high surface energy substances adsorbed on the
surface of the landing electrode and/or on the portion of the
reflector which contacts the landing electrode. Substances which
may impart such high surface energy to the reflector-landing
electrode interface include water vapor or other ambient gases
(e.g., carbon monoxide, carbon dioxide, oxygen, nitrogen) and gases
and organic components resulting from or left behind following
production of the DMD.
[0007] The problem of stiction has been addressed by applying
selected numbers, durations, shapes and magnitudes of voltage
pulses to the control electrode, or by passivating or lubricating
the portion of the landing electrode engaged by the deformed
reflector, and/or the portion of the deformed reflector which
engages the landing electrode. Passivation is effected by lowering
the surface energy of the landing electrode and/or the reflector
through chemically vapor-depositing on the engageable surfaces a
monolayer of a long-chain aliphatic halogenated polar compound,
such as perfluoroalkyl acid. An effective method of passivation is
to enclose a source of passivation, such as a predetermined
quantity to time-released passivant material, in a closed cavity
with the micromirrors at time of device manufacture.
[0008] Conventional hermetic packaging of MEMS devices usually
involves a packaging process that departs from the processes
normally used for non-MEMS device packaging. MEMS hermetic
packaging is expensive not only because the package often includes
a ceramic material, or a metallic or glass lid, but also because
the package must be configured to avoid contact with moving and
other sensitive parts of the MEMS device and to further allow a
controlled or reduced atmosphere inside the package. The high
package cost is, however, in conflict with market requirements for
many applications of MEMS devices, which put a premium at low
device cost and, therefore, low package cost.
[0009] Further, the conventional fabrication of hermetic MEMS
packages also encounters many technical challenges, such as those
caused by potentially high temperatures in connection with welding
of a hermetic lid to the package base. As an example, a recently
proposed package with a sealing process using a glass core involves
temperatures considerably above 450.degree. C., typically between
525 and 625.degree. C. dependent on the sealing glass selected.
These temperature ranges are a risk for the reliability of silicon
integrated circuits and for proper functioning of many MEMS device
components, and inhibit passivation and lubrication methods.
Similar and sometimes even higher temperatures are involved, when
packages use techniques such as anodic bonding and glass frit
bonding.
[0010] It would be advantageous to have a more fully hermetically
packaged MEMS device which could target low cost industrial,
automotive and consumer applications not currently reached by
higher cost packaged devices.
[0011] It would be advantageous to have a more fully hermetically
sealed MEMS device fabrication process flow in which both the
front-end process flow as well as the packaging process flow would
take advantage of semiconductor batch processing techniques applied
in the fabrication of non-MEMS integrated circuit devices and would
take advantage of installed automated machines.
[0012] It would be advantageous to have a more fully hermetically
sealed MEMS device including appropriate passivating and
lubricating agents, or controlled gaseous pressure in internal
cavities.
SUMMARY OF THE INVENTION
[0013] A hermetically sealed MEMS device with sidewall
encapsulation of seed layers, and a method for fabricating the
package of such MEMS device are described.
[0014] In an example method, a substrate is provided that includes
a MEMS structure having at least a portion raised to a height above
a substrate surface. A first seed layer including a metal of the
IVA Group of the Periodic Table of Elements is deposited over the
substrate surface; a second seed layer including a metal of high
conductivity is deposited over the first seed layer, thus forming a
first vertical pile. A first mask layer is formed over a region of
the second seed layer; the region has a width and a contour
continuously peripherally surrounding the MEMS structure and spaced
laterally from the MEMS structure. The first pile is etched where
it is un-covered by the first mask layer, thereby leaving the first
pile of first width un-etched while creating sidewalls for the
first pile; thereafter, the first mask layer is removed.
[0015] A second mask layer is formed over a region of the substrate
including the first pile, the mask layer having a thickness greater
than the first height. The second mask layer is patterned with an
opening greater than the first width to expose an underlying
portion of the substrate including the un-etched first pile, the
opening having a lateral continuous contour similar to but of
greater lateral width than the contour of the un-etched first pile.
A first vertical stack of one or more metal layers is plated over
the width and sidewalls of the first pile, the first stack
including a top layer of a first metal with a height equal to or
greater than the first height. Thereafter, the sacrificial polymer
is removed and a getter and passivation material is dispensed.
[0016] A cap material element is also provided, which has a surface
with a second pile of seed layers with sidewalls and a lateral
continuous contour similar to but of lesser or greater lateral
width than the contour of the first pile, and further with a second
stack of one or more metal layers over the width and sidewalls of
the second pile, the second stack including a top layer of a second
metal.
[0017] The cap and the substrate are than aligned to bring the top
layer of the second metal into contact with the top layer of the
first metal, with a greater lateral spacing of the first or second
metal of the top layer of lesser lateral width than the lateral
spacing of the second or first metal of the top layer of greater
lateral width from the MEMS structure. Thereafter, thermal energy
is applied to the one of the first and second metals having a lower
melting temperature to liquefy and dissolve the one of the first
and second metal into the other of the first and second metals by
forming one or more intermetallic compounds of the first and second
metals.
[0018] The metal of the IVA Group is selected from a group
including titanium, zirconium, hafnium, and alloys thereof with
chromium, molybdenum, and tungsten. Using a somewhat modified
methodology, the metal may be selected from the VA Group, including
vanadium, niobium, and tantalum.
BRIEF DESCRIPTION OF THE DRAWINGS
[0019] FIG. 1 shows a cross section of a portion of a MEMS device
with a hermetically sealed cap forming a cavity over the MEMS, the
cavity including a lubricant, the cap attached to the substrate by
a vertical stack of metal layers including gold-indium
intermetallic compounds.
[0020] FIGS. 2 to 6 illustrate certain wafer-level process steps to
fabricate metal layers surrounding MEMS structures, the metal
layers suitable for hermetic sealing of packages and encapsulating
lubricant-degrading compounds.
[0021] FIG. 2 depicts the step of protecting surface MEMS
structures on a substrate with sacrificial polymer, after all
surface MEMS processing steps have been completed.
[0022] FIG. 3A shows the steps of patterning and etching of the
package metal layout.
[0023] FIG. 3B illustrates the steps of depositing seed metal
layers including a layer of a refractory metal and a layer of
high-conductivity metal.
[0024] FIG. 4A depicts the step of patterning the seed metal layers
by covering the region-to-be-plated with a first mask layer.
[0025] FIG. 4B shows the step of etching the seed metal layers
un-covered by the first mask layer, creating sidewalls of the
layers; thereafter, the first mask layer is removed.
[0026] FIG. 5 illustrates the step of plating a first vertical
stack of one or more metal layers including a top layer of a first
metal, covering the seed metal sidewalls.
[0027] FIG. 6 depicts the step of removing the patterned polymeric
material and the MEMS structure protection, and dispensing the
getter and passivation material.
[0028] FIGS. 7 to 10 show certain wafer-level process steps for
fabricating caps with metallization to complete the sealing of
hermetic MEMS packages.
[0029] FIG. 7 indicates the step of depositing seed metal layers
including a layer of a refractory metal and a layer of a high
conductivity metal on a wafer-size cap material.
[0030] FIG. 8 depicts the step of patterning the seed metal layers
by covering the region-to-be-plated with a second mask layer.
[0031] FIG. 9 shows the step of etching the seed metal layers
un-covered by the second mask layer, creating sidewalls of the
layers; thereafter, the second mask is removed.
[0032] FIG. 10 illustrates the step of plating a second vertical
stack of one or more metal layers including a top layer of a second
metal, covering the seed metal sidewalls.
[0033] FIG. 11 illustrates the package assembly steps by aligning
the cap stack of metals with the substrate stack of metals to
contact indium and gold layers.
[0034] FIG. 12 depicts a cross section of a portion of another MEMS
device with a hermetically sealed cap forming a cavity over the
MEMS, the cavity including a lubricant, the cap attached to the
substrate by a vertical stack of metal layers including gold-indium
intermetallic compounds.
DETAILED DESCRIPTION OF EXAMPLE EMBODIMENTS
[0035] Life test and stress test data indicated that the
lubricating and passivating characteristics of compounds deposited
in hermetic packages of MEMS devices with moving parts may
deteriorate over time. Applicants found in detailed investigations
that the chief culprit for the compound degradation may be exposed
surfaces of copper layers needed in high-conductivity seed layers
and low-resistance traces for plating uniformity.
[0036] Applicants solved the problem of lubricant degradation when
they discovered a methodology to deposit the bond metals so that
they extend not only over the width but also over the sidewalls of
patterned seed metal piles, thereby encapsulating the copper of the
seed metal layers. The methodology is based on using photoresist
invers to existing practice, namely covering the region intended
for plating rather than exposing the region.
[0037] The exemplary embodiment 100 of FIG. 1 illustrates a portion
of a hermetic package for a micro-electro-mechanical system (MEMS)
structure 101. The package portion shown in FIG. 1 includes a
substrate 110 and an exemplary MEMS structure, shown as a surface
MEMS carried by substrate 110. At least a portion of surface MEMS
101 has a first height 101a over the substrate surface. As an
example, MEMS structure 101 may be an array of individually
addressable micromirrors of a digital mirror device (DMD) such as a
Texas Instruments DLP.TM. DMD special light modulator. In this
case, first height 101a may for example be in the range from 0.5
.mu.m to 1.5 .mu.m. In other MEMS devices, first height 101a may be
smaller or greater.
[0038] Substrate 110 may, for example, be a chip or chip area like
that of an integrated circuit chip comprising semiconductor
material such as silicon, silicon germanium, or gallium arsenide.
Semiconductor chips are impermeable to water molecules and thus
hermetic. The substrate may include circuit components of an
integrated circuit (IC) protected by an overcoat 111. In the
package portion illustrated in FIG. 1, the protective overcoat 111
is depicted as covering the whole substrate surface so that
overcoat 111 can be considered the effective substrate surface. In
addition, the package of device 100 includes a cap or cover 120,
which is configured to provide an enclosed cavity for housing MEMS
structure 101. In the example of DMDs, cap 120 is a flat plate or
other structure providing transparency to enable external light of
desired wavelengths to reach and be selectively modulated by
position settable reflecting surfaces of structure 101. In other
MEMS devices, cap 120 may be opaque, or may have a dome-shaped
configuration. In any case, cap 120 is formed to be impermeable to
water molecules and thus hermetic.
[0039] As illustrated on FIG. 1, cap 120 is attached to substrate
110 by a vertical stack 130 of metal layers. Stack 130 has a
continuous contour that peripherally laterally surrounds MEMS
structure 101 at a spacing distance 140 from MEMS structure 101. In
example DMDs, distance 140 may be between 50 .mu.m and 200 .mu.m.
The adhesion of stack 130 to substrate 110 may be enabled by 131a
and 131b, and the adhesion of stack 130 to cap 120 may be enabled
by metallic seed films 132a and 132b. In an example implementation,
seed films 131a and 132a may have a thickness of 100 nm and include
a refractory metal of the IV A Group of the Periodic Table of
Elements, such as titanium, and seed films 131b and 132b may have a
thickness of 200 nm and include a metal of high electrical
conductivity such as copper or aluminum. Seed films 131a and 131b
have a common sidewall 138, and seed films 132a and 132b have a
common sidewall 139. In another example implementation (see FIG.
12), the seed films of refractory metal include a metal of the V A
Group of the Periodic Table of Elements, such as tantalum. In this
case, the sidewall of the seed film of high conductivity metal is
set back from the sidewall of the seed film of refractory metal.
The adhesion of stack 130 to substrate 110 and to cap 120 is made
impermeable to water molecules and thus hermetic.
[0040] As illustrated in FIG. 1, seed films 131a and 131b have a
first width 131c. In example DMDs, first width 131c may be between
about 100 .mu.m and 150 .mu.m. Seed films 132a and 132b have a
second width 132c smaller than first width 131c. In example DMDs,
second width 132c may be between about 50 .mu.m and 80 .mu.m.
[0041] Vertical stack 130 of FIG. 1 includes a plurality of metal
layers of various thicknesses and widths. The portion of stack 130
near substrate 110 joins seed films 131a and 131b, wraps around
their common sidewall 137, fully encapsulating sidewall 137, and
thus has a width 130a greater than seed film width 131c. The
portion of stack 130 near cap 120 joins seed films 132a and 132b,
wraps around their common sidewall 138, fully encapsulating
sidewall 138, and thus has a width 130b larger than seed film width
132c, but tapered or stepped upwardly and inwardly from width 130a.
As illustrated in embodiment 100 of FIG. 1, metal stack 130
includes a plurality of layers 135, 136, and 137. In other MEMS
device implementations, layer 137 or layer 136, or both, may be
omitted, or an additional one or more metal layers may be
added.
[0042] In an example implementation, bottom layer 137 is joined to
seed film 131, is made of copper, and has a thickness of about 2
.mu.m. Intermediate layer 136 is joined to layer 137, is made of
nickel which acts as a barrier layer against metal diffusion, and
has a thickness of about 1 .mu.m. Layer 136 fully encapsulates
layer 137; consequently, when layer 136 is made of nickel,
out-diffusion of underlying copper is inhibited. Top metal layer
135 has its bottom joined to intermediate layer 136, its top joined
to seed film 132b, and a width that varies upwardly and inwardly
from width 130a to width 130b. A lower portion of layer 135 of
generally uniform width 130a has a thickness 133a of between about
5 .mu.m and 10 .mu.m, and the upper portion of layer 135 of tapered
or stepped width has a thickness 134a of between about 2 .mu.m and
4 .mu.m. For some MEMS devices, enhanced adhesion can be achieved
and any out-diffusion of copper from seed film 132b can be
inhibited by the addition of a nickel layer of about 1 .mu.m
thickness between the upper portion of thickness 134a and seed film
132b.
[0043] For the example MEMS device illustrated in FIG. 1, metal
layer 135 includes gold-indium intermetallic compounds of various
compositions, for instance AuIn.sub.2 with a melting temperature of
about 540.degree. C. and AuIn with a melting temperature of about
509.degree. C. In addition, metal layer 135 may include metallic
gold not consumed by intermetallic compounds. As explained below,
with gold provided with a wider bond line than indium during
fabrication and in an amount considerably more plentiful than the
amount of indium, the increase of temperature allows the gold
surface to react with any excess indium, capturing it as
intermetallic compounds.
[0044] An example embodiment of a wafer-level process flow for the
fabrication of low-temperature hermetically sealed MEMS structure
devices is illustrated with reference to FIGS. 2 to 11.
[0045] FIG. 2 shows an un-singulated chip area of a substrate 110
such as a chip area of an integrated circuit of a semiconductor
wafer 110 at a process stage where the initial processing of MEMS
structures 101 has been completed. The chip area of wafer 110 may
include circuitry for each chip, such as integrated circuits
manufactured by CMOS technology. The included circuitry is
electrically connected to the respective MEMS structures. Wafer 110
covered by a layer 111 of protective overcoat such as silicon
nitride and silicon oxide. In the illustrated embodiment, movable
portions of the MEMS structures 101 are shown above the wafer
surface, i.e., above the overcoat layer 111, by a height 101a. The
height 101a of the MEMS structures above the overcoat is herein
referred to as first height 101a. For the example of digital mirror
devices (DMD), first height 101a may be in a range of about 0.5
.mu.m to 1.5 .mu.m. The MEMS structures (e.g., movable mirrors of a
DMD) are advantageously supported by a protective polymeric
material 201 such as a layer of photoresist, which can be
sacrificed and removed at a later stage of the process flow. It is
a technical advantage that the steps of forming the packaging,
bonding, and sealing features begin only after the surface MEMS
processing is complete so that integration issues caused by
structure topology may be prevented.
[0046] The layout of the package features is next defined and the
substrate surface is covered with a patterned metallic seed film
for anchoring the package sealing structures.
[0047] In order to pattern protective layer 201, a photoresist
layer 301 (see FIG. 3A) is deposited on protective layer 201
through a mask or, alternatively, sealed MEMS structures, as
illustrated in FIGS. 2 to 11 by certain process steps. FIG. 2 shows
a portion of a substrate 110 such as a semiconductor wafer at a
process stage where the processing of MEMS structures 101 has been
completed. The semiconductor wafer 110 may include circuitry for
each chip, such as integrated circuits manufactured by CMOS
technology; the circuitry is electrically connected to the
respective MEMS structures. It is advantageous to have wafer 110
covered by a layer 111 of protective overcoat such as silicon
nitride and silicon carbide. The MEMS structures 101 are shown as
surface MEMS, i.e. above overcoat layer 111; the height 101a of the
MEMS structures above the overcoat is herein referred to as first
height 101a. For the example of digital mirror devices (DMD), first
height 101a may be between about 0.5 .mu.m and 1.5 .mu.m. The MEMS
structures are preferably embedded in a protective polymeric
material 201 such as photoresist, which can be sacrificed and
removed at a later stage of the process flow. It is a technical
advantage that the steps of forming the packaging, bonding, and
sealing features begin only after the surface MEMS processing is
complete so that integration issues caused by structure topology
can be prevented.
[0048] The next processes steps involve defining the layout of the
package features and to cover the substrate surface with patterned
metallic seed films for anchoring the package seal structures. In
order to pattern protective layer 201, a photoresist layer 301 (see
FIG. 3A) is deposited on protective layer 201 through a mask or,
alternatively, deposited as a layer and then photoetched.
Protective layer 201 is selectively etched to create an opening of
lateral width 310, with a portion of overcoat 111 exposed in the
opening of width 310. Opening of width 310 follows a continuous
contour laterally peripherally surrounding the MEMS structure 101
and spaced from the MEMS structure by a distance 320.
[0049] In the next process step, illustrated in FIG. 3B, metallic
seed films 131a and 131b are blanket deposited over the patterned
photoresist layer 301 and within the opening of width 310. Metallic
seed film 131a is of a material that has strong adhesion to
overcoat 111. In one implementation, film 131a is selected from a
group including metals of the IV A Group of the Periodic Table of
Elements, comprising titanium, zirconium, hafnium, and alloys
thereof with chromium, molybdenum, and tungsten. Preferably, film
131a has a thickness of about 100 nm. For another implementation
using a metal of the VA Group, see below. Seed film 131b uses a
metal of high electrical conductivity and preferably low cost, such
as copper and aluminum, also beryllium, magnesium, silver, and
gold. Preferably, film 131b has a thickness of about 200 nm. Seed
films 131a and 131b form a vertical pile of layers, referred to
herein as first vertical pile.
[0050] As illustrated in FIG. 4A, the second seed layer 131b of the
vertical pile of seed layers is next covered with a patterned layer
(referred to as the first mask layer) 401 over a region with first
width 410 and a contour continuously peripherally surrounding the
MEMS structures 101 and laterally spaced by a distance 420 from the
MEMS structure. Distance 420 is greater than distance 320. First
mask 401 is positioned substantially symmetrical from the center of
opening of width 310 with about equal mask portions to either side
of the center. (This center is indicated by phantom line 311 in
FIG. 4A). Due to this symmetry, the distance 402 between a mask
side 401b and the nearest opening side 310b is about the same along
the contour of mask 401. Mask 401 has the same general
two-dimensional continuous contour configuration as the opening of
width 310 previously formed in protective layer 301 (see FIG. 3A)
and is spaced by distance 420 from the MEMS structure 101. Distance
402 is selected so that it can accommodate the thicknesses of the
metal layers plated as a stack in the following deposition steps
(see FIG. 5). Width 410 may, for example, be between about 100
.mu.m and 150 .mu.m. The material for first mask 401 may, for
instance, be a photoresist polymer. The height 401a of mask 401 is
sufficient to withstand the following etching process step. The
remaining seed layers not covered by first mask 401 are
exposed.
[0051] FIG. 4B depicts the result of etching the first pile of seed
layers in regions un-covered by the first mask layer 401 of width
410. The etching step involves a chemical or plasma etching
technique and leaves the first pile un-etched with a width 131c,
which is substantially the same as first width 410 of the mask, and
creates common sidewalls 138, which are substantially the same for
layers 131a and 131b. After the etching process, first mask layer
401 is removed.
[0052] FIG. 5 illustrates the formation of a vertical stack of
metal layers over the seed film 131b and sidewall 138. The layers
are deposited sequentially; the preferred deposition process is
electrolytic plating since it is able to produce uniform layers in
short periods of time. In one example, a bottom layer 137 of, for
example, copper of about 2 .mu.m thickness is formed that adheres
to metallic seed film 131b, sidewalls 138, and overcoat 111 exposed
on the bottom of the opening of width 310. Next, a barrier layer
136 of, for example, nickel of about 1 .mu.m thickness is formed
over the layer 137; it also adheres to overcoat 111. Barrier layer
137 prevents the out-diffusion of copper atoms. And then, a top
layer 501 of a first metal of, for example gold of a thickness
between about 5 .mu.m and 10 .mu.m is formed over the barrier layer
136. The first metal also adheres to overcoat 111 and has a height
501a equal to or greater than the first height 101a. The sum of the
thicknesses of layers 137, 136, and 501 provides a stack height 511
and stack width 130a. In other MEMS device implementations, one or
both of layers 136, 137 may be omitted.
[0053] In the next process steps, indicated in FIG. 6, photoresist
layer 301 and sacrificial protective polymer layer 201 are removed
by a photoresist removal process such as plasma etching, releasing
the MEMS structures 101 and freeing them for movement. As FIG. 6
shows, the result of these processes is a structure 1110 that
comprises the substrate 110 with MEMS structures 101 of height 101a
over the substrate upper surface and with a vertical stack of metal
layers 137, 136 and 501 of width 130a and height 511 laterally
continuously surrounding and spaced by a distance 140 from the MEMS
structures 101. Metal layers 137, 136, and 501 cover sidewalls 138
of seed layers 131a and 131b and are attached to overcoat 111.
Furthermore, when required, a getter, lubrication and passivation
material 601 is dispensed.
[0054] FIGS. 7 to 10 depict steps in the wafer-level fabrication of
water-impermeable caps suitable for joinder to the wafer-level
structure 1110 for hermetically sealing the MEMS structures formed
in the chip areas of the substrate.
[0055] FIG. 7 indicates the step of providing a flat cap 120 with a
surface with metallic seed films 132a and 132b suitable for DMD
devices. The illustrated cap 120 may be made of a glass transparent
to visible light. Metallic seed film 132a is of a material that has
strong adhesion to the material of cap 120. In one implementation,
film 132a is selected from a group including metals of the IV A
Group of the Periodic Table of Elements, comprising titanium,
zirconium, hafnium, and alloys thereof with chromium, molybdenum,
and tungsten. Preferably, film 132a has a thickness of about 100
nm. Seed film 132b uses a metal of high electrical conductivity and
preferably low cost, such as copper and aluminum, also beryllium,
magnesium, silver, and gold. Preferably, film 132b has a thickness
of about 200 nm. Second seed films 132a and 132b represent a second
vertical pile of seed layers. Cap 120 is formed on a wafer scale
and thus compatible with a wafer-scale assembly for the MEMS
structures. Although a flat cap 120 is used for illustrative
purposes, it will be appreciated that the configuration of the cap
structure may be a vaulted dome or other configuration different
than a flat cap, with the specific configuration determined based
on the type and configuration of MEMS structure involved and also
in consideration of other particular needs and individual
preferences.
[0056] As illustrated in FIG. 8, the second seed layer 132b of the
second vertical pile of seed layers is next covered with a layer of
a polymeric material such as a photoresist layer 801 (referred to
as the second mask layer). Photoresist layer 801 is patterned to
provide a width 132c less than width 410; phantom line 811
indicates the center of second mask layer 801. Width 132c has the
same general two-dimensional continuous contour configuration as
the first mask layer 401 previously described, but of lesser or
greater lateral width than the contour of the etched first pile (of
seed layers 131a and 131b). Width 132c is positioned so that width
132c may be brought into alignment generally centrally of the width
410 of the stack of layers 131a and 131b in later processing. By
this alignment, center line 811 is brought into alignment with
center line 311 of FIG. 4A. As FIG. 8 shows, the seed layers 132a
and 132b outside second mask layer 801 remain exposed and will be
removed by etching in the next process step.
[0057] FIG. 9 depicts the result of etching the second pile of seed
layers in regions un-covered by the second mask layer 801 of width
132c. The etching step involves a chemical or plasma etching
technique and leaves the second pile un-etched with a width 132 and
creates common sidewalls 139, which are substantially the same for
layers 132a and 132b. After the etching process, second mask layer
801 is removed.
[0058] The process step shown in FIG. 10 comprises the deposition
of a second vertical stack 1034 of one or more metal layers over
the width 132c and the sidewalls 139 of the second pile of seed
layers. The second stack 1034 includes a top layer of a second
metal, for example, indium, suitable to form intermetallics with
the metal layer 501. In example DMD devices, layer 1034 may be
formed to a height 1034a of between about 2 and 4 .mu.m.
Advantageously, a barrier layer of, for example, nickel to a
thickness of about 1 .mu.m may be deposited on the width and
sidewall of metallic seed films 132a before the indium metal 1034
is deposited. The barrier metal as well as the second metal adhere
to the material of cap 120. The resulting width of metal stack 1034
is 130b. The preferred deposition technique is electrolytic
plating.
[0059] In some implementations, metal layer 1034 may be a composite
metal layer comprising a plurality of successively formed metal
layers, such as a bottom layer of about 200 nm thickness of
titanium deposited over the metallic seed layer 132b, followed by
an intermediate layer of indium deposited over the titanium, and
then a top layer of gold of about 100 nm thickness deposited over
the indium intermediate layer.
[0060] The resulting wafer scale cap structure, illustrated in FIG.
10 and designated 1010, comprises the second metal layer 1034
(viz., indium) of width 130b and height 1034a, adhering to the
metallic seed film 132b and to the surface of flat cap material
120. As mentioned, indium layer 1034 and remaining seed films 132a
and 132b are configured to match and fall within the outline of
gold layer 501 formed on substrate 110 as structure 1110. At this
stage, the cap structure 1010 is ready to be used for the
wafer-scale assembly of hermetic packages for the MEMS structures
on substrate 110 of structure 1110.
[0061] As mentioned, for some MEMS devices, such as DMDs, chemical
gettering substances, lubricants, corrosion inhibitants and/or
other materials (generally designated 601 in FIG. 6) may be added
prior to or contemporaneously with sealingly joining the cap and
substrate structures 1010 and 1110.
[0062] FIG. 11 illustrates the package assembly step. Cap 1010 is
aligned with substrate 1110 so that indium layer 1034 is facing
gold layer 501. In FIG. 11, indium layer 1034 is approximately
centered above gold layer 501 as indicated by indium center line
811 substantially matched with gold centerline 311. This alignment
step leaves a lateral distance 130c from the inside perimeter edge
of the laterally continuous contour of indium layer 1034 to the
corresponding inside perimeter edge of the similar laterally
continuous contour of gold layer 501. Cap 1010 is then lowered
(indicated by arrow 1111) onto substrate 1110 in order to bring
indium layer 1034 into contact with gold layer 501, resulting in an
asymmetrical bond line width, wherein the indium width at the bond
line is narrower (in typical embodiments, significantly narrower)
than the gold width at the bond line.
[0063] Without delay and with the indium layer and gold layer in
contact, thermal energy is applied in order to raise the
temperature until the indium metal is liquefied at about
156.degree. C. It is preferred to keep the temperature between
about 156 and 200.degree. C., since this temperature range is low
compared to typical processing temperatures of silicon components
and MEMS structures. Since the amount of indium is small relative
to the amount of gold, after a short period of time the indium
metal is dissolved into the gold layer by forming gold-indium
intermetallic compounds (the interaction is often referred to as a
transient liquid phase process). Among the formed compounds are the
indium-rich compound AuIn.sub.2 and the compound AuIn. The
oversized gold surface (relative to the indium surface in contact
with the gold surface) acts to capture excess liquid indium to form
intermetallic compounds 601 before liquid indium can enter sidewise
into the MEMS structure headspace. An occasional residual indium
metal squeezed sidewise is neutralized by the distance 140 of the
gold perimeter to the MEMS structures 101. As indicated in FIG. 1,
the resulting layer of intermetallics and residual gold is
designated 135. The insertion of barrier layer 136 of nickel
effectively blocks an interaction of gold with copper of layer 137
within the stated low temperature range. However, even in the
absence of the nickel layer, gold will interact much more slowly
with copper than with indium. Since nickel layer 136 wraps round
the sidewalls of copper layer 137 and is in touch with protective
layer 111, out-diffusion of copper is inhibited.
[0064] After the transient liquid phase wafer-level assembly
process described with reference to FIG. 11, the resulting MEMS
packages shown in FIG. 1 are formed. The packages all have metal
stacks 130 which adhere to the substrate (silicon wafer) 110 as
well as to cap (glass plate) 120 and are thus substantially fully
hermetic. The wafer can subsequently be singulated into discrete
MEMS devices, for instance by sawing the wafer to separate the chip
areas into discrete chip packages.
[0065] In contrast to the low temperature range of 156 to
200.degree. C. for forming gold-indium intermetallics, any
re-melting of the intermetallic compounds would require much higher
temperatures, for example about 509.degree. C. for AuIn and about
540.degree. C. for AuIn.sub.2. Consequently, additional device
processing after package assembly is possible with less concern
about thermal degradation of the hermetic seal. An example is the
solder processes utilized for attachment to external parts such as
other components and circuit boards.
[0066] FIG. 12 shows another example embodiment 1200 of a hermetic
package for a MEMS structure which is combined with certain
isolated structures, as needed for instance in Variable
Electrostatic Actuators (VEAs). This example embodiment is based on
a wafer-level process flow for the fabrication of low-temperature
hermetically sealed MEMS structure devices, which requires an
especially high degree of plating uniformity, while the polymeric
sacrificial material embedding the MEMS structures is selected to
protect against the plating chemistry. The high plating uniformity
is achieved by a two-step etching process of the two seed layer
stack, in contrast to the single-step etching process of FIG. 4B
employed in the above-described fabrication flow. For this
application, the refractory metal of the seed layer stack is
advantageously selected from the VA Group of the Periodic Table of
Elements.
[0067] As FIG. 12 indicates, the structure of the package of device
1200 is analogous to the package of device 100 illustrated in FIG.
1. The difference of device 1200 compared to device 100 is the
configuration and the metal of the seed layer 1231a made of
refractory metal adhering to overcoat 111. In an example
implementation, seed film 1231a may have a thickness of 100 nm and
include a refractory metal of the V A Group of the Periodic Table
of Elements, such as tantalum, niobium, or vanadium. Seed film 131b
may have a thickness of 200 nm and include a metal of high
electrical conductivity such as copper or aluminum. As illustrated
in FIG. 12, seed film 1231a has a width 1231c, which is
substantially identical to the width 130a of the stack of plated
metal layers, while seed film 131b has the width 131c, which is
smaller than width 1231c. In example DMDs, width 131c may be
between about 100 .mu.m and 150 .mu.m, and width 1231c may be
between about 120 .mu.m and 170 .mu.m. As a consequence of the
different widths, seed film 1231a has a sidewall 1238 different
from the sidewall 138 of the seed film 131b.
[0068] Seed metal layers 1231a and 131b are deposited in a process
step analogous to the deposition step described in conjunction with
FIG. 3B. Seed metal layer 131b (for instance, copper) is etched in
a process step as described in conjunction with FIG. 4B. On the
other hand, seed metal layer 1231a (for instance, tantalum) is
etched in a separate etching step in the time window after
completing the plating processes of the metal layers described in
FIG. 5, but before the removal of the sacrificial polymer layer
protecting the MEMS structures depicted in FIG. 6.
[0069] The described example embodiments are merely illustrative
and not intended to be construed in a limiting sense. The disclosed
principles apply to any semiconductor material for the chips,
including silicon, silicon germanium, gallium arsenide, gallium
nitride, or any other semiconductor or compound material used in
manufacturing. The same principles may be applied both to MEMS
components formed over the substrate surface and to MEMS components
formed within the substrate. The caps used in packaging the
components may be flat, curved, or any other geometry that suits
individual needs and preferences. The caps may be transparent or
completely opaque to all or specific wavelengths or ranges of
wavelengths of visible light, infrared light, radio frequency or
radiation in other portions of the electromagnetic spectrum.
[0070] The contacting metal layers of the stacks formed on the
substrate and cap may be other than gold and indium, with other
suitable choices being disclosed in application Ser. No. 13/671,734
filed Nov. 8, 2012, the entirety of which is incorporated by
reference herein. Also, the relative widths of the metal stacks can
be reversed, with the wider stacks being formed on the cap and the
narrower stack being formed on the substrate. In such case, the top
layer of the wider stack formed on the cap instead of the substrate
will be formed of the higher melting temperature meta; (e.g., gold)
and the top layer of the narrower stack formed on the substrate
instead of the cap will be formed of the lower melting temperature
metal. In such case, too, it may be advantageous to join the
substrate from above to the cap, rather than join the cap from
above to the substrate, to assist collection of liquefied lower
melting temperature metal on the wider higher melting temperature
metal.
[0071] For fully hermetic MEMS packages, the described approach
realized that general eutectic bonding may offer low temperature
sealing of packages and thus be compatible with low temperature
MEMS structures, but the resulting seals would de-bond at the same
low temperatures as the sealing process and thus not allow
post-sealing temperatures above the sealing temperature as required
by some customer board assembly and device operations.
[0072] The problem is addressed of sealing low cost hermetic
packages at low temperatures--and thus permitting lubrication of
surface MEMS structures--but allowing device operation at
temperatures significantly above the sealing temperature. In the
example gold/indium system approach a methodology is based on a
transient liquid phase sealing technique at low temperatures, which
creates intermetallic compounds re-melting only at much higher
temperatures. Yet, in a configuration wherein the gold amount is in
excess, the indium amount is restricted and kept within confined
borders. In the described process flow, indium and gold are kept
separate until immediately before sealing, creating a thermally
stable solution. Making the indium bond line asymmetrical relative
to the gold bond line, and especially selecting in indium bond line
significantly narrower than the gold bond line, allows the gold
surface to react with any excess indium before it can enter the
MEMS device area, capturing the indium as intermetallic
compounds.
[0073] In an example new package design, the package structures are
electrically isolated from the MEMS structures; any copper used in
seed layer and metallization stacks is inhibited by overlaying
metal barriers from diffusing into the MEMS operating space. The
temperature range, in which the indium is consumed by the gold,
does not have to be much higher than the indium melting temperature
(156.63.degree. C.); it is preferably in the range from about 156
to 200.degree. C. On the other hand, the re-melting temperatures of
indium-gold intermetallic compounds are much higher: for AuIn
509.6.degree. C., for AuIn.sub.2 540.7.degree. C. It is thus a
technical advantage for hermetic low temperature MEMS structures
(especially with the need for temperature-sensitive lubricants)
that the assembly temperature can be kept under 200.degree. C.,
while applications and operations at much higher post-assembly
temperatures can reliably be tolerated. Another advantage is that
the cost of hermetic MEMS packages fabricated by this method
compares well with the cost of conventional non-hermetic MEMS
packages.
[0074] The described example packaging method separates indium and
gold from each other until right at the assembly step, thus
creating a thermally stable solution in contrast to known methods,
where indium bodies are placed in contact with gold bodies during
the fabrication process. Since indium and gold diffuse rapidly at
elevated temperatures, and significantly even at ambient
temperature, intermetallic compound are continuously produced at
these interfaces. When the assembly temperature is reached, the
intermetallic compounds do not re-melt and can thus not participate
in the bonding process. Consequently, these interfaces may not be
thermally stable at ambient temperature, are preferably not exposed
before assembly to processing steps requiring elevated
temperatures, and have limited shelf life before assembly.
[0075] The described example packaging method uses asymmetrical
bond line widths. In particular, the indium bond line is
significantly narrower than the gold bond line. Consequently, the
gold surface can react with any excess indium and can capture it as
intermetallic compounds. With contacting surfaces of the indium
body and the gold body at the same width, as melted indium has a
strong tendency to push out of a bonding surface during an assembly
step, there may be a greater chance to enter the MEMS device
area.
[0076] Those skilled in the art will appreciate that many other
embodiments and variations are possible within the scope of the
claimed invention.
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