U.S. patent application number 15/188481 was filed with the patent office on 2016-10-13 for autoconfigurable phase-locked loop which automatically maintains a constant damping factor and adjusts the loop bandwidth to a constant ratio of the reference frequency.
The applicant listed for this patent is TEXAS INSTRUMENTS INCORPORATED. Invention is credited to Ajay Kumar, Krishnaswamy Nagaraj, Joonsung Park.
Application Number | 20160301418 15/188481 |
Document ID | / |
Family ID | 47353232 |
Filed Date | 2016-10-13 |
United States Patent
Application |
20160301418 |
Kind Code |
A1 |
Kumar; Ajay ; et
al. |
October 13, 2016 |
Autoconfigurable Phase-Locked Loop Which Automatically Maintains a
Constant Damping Factor and Adjusts the Loop Bandwidth to a
Constant Ratio of the Reference Frequency
Abstract
A phase-locked loop (PLL) includes a state machine programmed to
automatically produce a set of control signals to select a
charge-pump current and integrating capacitance value to
automatically adjust a loop bandwidth of the PLL. A charge-pump DAC
generates a charge-pump current of magnitude controlled by the
state machine control signals. An integrator integrates the
charge-pump output current to produce an integrated charge-pump
output signal. The integrator has a plurality of capacitors
switchably selected by control signals from the state machine to
produce an integrating capacitance value. A voltage controlled
oscillator (VCO) produces a PLL output frequency in response to the
integrated charge-pump output signal.
Inventors: |
Kumar; Ajay; (Phoenix,
AZ) ; Nagaraj; Krishnaswamy; (Plano, TX) ;
Park; Joonsung; (Allen, TX) |
|
Applicant: |
Name |
City |
State |
Country |
Type |
TEXAS INSTRUMENTS INCORPORATED |
Dallas |
TX |
US |
|
|
Family ID: |
47353232 |
Appl. No.: |
15/188481 |
Filed: |
June 21, 2016 |
Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
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13525285 |
Jun 16, 2012 |
9401722 |
|
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15188481 |
|
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61498922 |
Jun 20, 2011 |
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Current U.S.
Class: |
1/1 |
Current CPC
Class: |
H03L 7/06 20130101; H03L
2207/04 20130101; H03L 7/087 20130101; H03L 7/0898 20130101; H03L
7/0896 20130101; H03L 7/1075 20130101; H03L 7/107 20130101; H03L
7/18 20130101; H03L 7/093 20130101; H03L 7/1072 20130101 |
International
Class: |
H03L 7/107 20060101
H03L007/107; H03L 7/18 20060101 H03L007/18; H03L 7/087 20060101
H03L007/087 |
Claims
1. A phase-locked loop (PLL), comprising: a frequency detector
circuit for estimating a frequency of a reference frequency signal
by counting a number of cycles of the reference frequency signal
over a fixed period of time; a phase detector for generating up and
down command signals in response to phase differences between the
reference frequency signal and a frequency signal related to a base
PLL output frequency signal; a circuit for producing control
signals in dependence upon the frequency detected by said frequency
detector; a charge-pump DAC for generating a charge-pump current,
said charge-pump DAC being connected to receive said up and down
command signals and control signals from said circuit for producing
control signals to produce a charge-pump output current of
magnitude selected by said control signals from said circuit for
producing control signals; an integrator for integrating said
charge-pump output current, said integrator including having
plurality of capacitors switchably selected by control signals from
said circuit for producing control signals to produce an
integrating capacitance value; and a voltage controlled oscillator
(VCO) for producing the base PLL output frequency signal in
response to said integrated charge-pump output signal.
2. The PLL of claim 1 wherein said circuit for producing control
signals is a state machine.
3. The PLL of claim 2 wherein said state machine is programmed to
automatically produce a set of control signals to select a
charge-pump current and integrating capacitance value to
automatically adjust a loop bandwidth of said PLL.
4. The PLL of claim 2 wherein said state machine is programmed to
automatically produce a set of control signals to select a
charge-pump current and integrating capacitance value to
automatically adjust a loop bandwidth of said PLL over an entire
range of reference frequencies over which said PLL operates.
5. The PLL of claim 2 wherein said integrator comprises a resistor
and a first capacitor DAC circuit between said charge-pump output
and a reference potential and a second capacitor DAC circuit
between said charge-pump output and the reference potential.
6. The PLL of claim 5 wherein each of said capacitor DAC circuit
comprises a plurality of capacitors and a corresponding plurality
of switches, each switch controlled by a command signal from said
state machine to interconnect selected capacitances to produce a
desired integrating capacitance value.
7. The PLL of claim 2 wherein said charge-pump DAC comprises a
first set of current sources that are selected in response to an up
command from said phase detector and a second set of current
sources that are selected in response to a down command from said
phase detector.
8. The PLL of claim 1 further comprising a transconductance
amplifier for receiving said integrated charge-pump output signal
to provide a frequency controlling signal to said VCO.
9. The PLL of claim 2 further comprising a frequency divider to
divide the PLL base output frequency signal to produce the
frequency signal related to the base PLL output frequency.
10. The PLL of claim 2 further comprising a reference frequency
divider to produce an internal reference frequency to establish
states of said state machine.
Description
CROSS-REFERENCE TO RELATED APPLICATIONS
[0001] This continuation application claims priority to U.S. patent
application Ser. No. 13/525,285, filed Jun. 16, 2012, which claims
priority to and the benefit of U.S. Provisional Patent Application
No. 61/498,922, filed Jun. 20, 2011, both of which are incorporated
herein by reference in their entirety.
BACKGROUND
[0002] 1. Field
[0003] The various circuit embodiments described herein relate in
general to phase-locked loops (PLLs), and, more specifically, to
PLLs and methods for making and using the same in which the loop
bandwidth scales with PLL the reference frequency while maintaining
a constant damping factor, F.sub.REF, without a requirement that
the value of the reference frequency, F.sub.REF, be known.
[0004] 2. Background
[0005] An example of a typical phase-locked loop circuit (PLL) 10
is shown in FIG. 1, to which reference is now made. The PLL 10 has
a digital phase-frequency detector (DPFD) 12, herein sometimes
referred to as a "phase detector," that receives a reference
frequency (F.sub.REF) signal on a first input line 14 and a
feedback signal on a second input line 16. The DPFD 12 determines
whether the phase of the feedback signal leads or lags the phase of
the reference frequency, F.sub.REF, to command either an up or down
signal on output lines 18 and 20, respectively. The up command, for
example, indicates that the phase of the feedback signal leads the
phase of the reference frequency, F.sub.REF, and the down command
indicates that the phase of the feedback signal lags the phase of
the reference frequency, F.sub.REF.
[0006] The signal on the up output line 18 controls a switch 22 to
apply current from a first current source 24 to an integrator 26 to
increase the voltage on the input 27 of the transconductance
amplifier 28. The signal on the down output line 20 controls a
switch 30 to sink current through a second current source 32 from
the integrator 26 to a reference potential, or ground, to decrease
the voltage on the input of the transconductance amplifier 28. The
integrator 26 has a first capacitor 34 between the input 27 to the
transconductance amplifier 28 and a reference potential or ground.
In addition, the integrator 26 has a resistor 36 and a second
capacitor 38 in series between the input to the transconductance
amplifier 28 and the reference potential, or ground.
[0007] The transconductance amplifier 28 produces an output
current, I.sub.VCO, on line 40 to control the frequency of a
voltage-controlled oscillator (VCO) 42. The VCO 42 produces a base
output frequency on line 44 that is proportional to the input
voltage to the transconductance amplifier 28, which, as described
above, is proportional to the amount of lead or lag of the phase of
the feedback voltage on line 16 with respect to the reference
frequency, F.sub.REF. The base output frequency from the VCO 42 on
line 44 may be divided by a number, for example Q.sub.DIV, by a
frequency divider 46 to provide a PLL frequency output, F.sub.OUT,
on output line 48. The base frequency output from the VCO 42 on
line 44 may also be divided by a number, for example, M.sub.DIV, to
provide a frequency output on feedback line 16 to the second input
of the DPFD 12 for comparison with the reference frequency,
F.sub.REF. The base frequency output from the VCO 42 can also be
feedback to the DPFD 12 by another means to make a comparison with
the reference frequency, F.sub.REF.
[0008] One of the problems, however, especially for a chip
manufacturer, is that often the value of the reference frequency,
F.sub.REF, that customers may employ in the operation of the PLL is
not known. Consequently, the design of a single PLL that is
suitable for diverse purposes can be very difficult. Moreover, PLLs
are often designed to operate over a large reference frequency
range. For example in some applications, the reference frequency,
FREF, may be anywhere in a range between 2 MHz and 30 MHz.
[0009] This can be appreciated from an analysis of the loop
behavior of the circuit 10 of FIG. 1, which can be modeled by the
phase-domain model 50 of FIG. 2, to which reference is now
additionally made. In the phase-domain model 50 of FIG. 2, the
phase of the input signal, .phi..sub.REF, is applied on line 52 to
an adder 54, the output of which is applied to a loop filter 56.
The loop filter 56 models the transistor level response of the
feedback loop of the circuit 10 of FIG. 1. The output of the loop
filter 56 is applied to a transconductance amplifier 58, which
produces an output that is applied to an integrating capacitor 60
and to a delay block 62. The transconductance amplifier 58 along
with the integrating capacitor 60 models the behavior of the
transconductor circuit 28, VCO 42, and feedback divider 47 of FIG.
1. The delay supplied by the delay block models the sample and hold
delay of the DPFD 12, which in the example illustrated is chosen to
be equal to 0.6 times the time period of the F.sub.REF signal. The
output of the delay block 62 is subtracted in the adder 54 from the
input phase reference signal, .PHI..sub.REF, on line 52. To
complete the model of the loop behavior, K.sub.VCO is simulated
from the given oscillator architecture.
[0010] FIG. 3, to which reference is now additionally made, is a
graph of closed loop gain in dB verses frequency for two input
reference frequencies of 2 megahertz and 30 megahertz. Thus, for a
range of reference frequencies, F.sub.REFs, between 2 MHz and 30
MHz (the actual value being unknown) +N.sub.DIV (the actual value
being unknown) the following issues occur.
[0011] A typical PLL is designed with a loop-bandwidth of less than
F.sub.REF/10 in order to get a stable response from the PLL across
all process and voltage corners. Higher loop-bandwidth translates
to faster settling time for the PLL 10. However, the absolute value
of the bandwidth can be chosen based on the particular application
in which the PLL is used. The zero 66 of the loop-filter which is
formed by resistor 36 and capacitor 38 is usually chosen to be a
factor 1/K1 of the loop-bandwidth. The absolute value of the factor
1/K1 can change with the intended application. As an example, in
this embodiment the factor is set at K1=3, so zero 66 is parked
near 66 KHz. The pole 68, which is formed by resistor 36 and the
series combination of capacitor 34 and capacitor 38, is usually
chosen to be a factor K2 of the loop-bandwidth. In this embodiment
the value of K2 is chosen to be 3 so pole 68 is set at 600 KHz.
[0012] With the above combination of loop-filter pole and zero, the
bandwidth comes close to desired value of 200 KHz as shown by curve
67 of FIG. 3. The value of the charge-pump is chosen in conjunction
of loop-gain such that the loop is stable and loop-peaking is met
for the application. Now if a traditional PLL, which is designed
for F.sub.REF=2 MHz and output of 400 MHz, is used with input
F.sub.REF=30 MHz, then it does not work, because for 30 MHz PLL,
the desired loop-bandwidth would be 3 MHz and in that case both
designed zero 66 and pole 68 will come inside the loop-bandwidth as
shown in FIG. 4. As a result the PLL loop frequency response
becomes the curve 72 shown in FIG. 3 which has over 20 dB of
peaking. This implies that system has gone unstable.
[0013] Another challenge is that it is desirable for the output
frequency, F.sub.OUT, be in a range between 100 MHz and 500 MHz.
The applicable formulae are:
LG = I CP K v K LPF M ##EQU00001## .omega. n = I CP K v MC 1
##EQU00001.2## .zeta. = 1 2 I CP K v C 1 M R 1 ##EQU00001.3##
.omega. u = I CP K v R 1 M ##EQU00001.4##
where: [0014] LG is the loop gain [0015] I.sub.CP is the
charge-pump current [0016] K.sub.V is the gain of the VCO 42 [0017]
K.sub.LPF is the response of the loop low-pass filter 56 [0018] M
is the frequency divisor in the feedback loop [0019] .omega..sub.n
is the natural frequency of the loop [0020] C.sub.1 is the
capacitance of the loop zero capacitor 60 [0021] .zeta. is the loop
damping factor [0022] R1 is the resistance of the loop zero
resistor 36 [0023] .omega..sub.u is the frequency of the unity gain
cross-over point
[0024] For the case where the loop frequency, F.sub.REF, is 2 MHz,
the loop bandwidth is 200 KHz, and the zero is at 50 KHz, the
charge-pump current, I.sub.CP, is chosen so that the damping
factor, is approximately 1 for an output frequency, F.sub.OUT, of
400 MHz. This can be seen in the graph of loop gain verses
frequency of FIG. 5, to which reference is now additionally made.
The curve 80 shows the 400 MHz frequency response and curve 82
shows a 100 MHz frequency response. Over an output frequency range
between 100 MHz and 500 MHz, with I.sub.CP held constant and
M.sub.DIV varying from 50 to 250, it can be seen that the loop gain
has an increase factor of five, and is only marginally stable.
Thus, even though the reference frequency, F.sub.REF, may be known,
loop may become unstable. Therefore, in order to maintain loop
stability, the traditional approach requires the user to specify
information about the reference frequency, F.sub.REF, to enable the
charge-pump current, I.sub.CP, to be scaled with respect to the
frequency divider, M.sub.DIV.
[0025] Nevertheless, even though a reference frequency, F.sub.REF,
may be specified, as a practical matter, most PLL designs are
optimized for only a few reference frequencies, F.sub.REFs. For
other reference frequencies, F.sub.REFs, the damping factor,
.zeta., may still change. Changes in the damping factor, .zeta.,
may cause overshoot and stress the device.
[0026] What is needed, therefore, is a PLL and method for making
and using it in which the loop bandwidth scales with the reference
frequency, F.sub.REF, whereby it is not necessary to actually know
the reference frequency, F.sub.REF. Also needed is an
autoconfigurable phase-locked loop which automatically maintains a
constant damping factor and adjusts the loop bandwidth to a
constant ratio of the reference frequency.
SUMMARY
[0027] According to one embodiment disclosed herein, a phase-locked
loop (PLL) includes a frequency detector for detecting a frequency
of an unknown reference frequency and a phase detector for
generating up and down command signals in response to phase
differences between the unknown reference frequency and a frequency
related to a base PLL output frequency. A circuit is provided for
producing control signals in dependence upon the frequency detected
by the frequency detector. A charge-pump DAC generates a
charge-pump current and is connected to receive the up and down
command signals and control signals from the circuit for producing
control signals to produce a charge-pump output current of
magnitude selected by the control signals from the circuit for
producing control signals. An integrator integrates the charge-pump
output current and has a plurality of capacitors switchably
selected by control signals from the circuit for producing control
signals to produce an integrating capacitance value. A voltage
controlled oscillator (VCO) produces the base PLL output frequency
in response to the integrated charge-pump output signal. In one
embodiment, the circuit for producing control signals is a state
machine that is programmed to automatically produce a set of
control signals to select a charge-pump current and integrating
capacitance value to automatically adjust a loop bandwidth of the
PLL.
[0028] According to another embodiment disclosed herein, a
phase-locked loop (PLL) includes means for automatically adjusting
a loop bandwidth without requiring knowledge of a reference
frequency of the PLL. The means for automatically adjusting the
loop bandwidth includes a circuit for measuring a frequency related
to the reference frequency, a state machine for producing logic
states corresponding to the frequency related to the reference
frequency, a first digital-to-analog converter connected to adjust
capacitances in the PLL according to the logic states of the state
machine, and a second digital-to-analog converter connected to
modify a charge-pump current to an integrator of the PLL according
to the logic states of the state machine. The PLL 1 automatically
maintains a constant damping factor.
[0029] According to yet another embodiment disclosed herein a
method is provided for automatically adjusting a loop bandwidth of
a phase-locked loop (PLL). The method includes detecting a
frequency of an unknown reference frequency and generating up and
down command signals in response to phase differences between the
unknown reference frequency and a PLL output frequency. Control
signals are developed, depending on the detected frequency. In one
embodiment, the control signals are developed by a state machine. A
charge-pump current of magnitude established by the control signals
is generated, and an integrated charge-pump current is produced
using capacitors selected according to the control signals. The
frequency of a voltage controlled oscillator (VCO) is adjusted,
based on the integrated charge-pump current to producing the PLL
output frequency.
BRIEF DESCRIPTION OF THE DRAWINGS
[0030] FIG. 1 is an electrical schematic diagram showing an example
of a typical phase-locked loop (PLL) circuit.
[0031] FIG. 2 is an electrical schematic diagram of a phase-domain
model that models the loop behavior of the PLL of FIG. 1.
[0032] FIG. 3 is a graph of loop gain in dB verses frequency in
megahertz for reference frequencies of 2 megahertz and 30
megahertz.
[0033] FIG. 4 is a graph of frequency illustrating the pole and
zero of the PLL of FIG. 1 in relation to stable and unstable 3 dB
crossover points.
[0034] FIG. 5 is a graph of loop gain verses frequency of a PLL,
comparing frequency responses of 100 MHz and 400 MHz in the PLL of
FIG. 1.
[0035] FIG. 6 is an electrical schematic diagram showing an example
of an autoconfigurable phase-locked loop (PLL) circuit that
automatically adjusts the loop bandwidth and maintains a constant
damping factor.
[0036] FIG. 7 is an electrical schematic diagram showing an example
of a frequency detector circuit for providing input states to the
state machine of FIG. 6.
[0037] FIG. 8 is a state table showing an example of various states
of a state machine for controlling a charge-pump DAC and capacitor
DACs for reference frequencies of 2 MHz and 30 MHz, and output
frequencies of 100 MHz, 400 MHz, and 600 MHz.
[0038] FIG. 9 is an electrical schematic diagram showing an example
of a charge-pump DAC that may be employed in the autoconfigurable
phase-locked loop (PLL) circuit of FIG. 6.
[0039] FIG. 10 shows the quantization error of the charge-pump DAC
of FIG. 9.
[0040] FIG. 11 is an electrical schematic diagram showing an
example of a capacitor-DAC circuit that may be employed in the
autoconfigurable phase-locked loop (PLL) circuit of FIG. 6.
[0041] FIGS. 12 and 13 are graphs respectively showing step and
frequency response in the PVT corners.
[0042] In the various figures of the drawing, like reference
numbers are used to denote like or similar parts.
DETAILED DESCRIPTION
[0043] FIG. 6 is an electrical schematic diagram showing an example
of an autoconfigurable phase-locked loop (APLL) circuit 90 that
automatically adjusts the loop bandwidth and maintains a constant
damping factor. The APLL circuit 90 receives the reference
frequency, F.sub.REF, on input line 14 to a user programmable
pre-divider circuit 92 to produce an internal reference frequency
F.sub.REF.sub._.sub.INT on line 94. The internal reference
frequency F.sub.REF.sub._.sub.INT is connected to a digital
phase-frequency detector (DPFD) 12 as well as a frequency detector
96. The DPFD 12 develops up and down charge-pump command DAC
signals on respective lines 18 and 20 in the manner described above
with reference to FIG. 1, depending on whether the phase of the
feedback signal on line 16 leads or lags the phase of the internal
reference frequency F.sub.REF.sub._.sub.INT.
[0044] A charge-pump DAC circuit 98, described in greater detail
with reference to FIG. 9 below, has an output on line 27 that is
integrated by an integrator 100 to increase or decrease the input
voltage on the transconductance amplifier 28. The charge-pump DAC
98 includes a number of switches that may be connected in various
combinations to provide selected charge-pump currents, depending on
the value of the internal reference frequency,
F.sub.REF.sub._.sub.INT.
[0045] The integrator 100 includes a first capacitor-DAC circuit
102 in series with the resistor 36 between the line 27 and a
reference potential, or ground node 103. The integrator 100 also
has a second capacitor-DAC circuit 104 connected directly between
the line 27 and the reference potential or ground node. Details of
the first and second capacitor-DAC circuits 102 and 104 are shown
in greater detail in FIG. 11 below. The capacitor-DAC 102 and the
capacitor DAC 104 each comprise a number of capacitors that may be
connected in various combinations to provide selected capacitances,
also depending on the value of the internal reference frequency,
F.sub.REF.sub._.sub.INT. These selections are accomplished by
detecting the frequency of the internal reference frequency,
F.sub.REF.sub._.sub.INT, in the frequency detector 96, which is
described in greater detail with reference to FIG. 7 below.
[0046] In a manner similar to that described with reference to FIG.
1 above, the transconductance amplifier 28 produces an output
current, I.sub.VCO, on line 40 to control the frequency of a
voltage-controlled oscillator (VCO) 42. The VCO 42 produces a base
output frequency on line 44 that is proportional to the input
voltage to the transconductance amplifier 28, which, as described
above, is proportional to the amount of lead or lag of the phase of
the feedback voltage on line 16 with respect to the internal
reference frequency, F.sub.REF.sub._.sub.INT. The output from the
VCO 42 on line 44 may be divided by a number, for example
Q.sub.DIV, by a frequency divider to provide a frequency output,
F.sub.OUT, on output line 48. The output from the VCO 42 on line 44
may also be divided by a number, for example, M.sub.DIV, to provide
a frequency output on feedback line 16 to the second input of the
DPFD 12 for comparison with the internal reference frequency,
F.sub.REF.sub._.sub.INT.
[0047] To automatically adjust the PLL in dependence on the
frequency of the reference frequency, F.sub.REF, that is applied,
the output of the frequency detector 96 on line 106 presents a
number of logic states to a state machine 108, which develops
control signals to the charge-pump DAC 98, the capacitor DAC 102,
and the capacitor DAC 104 on respective lines 110, 112, and 114.
Thus, the state machine 108 configures the digital logic circuits
of the charge-pump DAC 98 and the capacitor DAC circuits 102 and
104 so that the currents in the charge-pump DAC 98 and the
capacitors of the capacitor DACs 102 and 104 are selected to
compensate for the particular reference frequency, F.sub.REE,
applied to the APLL 90 to automatically maintain the loop bandwidth
over the range of reference frequencies that may be expected to be
employed.
[0048] Using traditional PLL parameters,
.omega. n = I CP K v MC 1 ##EQU00002## .zeta. = 1 2 I CP K v C 1 M
R 1 ##EQU00002.2## Thus , .omega. 3 dB = I CP K v R 1 M
##EQU00002.3##
where: [0049] .omega..sub.n is the natural frequency of the loop
[0050] I.sub.CP is the charge-pump current=k.sup.2I.sub.B [0051]
I.sub.B is the input bias current [0052] K.sub.V is the gain of the
VCO [0053] M is the feedback divisor [0054] C.sub.1 is the loop
zero capacitance [0055] R.sub.1 is the loop zero resistance [0056]
.zeta. is the loop damping factor [0057] .omega..sub.3dB is the 3
dB cross point for the loop (.about.2.zeta..omega..sub.n) [0058] If
we can generate [0059] 1) the charge-pump current, I.sub.CP, to be
proportional to F.sub.OUT, that is
I.sub.CP=k.sup.2I.sub.B*M*F.sub.REF.sub._.sub.INT=k.sup.2I.sub.B*F.sub.OU-
T, and [0060] 2) C.sub.1 proportional to 1/F.sub.REF.sub._.sub.INT,
that is C.sub.1=C.sub.U/F.sub.REF.sub._.sub.INT then,
[0060] .zeta. eff = 1 2 k 2 I B MF REF_INT K v C U MF REF_INT R 1 =
R 1 k I B K v C U 2 .apprxeq. 1 ##EQU00003## .omega. n = k 2 I B MF
REF_INT K v M .times. F REF_INT C U = kF REF_INT I B K v C U
##EQU00003.2## .omega. 3 dB = kI B K v R 1 F REF_INT
##EQU00003.3##
where [0061] C.sub.U is the total filter capacitor [0062]
.zeta..sub.eff is the effective damping of the loop [0063] Thus,
f.sub.3dB.infin.F.sub.REF.sub._.sub.INT
[0064] To find F.sub.OUT: [0065] I.sub.CP (.mu.A)=I.sub.B (3.75
mA)*M*F.sub.REF.sub._.sub.INT (MHz) [0066]
F.sub.out=M*F.sub.REF.sub._.sub.INT=500 mA with I.sub.CP=1.875
.mu.A [0067] F.sub.out=M*F.sub.REF.sub._.sub.INT=100 mA with
I.sub.CP=0.375 .mu.A [0068] C.sub.1=120 pF/F.sub.REF.sub._.sub.INT
(MHz) [0069] F.sub.out=500 MHz, F.sub.REF.sub._.sub.INT=2 MHz with
M=250 and C.sub.1=50 pF [0070] F.sub.out=100 MHz,
F.sub.REF.sub._.sub.INT=30 MHz with M=3 and C.sub.1=3.3 pF
[0071] An example of a frequency detector circuit 96 to provide
input states to the state machine 108 in FIG. 6 is shown with
additional reference now to FIG. 7. The example of a suitable
frequency detector circuit 96 uses a monostable multivibrator
circuit 120; however, it should be noted that the monostable
multivibrator 120 is only an example of a signal source that is
inexpensive to realize, and that many other circuit implantations
could be equally advantageously employed.
[0072] In the example illustrated, the monostable multivibrator
circuit 120 may be designed to oscillate at a 10 MHz frequency. It
should be noted that 10 MHz has been selected as a convenient
frequency against which the internal reference frequency,
F.sub.REF.sub._.sub.INT, can be compared; however, any other
suitable frequency can be selected.
[0073] A current source 122 supplies a constant charging current,
I.sub.OSC, from a constant analog voltage supply, VDDA, to a
capacitor 124. The node 126 between the current source 122 and
capacitor 124 is connected to the inverting input of a comparator
128, and a bandgap voltage supply 130 is connected to the
noninverting input of the comparator 128 to supply a stable voltage
V.sub.BG thereto. The comparator 128 is referenced to a constant
digital voltage source, VDDD.
[0074] The output from the comparator 128 is fed back to a switch
132 across the capacitor 124. The output of the comparator 128 is
also supplied to an inverter 134 to provide the 10 MHz output
frequency on output line 136. The inverter 134 is also referenced
to the constant digital voltage supply, VDDD. Thus, in operation,
when the charge on the capacitor 124 reaches the threshold of the
comparator 128 established by the bandgap voltage VBG, the output
of the comparator 128 will change states, closing the switch 132 to
discharge the capacitor 124. The frequency of the monostable
multivibrator can therefore be established by adjusting the size of
the capacitor 124 and magnitude of its charging current, which
determines the rate at which the capacitor 124 is charged.
[0075] Thus, with a monostable multivibrator of the type that
provides a relatively stable output frequency, F.sub.OUT, an
estimate of the reference frequency, F.sub.REF, may be made. To
make this estimate, the 10 MHz output from the inverter 134 is
connected to a counter 140, which counts 64 cycles of the 10 MHz
signal (in 6.4 .mu.s). At the same time, the internal reference
frequency, F.sub.REF, is applied to a counter 142. The counters 140
and 142 are reset whenever the user changes the input or output
frequency of the PLL, functionally indicated by box 146. It should
be noted that the 10 MHz frequency of the monostable multivibrator
120 and the count of the counter 140 are selected to enable the
range of internal reference frequencies, FREF_INT, that are
expected to be employed to be counted.
[0076] The outputs from the counters 140 and 142 are connected to a
frequency calculator 144, which determines the number of cycles of
the internal reference frequency, F.sub.REF, that occur during the
64 cycles of the 10 MHz signal from the monostable multivibrator
120. The frequency calculator 144 produces output states
representing the number of cycles of the internal reference
frequency, F.sub.REF, occurring during this period on output lines
106 to the state machine 108.
[0077] It will be recognized that the bandgap voltage supply 130
and the capacitor 124 have a very low temperature coefficient. Most
of the frequency variation will come from the current source 122,
I.sub.OSC. The jitter/F.sub.OSC ripple in VDDA can be determined
from:
I OSC = C OSC V BG T ##EQU00004## f OSC = I OSC C OSC V BG
##EQU00004.2## .DELTA. f OSC = .DELTA. I OSC + .DELTA. C OSC +
.DELTA. V BG ##EQU00004.3## .DELTA. f OSC = .+-. 10 % .+-. 5 % .+-.
1 % = .+-. 20 % ##EQU00004.4##
[0078] To determine F.sub.OUT, [0079] I.sub.CP (.mu.A)=I.sub.B
(3.75 mA)*M*F.sub.REF.sub._.sub.INT (MHz) [0080] If
Fout=M*F.sub.REF.sub._.sub.INT=500 MHz, [0081] this implies that
I.sub.CP=1.875 .mu.A [0082] If Fout=M*F.sub.REF.sub._.sub.INT=100
MHz [0083] This implies that I.sub.CP=0.375 uA [0084] C.sub.1=120
pF/F.sub.REF.sub._.sub.INT (MHz) [0085] For Fout=500 MHz,
F.sub.REF.sub._.sub.INT=2 MHz, M=250 and C.sub.1=50 pF [0086] For
Fout=100 MHz, F.sub.REF.sub._.sub.INT=30 MHz, M=3 and C.sub.1=3.3
pF
[0087] Using this information, the various outputs from the state
machine 108 in response to the frequencies determined by the
frequency calculator 144 can be determined. Examples of some of the
various states of the state machine 108 may assume to supply the
control signals are shown in the table 160 of FIG. 8, to which
reference is now additionally made. Thus, the outputs from the
state machine 108 adjusts the capacitances of the capacitors in the
charge-pump DAC 98, the capacitor DAC 102, and the capacitor DAC
104 in accordance with the states shown in the table 160 of FIG.
8.
[0088] One construction of a charge-pump DAC 180 that may be used
to provide the state-machine controlled capacitances is shown in
FIG. 9, to which reference is now additionally made. The
charge-pump DAC 180 receives up and down command signals from the
digital phase-frequency detector (DPFD) 12 (see FIG. 6) on
complementary input lines 18, 18z and 20, 20z respectively. The
output is derived on output line CP_OUT 27.
[0089] Current is normally sourced to or sunk from the charge-pump
circuit 180 by respective current sources 182 and 184, in the
example illustrated, each supplying 250 nA. In addition, a number
of additional current sources are switchably connectable to the
charge-pump on both the supply side and sink side, to selectively
supply additional current to the current supplied by the current
sources 182 and 184. In the example illustrated, for example,
current sources 186, 188, 190, and 192 are provided to selectively
supply additional currents of 125 nA, 250 nA, 0.5 .mu.A, and 1
.mu.A to the charge-pump. Likewise, current sources 194, 196, 198,
and 200 are provided to selectively sink additional currents of 125
nA, 250 nA, 0.5 .mu.A, and 1 .mu.A from the charge-pump.
[0090] The current sources 186, 188, 190, and 192 are controlled by
signals from the state machine 108 by selectively switching on and
off PMOS switch devices 310-311, 313-314, 316-317, and 319-320
respectively associated therewith. Likewise, the current sources
194, 196, 198, and 300 are controlled by signals from the state
machine 108 by selectively switching off and on PMOS switch devices
322-323, 325-326, 328-329, and 331-332 respectively associated
therewith. Since the current is either sourced or sunk from the
charge-pump, the switches in the "up" side of the circuit are
operated oppositely from the switches in the "down" side of the
circuit.
[0091] The quantization error of the charge-pump DAC 180 is shown
in FIG. 10, to which reference is now additionally made. In FIG. 10
the output frequencies, F.sub.OUT, of the PLL with the various
charge-pump values described above are shown for reference
frequencies of 2 MHz and 30 MHz. Curve 151 shows the quantization
error for an output frequency of 100 MHz with a 2 MHz reference
frequency, and curve 153 shows the quantization error for an output
frequency of 100 MHz with a 30 MHz reference frequency. It can be
seen that the peaking of the 100 MHz output for a 2 MHz reference
frequency is about 3.143, and the loop bandwidth is about 199.5
KHz. On the other hand, the peaking of the 100 MHz output for a 30
MHz reference frequency is about 3.143, and the loop bandwidth is
about 2.995 MHz. The loop resistor 36 is constant, and in the
example illustrated, is about 70 K.OMEGA..
[0092] In the example illustrated: [0093] I.sub.CP (0.38 .mu.-2.2
.mu.A) DAC and its Q-noise [0094] I .sub.CP.sub._.sub.DAC=0-3 .mu.A
(4 bit) [0095] I.sub.CP error is 1-LSB=0.2 .mu.A [0096] Max error
is I.sub.CP=0.375 .mu.A+I.sub.err=0.575 .mu.A [0097] C.sub.1 (4-60
pF) and its quantization noise [0098] C.sub.1.sub._.sub.DAC=0-64 pF
(5 bit) [0099] C.sub.1-DAC error is 1-LSB=2 pF [0100] Max error is
C.sub.1-DAC=4 pF+I.sub.err=6 pF
[0101] An example of a capacitor DAC 102 that can be used in the
autoconfigurable phase-locked loop (PLL) circuit 90 of FIG. 6 is
shown in FIG. 11 to which reference is now additionally made. The
capacitor DAC circuit 102 may be instantiated to provide selectable
capacitances for both capacitor DAC circuits 102 and 104 in the
circuit of FIG. 6, the capacitor DAC circuit 104 being shown as a
variable capacitor in FIG. 11 for simplicity. The capacitor circuit
102 in FIG. 11 includes a number of capacitors 342-346 that may be
selectively connected to a circuit output node 348 by a number of
PMOS switches 350-351, 353-354, 356-357, 359-360, and 362-363. The
various PMOS switches 350-351, 353-354, 356-357, 359-360, and
362-363 are controlled by outputs from the state machine 108 to
selectively connect one or more of the capacitors 342-346 in
parallel to provide a controllable capacitance.
[0102] Once an autoconfigurable phase-locked loop (PLL) circuit of
the type described here is designed for a F.sub.REF.sub._.sub.INT,
the loop can automatically adjust itself to be stable over a range
of reference frequencies, F.sub.REF.sub._.sub.INT from 2 MHz with
an output frequency of 400 MHz. Moreover, once the loop is designed
to have a stable charge-pump current, I.sub.CP, the loop state
machine 108 will automatically adjust the charge-pump current,
I.sub.CP, for other reference frequencies, F.sub.REF, and other
output frequencies, F.sub.OUT.
[0103] For example,
[0104] a. For F.sub.OUT=400 MHz, I.sub.CP=1.5 .mu.A (designed
Nominal value)
[0105] b. For F.sub.OUT'=600 MHz, I.sub.CP'=1.5 .mu.A*600/400=2.25
.mu.A
[0106] The loop state machine similarly scales C.sub.1. That is
once the loop is designed for one internal reference frequency,
F.sub.REF.sub._.sub.INT, and one output frequency, F.sub.OUT, then
the state machine scales it for all other values. For example, the
loop can be designed for F.sub.REF.sub._.sub.INT=2 MHz with
F.sub.OUT=400 MHz.
[0107] Auto Configuration algorithm
I CP = I B * MF REF_INT = I B * F OUT ##EQU00005## C 1 = C U / F
REF_INT ##EQU00005.2## I CP 1 I CP 0 = F OUT 1 F OUT 0 = C CYC 1 C
CYC 0 = .kappa. ##EQU00005.3## C fil 1 C fil 0 = F REF_INT 0 F
REF_INT 1 = .eta. ##EQU00005.4##
[0108] With the minimum charge-pump current,
I.sub.CP.sub._.sub.min, =0.25 .mu.A and the minimum capacitance for
C.sub.1, C.sub.1.sub._.sub.min=4 pF, if I.sub.CP changes from 0.375
to 2.25 therefore the ratio is 6. Thus, a 3-bit state machine may
be used, and to minimize variations in .omega..sub.3db and .zeta. a
4-bit DAC may be used. If C.sub.1 changes from 4 pF to 60 pF, a 4
bit state machine may be used, and to minimize variation in
.omega..sub.3dB and .zeta. a 5 bit DAC may be used.
[0109] The circuit is also relatively insensitive to PVT
variations: [0110] F.sub.OSC.varies.I.sub.OSC=n.I.sub.B [0111] This
implies:
[0111] C CYC = F REF_INT F OSC .varies. 1 nI B ##EQU00006## and
##EQU00006.2## I CP .varies. k 2 I B MF REF_INT ##EQU00006.3##
[0112] If I.sub.B becomes ".beta..sub.IB" from a PVT variation,
then the charge-pump current, I.sub.CP, and oscillator frequency,
F.sub.OSC, will increase by the same factor. Thus, the effective
internal reference frequency,
F.sub.REF.sub._.sub.INT.sub._.sub.eff, will appear as
F.sub.REF.sub._.sub.INT/.beta..
.omega. 3 dB = kI B K v R 1 F REF_INT ##EQU00007## .omega. 3 dB_eff
= k .beta. I B K v R 1 F REF_INT .beta. ##EQU00007.2##
[0113] Thus, the effective value of .omega..sub.3dB does not change
with process variation in the bias current. The algorithm works as
ratio of numbers, which is accurate over process variation. Graphs
of step and frequency response in the corners are shown
respectively in FIGS. 12 and 13.
[0114] Electrical connections, couplings, and connections have been
described with respect to various devices or elements. The
connections and couplings may be direct or indirect. A connection
between a first and second electrical device may be a direct
electrical connection or may be an indirect electrical connection.
An indirect electrical connection may include interposed elements
that may process the signals from the first electrical device to
the second electrical device.
[0115] Although the invention has been described and illustrated
with a certain degree of particularity, it should be understood
that the present disclosure has been made by way of example only,
and that numerous changes in the combination and arrangement of
parts may be resorted to without departing from the spirit and
scope of the invention, as hereinafter claimed.
* * * * *