U.S. patent application number 14/658649 was filed with the patent office on 2016-09-22 for semiconductor device and manufacturing process thereof.
The applicant listed for this patent is TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.. Invention is credited to CHI-CHENG HUNG, SHIU-KO JANGJIAN, POHAN KUNG, YING -JING LU, YU-SHENG WANG.
Application Number | 20160276156 14/658649 |
Document ID | / |
Family ID | 56924996 |
Filed Date | 2016-09-22 |
United States Patent
Application |
20160276156 |
Kind Code |
A1 |
KUNG; POHAN ; et
al. |
September 22, 2016 |
SEMICONDUCTOR DEVICE AND MANUFACTURING PROCESS THEREOF
Abstract
A semiconductor device is provided which includes a dielectric
layer over a gate structure of the semiconductor device. The
semiconductor device also includes a conductive interconnect
configured to couple the gate structure with an I/O region over the
conductive interconnect. The semiconductor also includes a metal
silicide layer disposed between the conductive interconnect and the
dielectric layer where the metal silicide is a silicide form of a
metal different from the conductive interconnect.
Inventors: |
KUNG; POHAN; (TAINAN CITY,
TW) ; LU; YING -JING; (KAOHSIUNG COUNTY, TW) ;
HUNG; CHI-CHENG; (TAINAN CITY, TW) ; WANG;
YU-SHENG; (TAINAN CITY, TW) ; JANGJIAN; SHIU-KO;
(TAINAN CITY, TW) |
|
Applicant: |
Name |
City |
State |
Country |
Type |
TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD. |
HSINCHU |
|
TW |
|
|
Family ID: |
56924996 |
Appl. No.: |
14/658649 |
Filed: |
March 16, 2015 |
Current U.S.
Class: |
1/1 |
Current CPC
Class: |
H01L 21/76855 20130101;
H01L 21/76834 20130101; H01L 21/76849 20130101; H01L 23/53238
20130101; H01L 29/78 20130101; H01L 23/53223 20130101; H01L
21/76889 20130101 |
International
Class: |
H01L 21/28 20060101
H01L021/28; H01L 29/78 20060101 H01L029/78; H01L 29/49 20060101
H01L029/49; H01L 29/66 20060101 H01L029/66; H01L 29/10 20060101
H01L029/10 |
Claims
1. A semiconductor device, comprising: a dielectric layer over a
gate structure of the semiconductor device; a conductive
interconnect configured to couple the gate structure with an I/O
region over the conductive interconnect; and a metal silicide layer
disposed above the conductive interconnect and the dielectric
layer, the metal silicide being a silicide form of a first metal
different from the conductive interconnect, and the metal silicide
layer comprising a sidewall substantially coplanar with a side wall
of the conductive interconnect.
2. The semiconductor device according to claim 1 further comprising
a conductive layer disposed between the conductive interconnect and
the metal silicide layer, wherein the conductive layer is the first
metal.
3. The semiconductor device according to claim 2 further comprising
a silicon layer inside the dielectric layer, wherein the silicon
layer is between the metal silicide layer and the dielectric
layer.
4. The semiconductor device according to claim 3, wherein the
silicon layer is further disposed on a periphery of the metal
silicide layer.
5. The semiconductor device according to claim 1, wherein the
coefficient of linear thermal expansion (CTE-l) of the conductive
interconnect is larger than the CTE of the metal silicide layer,
and the CTE-l of the metal silicide layer is larger than the CTE-l
of the dielectric layer.
6. The semiconductor device according to claim 2, wherein the
conductive layer includes one of cobalt, nickel, tungsten,
molybdenum, titanium, platinum and tantalum.
7. The semiconductor device according to claim 1, wherein the
conductive interconnect includes copper.
8. The semiconductor device according to claim 1, wherein a ratio
of thickness between the dielectric layer and the metal silicide
layer is between 1 and 200.
9. A semiconductor device, comprising: a first dielectric layer; a
conductive interconnect disposed within the first dielectric layer;
a metal silicide layer disposed over the conductive interconnect; a
silicon layer disposed on a periphery of the metal silicide layer;
and a second dielectric layer disposed over the metal silicide
layer and the silicon layer, the second dielectric layer covering a
top surface of the metal silicide layer.
10. The semiconductor device according to claim 9, wherein the
silicon layer is disposed between the metal silicide layer and the
second dielectric layer.
11. The semiconductor device according to claim 9, wherein the
coefficient of linear thermal expansion (CTE-l) of the conductive
interconnect is larger than CTE-l of the metal silicide layer, and
the CTE-l of the metal silicide layer is larger than the CTE-l of
the first and the second dielectric layers.
12. The semiconductor device according to claim 9, wherein the
conductive interconnect includes a first metal, and the metal
silicide layer is a silicide form of a second metal different from
the first metal.
13. The semiconductor device according to claim 12, wherein the
second metal includes one of cobalt, nickel, tungsten, molybdenum,
titanium, platinum and tantalum.
14. The semiconductor device according to claim 12 further
comprising a conductive layer including the second metal, disposed
between the conductive interconnect and the metal silicide
layer.
15. (canceled)
16. (canceled)
17. (canceled)
18. (canceled)
19. (canceled)
20. (canceled)
21. A semiconductor device, comprising: a dielectric layer over a
gate structure of the semiconductor device; a conductive
interconnect disposed within the dielectric layer; a metal silicide
layer disposed over the conductive interconnect; and a silicon
layer disposed on a periphery of the metal silicide layer and
covering the dielectric layer.
22. The semiconductor device according to claim 21, wherein the
coefficient of linear thermal expansion (CTE-l) of the conductive
interconnect is larger than the CTE-l of the metal silicide layer,
and the CTE-l of the metal silicide layer is larger than the CTE-l
of the dielectric layer.
23. The semiconductor device according to claim 21, wherein the
metal silicide layer is a silicide form of a metal selected from
one of cobalt, nickel, tungsten, molybdenum, titanium, platinum and
tantalum.
24. The semiconductor device according to claim 21, wherein the
conductive interconnect includes copper.
25. The semiconductor device according to claim 21, wherein a ratio
of thickness between the dielectric layer and the metal silicide
layer is between 1 and 200.
26. The semiconductor device according to claim 21, wherein the
conductive interconnect includes a first metal, and the metal
silicide layer is a silicide form of a second metal different from
the first metal.
Description
BACKGROUND
[0001] As the semiconductor manufacturing and fabrication industry
has progressed to advanced technology nodes, it can be found that
integration levels are increasing, device features are reduced, and
greater demands are increasing for device performance.
[0002] In a fabrication process for a semiconductor chip,
conductive interconnect structures are widely utilized for
electrically connect different components of the device and/or
connect external circuits. The requirements for reliability and
performance of the conductive interconnects are becoming more
stringent as the feature size continues to shrink. Advanced
manufacturing techniques are investigated for improving the
integrity of the conductive interconnects and the system
performance of the semiconductor chip.
BRIEF DESCRIPTION OF THE DRAWINGS
[0003] Aspects of the present disclosure are best understood from
the following detailed description when read with the accompanying
figures. It is noted that, in accordance with the standard practice
in the industry, various features are not drawn to scale. In fact,
the dimensions of the various features may be arbitrarily increased
or reduced for clarity of discussion.
[0004] FIGS. 1A-1L are cross sectional views of operations for
manufacturing a semiconductor device, in accordance with some
embodiments of the present disclosure.
[0005] FIG. 2 is a schematic showing a semiconductor manufacturing
platform, in accordance with some embodiments of the present
disclosure.
[0006] FIG. 3 is a flow diagram showing operations for
manufacturing a semiconductor device, in accordance with some
embodiments of the present disclosure.
[0007] FIG. 4 is a flow diagram showing operations for
manufacturing a semiconductor device, in accordance with some
embodiments of the present disclosure.
[0008] FIG. 5 is a flow diagram showing operations for
manufacturing a semiconductor device, in accordance with some
embodiments of the present disclosure.
DETAILED DESCRIPTION
[0009] The following disclosure provides many different
embodiments, or examples, for implementing different features of
the provided subject matter. Specific examples of components and
arrangements are described below to simplify the present
disclosure. These are, of course, merely examples and are not
intended to be limiting. For example, the formation of a first
feature over or on a second feature in the description that follows
may include embodiments in which the first and second features are
formed in direct contact, and may also include embodiments in which
additional features may be formed between the first and second
features, such that the first and second features may not be in
direct contact. In addition, the present disclosure may repeat
reference numerals and/or letters in the various examples. This
repetition is for the purpose of simplicity and clarity and does
not in itself dictate a relationship between the various
embodiments and/or configurations discussed.
[0010] Further, spatially relative terms, such as "beneath,"
"below," "lower," "above," "upper" and the like, may be used herein
for ease of description to describe one element or feature's
relationship to another element(s) or feature(s) as illustrated in
the figures. The spatially relative terms are intended to encompass
different orientations of the device in use or operation in
addition to the orientation depicted in the figures. The apparatus
may be otherwise oriented (rotated 90 degrees or at other
orientations) and the spatially relative descriptors used herein
may likewise be interpreted accordingly.
[0011] FIGS. 1A-1L are cross sectional views of operations for
manufacturing a semiconductor device 100, in accordance with some
embodiments of the present disclosure. Referring to FIG. 1A, a
semiconductor substrate 102 is provided. Semiconductor substrate
102 includes a semiconductor material such as silicon, silicon
germanium, or the like. Semiconductor substrate 102 may be lightly
doped with a p-type impurity to become a p-type silicon substrate
(P-substrate). Otherwise, semiconductor substrate 102 can also be
doped with an n-type impurity to be an n-type silicon substrate
(n-substrate). In some embodiments, semiconductor substrate 102
includes an elementary semiconductor such as silicon or germanium
in crystal, polycrystalline, or an amorphous structure. In some
embodiments, semiconductor substrate 102 may be compound
semiconductor such as gallium arsenide (GaAs), gallium phosphide
(GaP), silicon carbide (SiC), indium phosphide (InP), indium
arsenide (InAs), or indium antimonide (InSb). In other embodiment,
semiconductor substrate 102 may be an alloy semiconductor such as
silicon germanium (SiGe), gallium arsenide phosphide (GaAsP),
aluminium gallium arsenide (AlGaAs), aluminium indium arsenide
(AlInAs), germanium indium arsenide (GaInAs), germanium indium
phosphide (GaInP), and/or germanium indium arsenide phosphide
(GaInAsP) or any other suitable materials.
[0012] In some embodiments, semiconductor substrate 102 may be a
silicon on insulator (SOI) substrate. SOI substrates are fabricated
using separation by implantation of oxygen (SIMOX), wafer bonding,
and/or other suitable methods. In some examples, semiconductor
substrate 102 includes a doped epitaxy layer or a buried layer. In
other examples, semiconductor substrate 102 has a multilayer
compound structure.
[0013] In FIG. 1B, various isolation features 12, such as shallow
trench isolation (STI) or local oxidation of silicon (LOCOS), are
formed in semiconductor substrate 102 to separate devices.
Isolation features 12 are formed to define and electrically isolate
various active regions as shown in FIG. 1. For example, isolation
features 12 may define a region for a complementary metal oxide
semiconductor (CMOS) device, a region for a core n-type MOS (NMOS)
device, a region for a core p-type MOS (PMOS) device, and other
regions for various microelectronic devices utilized in integrated
circuits. It is understood that several processes disclosed below
form corresponding features in some other active regions on
semiconductor substrate 102 for some other types of devices.
Isolation features 12 may comprise silicon oxide (SiOx), silicon
nitride (SiN), silicon oxynitride (SiON), an air gap, other
suitable materials, or combinations thereof.
[0014] Subsequently, a first doped region 13 is formed in
semiconductor substrate 12. Moreover, a second doped region 14 is
formed in semiconductor substrate 12 adjacent to some isolation
features 12. First doped region 13 and second doped region 14 can
be a source region or a drain region for PMOS, NMOS or CMOS
transistors. First doped region 13 and second doped region 14
comprise highly concentrated dopants, and are formed as p-type
regions with boron or n-type region with phosphorus. First doped
region 13 and second doped region 14 may be formed by various
processes, for example, thermal diffusion process. First doped
region 13 and second doped region 14 may be formed by a plurality
of operations, whether now known or to be developed, such as
growing a sacrificial oxide on semiconductor substrate 102, opening
a pattern for a location(s) in first doped region 13 or second
doped region 14, implanting impurities and annealing.
[0015] In some embodiments, semiconductor substrate 102 may include
various well regions (not shown) depending on design specifications
as known in the art. The well regions are formed in a p-well
structure, an n-well structure or a twin well structure. The doping
concentration in those well regions is less than first doped region
13 or second doped region 14. The p-well structure is formed with
p-type dopants to surround n-type first doped region 13 or n-type
second doped region 14. Alternatively, the n-well structure is
formed with n-type dopants to surround p-type first region 13 or
second doped region 14.
[0016] In FIG. 1B, an inter-layer dielectric (ILD) layer 104 is
formed on semiconductor substrate 102. ILD layer 104 includes parts
of MOS transistors, such as a gate structure 15, first sidewall
spacer 18, and second sidewall spacer 19 and conductive plugs 21
and 22.
[0017] Gate structure 15 is disposed on semiconductor substrate
102. Gate structure 15 may include a gate dielectric 16 disposed on
semiconductor substrate 102 and a gate electrode 17 disposed on
gate dielectric 16.
[0018] Gate dielectric 16, which is a layer on semiconductor
substrate 102, may include a silicon oxide layer. Alternatively,
gate dielectric 16 may optionally include a high-k dielectric
material, silicon oxide, silicon nitride, silicon oxynitride, other
suitable materials, or combinations thereof. The high-k material
may be selected from metal oxides, metal nitrides, metal silicates,
transition metal-oxides, transition metal-nitrides, transition
metal-silicates, oxynitride of metals, metal aluminates, zirconium
silicate, zirconium aluminate, hafnium oxide, or combinations
thereof. Examples of high-k dielectric material includes HfO.sub.2,
HfSiO, HfSiON, HfzrO, LaO, BazrO, HfLaO, HfSiO, LaSiO, AlSiO,
HfTaO, HfTiO, zirconium oxide, aluminum oxide, other suitable
high-k dielectric materials, and/or combinations thereof. In some
embodiments, gate dielectric 16 may have a multilayer structure
such as one layer of silicon oxide and another layer of high k
material. Gate dielectric 16 may be formed over an interfacial
layer by any suitable process.
[0019] Gate electrode 17 is disposed on gate dielectric 16. Gate
electrode 17 includes conductive material, such as aluminum,
copper, titanium, tantalum, tungsten, molybdenum, tantalum nitride,
TiN, WN, TiAl, TiAlN, TaCN, TaC, TaSiN, metal alloys, other
suitable materials, and/or combinations thereof. In some
embodiments, heavily doped amorphous silicon or polysilicon is
alternatively used. In that case a highly concentrated dopant such
as boron or phosphorus is utilized to form gate electrode 17. In
some embodiments, a silicon layer is used as gate material for gate
structure 15. A silicide layer (not shown) is formed on gate
electrode layer 17 by reacting silicon with conductive material
such as tungsten, Ti, Pt, Ta, Nb, Hf, Mo, or other suitable
metal.
[0020] Gate structure 15 has a first sidewall spacer 18 of gate
structure 15 and a second sidewall spacer 19 disposed opposite to
first sidewall spacer 18 of gate structure 15. First sidewall
spacer 18 and second sidewall spacer 19 are formed by dielectric
material such as silicon nitride or silicon oxide. First sidewall
space 18 and second sidewall spacer 19 may be formed in different
shapes in the upper portions or slopes. First sidewall spacer 18
and second sidewall spacer 19 may be formed by deposition of thin
film, such as silicon nitride, on gate structure 15 and
semiconductor substrate 12. Then an etching process is used to
remove the residue film material on the surface of semiconductor
substrate 12, leaving first sidewall spacer 18 and second sidewall
19.
[0021] Referring to FIG. 1B, ILD layer 104 further comprises
conductive plugs 21 and conductive plug 22. Conductive plug 21 may
be formed atop first doped region 13. Conductive plug 21 is
electrically coupling first doped region 13 with conductive
materials of overlying layers in semiconductor device 100.
Similarly, conductive plug 22 is electrically coupling second doped
region 14 with conductive materials of overlying layers in
semiconductor device 100. Conductive plugs 21 and 22 are formed
with electrically conductive materials, such as aluminum, copper,
tungsten, or other suitable metal. Conductive plugs 21 and 22 may
be formed by a suitable process such as low pressure chemical
vaporization deposition (LPCVD) or sputtering.
[0022] In some embodiments, a diffusion barrier layer (not shown)
is formed between conductive plugs 21 and 22 and semiconductor
substrate 102. For example, titanium, titanium nitride or
tungsten-tungsten can be used in forming the diffusion barrier
layer. The diffusion barrier layer may be formed by sputtering, CVD
or other suitable process.
[0023] ILD 104 also includes dielectric materials for electrically
isolating among components in ILD layer 104, and between ILD 104
and semiconductor substrate 102. A suitable process may be utilized
for forming the dielectric materials, such as deposition. Then a
planarization process is applied to ILD layer 104 for further
processes.
[0024] Referring to FIG. 1B, a dielectric layer 105 is disposed on
ILD layer 104. Dielectric layer 105 includes materials such as
silicon oxide, silicon nitride (SiN), silicon oxynitride, silicon
oxycarbide (SiOC), silicon carbide, fluorinated silicon oxide
(SiOF), carbon-doped silicon oxide (e.g., SiOCH), spin-on glass
(SOG), amorphous fluorinated carbon, fluorinated silica glass
(FSG), polyimide, BCB (bis-benzocyclobutenes), non-porous
materials, porous materials, and/or combinations thereof. In some
embodiments, Dielectric layer 105 includes a high density plasma
(HDP) dielectric material (e.g., HDP oxide) and/or a high aspect
ratio process (HARP) dielectric material (e.g., HARP oxide). In
some embodiments, Dielectric layer 105 is a planarized dielectric
film.
[0025] Dielectric layer 105 is formed by a suitable deposition
process, which may include chemical vapor deposition (CVD),
physical vapor deposition (PVD), ionized PVD (IPVD) and atomic
layer deposition (ALD). Additionally, other processes include high
density plasma CVD (HDPCVD), metal organic CVD (MOCVD), remote
plasma CVD (RPCVD), plasma enhanced CVD (PECVD), LPCVD, thermal
oxidation, UV-ozone oxidation, epitaxial growth methods (e.g.,
selective epitaxy growth), sputtering, plating, spin-on coating,
other suitable methods, and/or combinations thereof. In an
embodiment, dielectric layer 105 has a suitable range of thickness
from about 100 .ANG. to about 2000 .ANG..
[0026] In FIG. 1C, a trench 107 and a recess 108 are formed by a
suitable etching process on dielectric layer 105 to form patterned
dielectric layer 106. Recess 108 may include a stacked trench and
via structure. In some embodiments, a layer of photoresist is
formed over dielectric layer 105 by a suitable process, for
example, lithography or other alternatives, and patterned to form a
photoresist feature by a proper photolithography patterning method.
A photolithography process may also be implemented or replaced by
other proper methods such as maskless photolithography,
electron-beam writing, ion-beam writing, and/or molecular imprint.
In some embodiments, a photolithography process may include forming
a photoresist layer over dielectric layer 105, exposing photoresist
to a pattern, performing a post-exposure bake process, and forming
a masking element including the photoresist. In an embodiment, a
dual damascene technology is utilized where an intermediate etch
stop layer may be formed as hard mask for the stacked trench-via
structure of recess 108.
[0027] Subsequently, trench 107 and recess 108 may then be etched
using reactive ion etching (RIE) processes and/or other etching
processes. An etching process may include dry etching, wet etching,
and/or other etching methods (e.g., reactive ion etching). The
etching process may also be either purely chemical (plasma
etching), purely physical (ion milling), and/or combinations
thereof.
[0028] A dry etching process may be implemented in an etching
chamber. The thickness of different features may be controlled by
adjusting some process parameters including a radio frequency (RF)
source power, a bias power, electrode size, a pressure, a flow
rate, etching duration, a wafer temperature, other suitable process
parameters, and/or combinations thereof. A dry etching process may
implement an oxygen-containing gas, fluorine-containing gas (e.g.,
CF.sub.4, SF.sub.6, CH.sub.2F.sub.2, CHF.sub.3, and/or
C.sub.2F.sub.6), chlorine-containing gas (e.g., Cl.sub.2,
CHCl.sub.3, CCl.sub.4, and/or BCl.sub.3), bromine-containing gas
(e.g., HBr, He and/or CHBr.sub.3), iodine-containing gas, other
suitable gases and/or plasmas, and/or combinations thereof. In some
embodiments, the dry etching process utilizes an O.sub.2 plasma
treatment and/or an O.sub.2/N.sub.2 plasma treatment. Further, the
dry etching process may be performed for a suitable duration.
[0029] A wet etching process may utilize a hydrofluoric acid (HF)
solution for a HF dipping process. In some embodiments, a wet
etching process may apply a diluted hydrofluoric acid to an
intermediate semiconductor structure. In some embodiments, the wet
etching process includes exposing to a hydroxide solution
containing ammonium hydroxide, diluted HF, deionized water, and/or
other suitable etchant solutions.
[0030] After trench 107 and recess 108 are formed on patterned
dielectric layer 106, the photoresist may be stripped thereafter.
Subsequently, a diffusion barrier layer (not shown) may be
optionally formed on the bottom and sidewalls of trench 107 and
recess 108. A typical diffusion barrier metal or alloy includes
tantalum, nickel, hafnium, niobium, zirconium, vanadium, tungsten,
nichrome, and titanium tungdsten. In addition, conductive ceramics
is also considered, such as indium oxide, copper silicide, tungsten
nitride, and titanium nitride. A suitable deposition process for
forming the diffusion barrier layer as previously discussed can be
used, such as CVD, ALD and PVD. The diffusion barrier layer has a
thickness from about 20 .ANG. to about 200 .ANG.. It is understood,
however, that the dimensions recited throughout the present
disclosure will scale due to the utilized manufacturing
techniques.
[0031] FIG. 1D is a step of filling conductive material into trench
107 and recess 108. A conductive interconnect 112 and a conductive
interconnect 114 are then formed in trench 107 and recess 108,
respectively. Conductive interconnect 112 is formed to electrically
couple features in patterned dielectric layer 106. Similarly,
conductive interconnect 114 is formed in recess 108 to electrically
connect underlying layers. In some embodiments, conductive
interconnect 112 and conductive interconnect 114 are configured to
couple gate structure 15 with an input/output (I/O) region (not
shown) over conductive interconnect 112 and conductive interconnect
114. The conductive material for conductive interconnect 112 and
conductive interconnect 114 includes copper, aluminum or other
suitable materials.
[0032] In an embodiment, before the formation of conductive
interconnects 112 and conductive interconnect 114, a seed layer is
optionally formed on the walls of trench 107 and recess 108.
Typical materials for the seed layer include Pd or other compounds
of polymers and organic materials. The seed layer may be formed by
deposition through a suitable process such as PVD.
[0033] After conductive interconnects 112 and 114 are formed, a
suitable planarization process is used. In some embodiments,
patterned dielectric layer 106, and conductive interconnects 112
and 114 are planarized. Additionally, dielectric layer 106,
conductive interconnects 112 and 114 are made coplanar to
facilitate subsequent processes. A planarization process may be a
chemical mechanical planarization (CMP) operation.
[0034] Referring to FIG. 1E, a conductive layer 110 is deposited on
conductive interconnect 112 and conductive interconnect 114. In
some embodiments, conductive layer 110 is formed between conductive
interconnects 112 or 114 and overlying layers, such as dielectric
layers. Conductive layer 110 is used to prevent conductive material
in conductive interconnect 112 and conductive interconnect 114,
such as copper, from diffusing into surrounding dielectric
materials. Conductive layer 110 is formed with conductive materials
such as cobalt, nickel, tungsten, molybdenum, titanium, platinum
tantalum, other suitable material, and/or combinations thereof.
[0035] Conductive layer 110 has a thickness from about 10 .ANG. to
about 100 .ANG.. A suitable deposition process for forming
conductive layer 110 includes CVD, ALD and other suitable
processes. In some embodiments, a deposition process may perform
selective deposition of conductive layer 110 onto the surface of
the openings of conductive interconnect 112 and conductive
interconnect 114 in order for electrically insulating between
conductive interconnect 112 and conductive interconnect 114. Also,
the selective deposition provides to insulate conductive
interconnect 112 and conductive interconnect 114 and other
conductive interconnects in patterned dielectric layer 106.
[0036] Referring to FIG. 1F, a silicon layer 116 is deposited over
conductive layer 110. In one embodiment, silicon layer 116 is
covering patterned dielectric layer 106. Silicon layer 116 has a
thickness of from about 10 .ANG. to about 100 .ANG.. A suitable
deposition process includes CVD using silane (SiH.sub.4) or
disilane (Si.sub.2H.sub.6) as a silicon precursor. Alternatively,
silicon layer 116 can be formed by a PVD process by using silicon
as target.
[0037] Referring to FIG. 1G, a metal silicide layer 118 is formed
at the interface of silicon layer 116 and conductive layer 110. In
an embodiment, silicon layer 116 is disposed on the periphery of
metal silicide layer 118. Silicon layer 116 provides silicon for
forming metal silicide layer 118. Metal silicide layer 118 is
formed by reacting silicon atoms from silicon layer 116 with the
metal included in conductive layer 110. Metal silicide layer 118
may include Co.sub.2Si, CoSi, CoSi.sub.2, NiSi, NiSi.sub.2,
WSi.sub.2, MoSi.sub.2, TiSi.sub.2, PtSi, TaSi.sub.2, other suitable
materials, and/or combinations thereof.
[0038] Metal silicide layer 118 is formed over conductive
interconnects 112 and 114. In one embodiment, when the conductive
material in contact with conductive layer 110 is consumed in
forming metal silicide layer 118, metal silicide layer 118 would be
formed on conductive interconnects 112 and 114. In another
embodiment where part of conductive layer 110 is disposed on
conductive interconnects 112 and 114, metal silicide layer 118 is
formed between silicon layer 116 and conductive layer 110. In one
embodiment, metal silicide layer 118 is disposed over the surfaces
of conductive interconnects 112 and 114.
[0039] Referring FIG. 1H, a second dielectric layer 220 is formed
on metal silicide layer 118. In one embodiment, second dielectric
layer 220 is deposited on patterned dielectric layer 106. Second
dielectric layer 220 may be deposited on silicon layer 116. In one
embodiment, the material used for forming second dielectric layer
220 is the same as that for forming patterned dielectric layer 106.
In another embodiment, when both the silicon of silicon layer 116
and the silicon-contacting metal in conductive layer 110 are
consumed, metal silicide layer 118 may be formed between second
dielectric layer 220 and conductive interconnects 112 and 114.
Second dielectric layer 220 has a thickness of from about 100 .ANG.
to about 2000 .ANG.. In one embodiment, the ratio of thickness
between second dielectric layer 220 and metal silicide layer 118 is
between 1 and 200.
[0040] In an embodiment, the step of forming metal silicide layer
118 to be a silicide form of the conductive material of conductive
layer 110 is performed during the formation of the second
dielectric layer 220 on silicon layer 116.
[0041] In an embodiment, silicon layer 116 has a coefficient of
thermal expansion (CTE) of from about 2 ppm/.degree. C. to about
3.3 ppm/.degree. C., for example 2.6 ppm/.degree. C. In another
embodiment, second dielectric layer 220 has a CTE of from about 0.1
ppm/.degree. C. to about 5 ppm/.degree. C., for example 1
ppm/.degree. C. In some embodiments, conductive layer 110 has a CTE
of from about 4.5 ppm/.degree. C. to about 9 ppm/.degree. C., for
example 6.3 ppm/.degree. C., or from about 13 ppm/.degree. C. to
about 14 ppm/.degree. C., for example 13.5 ppm/.degree. C. In an
embodiment, conductive interconnects 112 or 114 has a CTE of from
about 16 ppm/.degree. C. to about 24 ppm/.degree. C. In an
embodiment, metal silicide layer 118 has a CTE of from about 6.5
ppm/.degree. C. to about 9.5 ppm/.degree. C., or from about 9.5
ppm/.degree. C. to about 15 ppm/.degree. C.
[0042] In some examples, the CTE of conductive interconnect 112 or
conductive interconnect 114 is larger than the CTE of metal
silicide layer 118. In some examples, the CTE of metal silicide
layer 118 is larger than the CTE of silicon layer 116. In some
examples, the CTE of metal silicide layer 118 is larger than the
CTE of second dielectric layer 220. In some examples, the CTE of
metal silicide layer 118 is larger than the CTE of patterned
dielectric layer 106.
[0043] In some examples, the ratio of the CTE between metal
silicide layer 118 and second dielectric layer 220 is larger than
the ratio of CTE between metal silicide layer 118 and silicon layer
116. In some examples, the ratio of the CTE between conductive
interconnect 112 and second dielectric layer 220 is larger than the
ratio of CTE between conductive interconnect 112 and silicon layer
116.
[0044] In one embodiment, metal silicide layer 118 can be formed
in-situ with second dielectric layer 220. In other words, the
formation of both metal silicide layer 118 and second dielectric
layer 220 can be performed within the same chamber or within one
platform without breaking vacuum. Alternatively, second dielectric
layer 220 is formed in one chamber by breaking vacuum after metal
silicide layer 118 is formed in another chamber.
[0045] In conventional practices, it is required to form conductive
layer 110 and second dielectric layer 220 in different chambers,
and thus a process sequence with breaking vacuum is inevitable.
When conductive layer 110 is formed and moved out of the vacuum
condition, it is found that a metal oxide layer may be formed
before second dielectric layer 220 is formed on conductive layer
110. The metal oxide layer is formed by reacting oxygen in the
atmosphere with conductive layer 110. It is believed that the metal
oxide layer may lead to defects such as bubbles or peeling. The
adhesion between conductive layer 110 and second dielectric layer
220 is thus degraded. The device integrity and reliability would be
impacted due to peeling or bubbles. On the contrary, in the present
disclosure, silicon layer 116 is formed on conductive layer 110
before conductive layer 110 is exposed to oxygen. That can prevent
formation of a metal oxide layer. The performance of adhesion
between conductive layer 110 and second dielectric layer 220 is
thus improved.
[0046] FIGS. 1I-IJ are cross sectional views of a semiconductor
device manufacturing processes, in accordance with some
embodiments. FIGS. 1I-1J show alternative operation steps
subsequent to the operation step illustrated in FIG. 1F. Referring
to FIG. 1I, second dielectric layer 220 is deposited on silicon
layer 116 before metal silicide layer 118 is formed. In an
embodiment, second dielectric layer 220 is covering part of
patterned dielectric layer 106. In another embodiment, silicon
layer 116 is disposed between patterned dielectric layer 106 and
second dielectric layer 220. Additionally, second dielectric layer
220 is disposed over conductive layer 110. In one embodiment,
conductive layer 110 is disposed between pattern dielectric layer
106 and second dielectric layer 220.
[0047] Referring to FIG. 1J, metal silicide layer 118 is formed
between second dielectric layer 220 and conductive interconnect 114
or conductive interconnect 112. In some embodiments, a suitable
process for forming metal silicide layer 118 includes an annealing
process, such as heating semiconductor substrate 102.
[0048] In one embodiment, metal silicide layer 118 is formed on
conductive layer 110. In another embodiment, metal silicide layer
118 is formed at the surface between silicon layer 116 and
conductive layer 110. In yet another embodiment, metal silicide
layer 118 is formed between silicon layer 116 and conductive
interconnect 112 and conductive interconnect 114.
[0049] FIGS. 1K-IL are cross sectional views of a semiconductor
device manufacturing processes, in accordance with some
embodiments. FIGS. 1K-1L show another alternative operation steps
subsequent to the operation step illustrated in FIG. 1E. Referring
to FIG. 1K, part of second dielectric layer 220 is formed on
patterned dielectric layer 106. In that case second dielectric
layer 220 is utilized, instead of the formation of silicon layer
116 as illustrated in FIG. 1F, with a view to keeping oxygen from
reacting with metal in conductive layer 110. In an embodiment,
second dielectric layer 220 is covering portions of patterned
dielectric layer 106. Second dielectric layer 220 is disposed over
conductive layer 110. In another embodiment, conductive layer 110
is disposed between patterned dielectric layer 106 and second
dielectric layer 220.
[0050] During operation illustrated in FIG. 1K where part of second
dielectric layer 220 is formed, the formation of metal silicide
layer 118 is also started on the surface of conductive layer 110.
With second dielectric layer 220, the silicon in second dielectric
layer 220 is transferred into metal silicide layer 118 during the
formation of second dielectric layer 220. In one embodiment, metal
silicide layer 118 is formed between second dielectric layer 220
and conductive layer 110.
[0051] Referring to FIGS. 1E, and 1K, second dielectric layer 220
and metal silicide layer 118 are formed in-situ with conductive
layer 110 without breaking vacuum. In addition, the step of forming
metal silicide layer 118 to be a silicide form of the conductive
material of conductive layer 110 is performed during the formation
of second dielectric layer 220.
[0052] Referring to FIG. 1L, a full second dielectric layer 220 and
a full metal silicide layer 118 are formed.
[0053] FIG. 2 shows a schematic of a semiconductor manufacturing
platform 200, in accordance with some embodiments. Semiconductor
manufacturing platform 200 includes a first tool 202, a second tool
204, and a channel 206.
[0054] First tool 202 includes a first chamber 202 to accommodate a
semiconductor wafer for conducting processes. First tool 202 is
configured to perform semiconductor manufacturing operations, such
as those illustrated in FIGS. 1A-1L, on the semiconductor wafer.
First chamber 202 is shown for illustration, and different
configurations with more chambers are alternatively used in first
tool 202. Similarly, second tool 204 includes a second chamber 204
to accommodate a semiconductor wafer. In one embodiment, a
manufacturing process performed in first tool 202 may be different
from the manufacturing process performed in second tool 204.
[0055] Channel 206 is disposed between first tool 202 and second
tool 204. Channel 206 includes a robot 208, configured to move
semiconductor wafers between first tool 202 and second tool 204. In
one embodiment, channel 206 is configured under a low pressure or
vacuum condition. The pressure of channel 206 may be kept under 0.1
torr. When two or more different processes are performed in first
tool 202 and second tool 204 in sequence, channel 206 provides a
virtual vacuum tunnel through which contamination due to undesired
reactants, such as oxygen, can be controlled. For example, the
operations in FIGS. 1E and 1K performed in sequence may be
conducted in first tool 202 and second tool 204 separately. The
sequential operations require a working environment without
breaking vacuum in order to prevent the formation of a metal oxide
layer on conductive layer 110. In that case channel 206 can be
leveraged in moving semiconductor wafer without breaking vacuum
after conductive layer 110 is formed.
[0056] FIG. 3 is a flow diagram showing a semiconductor
manufacturing process, in accordance of some embodiments. In
operation 310, semiconductor substrate 102 of semiconductor device
100 is provided. In operation 320, at least one transistor is
formed on semiconductor substrate 102. The transistor includes a
gate structure, a source region and a drain region.
[0057] In operation 330, dielectric layer 105 is etched to form
trench 107 and recess 108 such that patterned dielectric layer 106
is formed over the gate structure of semiconductor device 100.
Subsequently, in operation 340, conductive interconnect 112 and 114
are formed in trench 107 and recess 108, respectively, in patterned
dielectric layer 106. A surface of conductive interconnect 112 or
conductive interconnect 114 uncovered by the patterned dielectric
layer 106 is exposed. In an embodiment, conductive interconnect 112
and conductive interconnect 114 include a conductive material such
as copper or aluminum.
[0058] In operation 350, conductive layer 110 having a conductive
material, such as cobalt, nickel, tungsten, molybdenum, titanium,
platinum and tantalum, is formed on the exposed surface of
conductive interconnect 112 or conductive interconnect 114. In one
embodiment, the conductive material is formed over the exposed
surface.
[0059] In operation 360, silicon layer 116 is formed on conductive
layer 110. Silicon layer 116 provides the silicon for forming metal
silicide layer 118. In operation 370, metal silicide layer 118 is
formed to be a silicide form of the conductive material for
conductive interconnect 112 or conductive interconnect 114. Metal
silicide layer 118 is formed by reacting the conductive material
with silicon. In an embodiment, metal silicide layer 118 is formed
by reacting the conductive material in conductive layer 110 and the
silicon through a process of, for example, heating the
substrate.
[0060] In operation 380, second dielectric layer 220 is formed on
silicon layer 116. In one embodiment, second dielectric layer 220
is formed on patterned dielectric layer 106. In an embodiment, the
step of forming metal silicide layer 118 to be a silicide form of
the conductive material is performed during the formation of second
dielectric layer 220 on silicon layer 116.
[0061] FIG. 4 is a flow diagram showing a semiconductor
manufacturing process, in accordance of some embodiments. Referring
to FIG. 4, operations 310-360 are illustrated in operations 310-360
of FIG. 3. Following operation 360, in operation 410, second
dielectric layer 220 is formed on silicon layer 116. In operation
420, metal silicide layer 118 is formed between conductive layer
110 and second dielectric layer 220.
[0062] FIG. 5 is a flow diagram showing a semiconductor
manufacturing process, in accordance of some embodiment. Referring
to FIG. 5, operations 310-350 are illustrated in operations 310-350
of FIG. 3. Following operation 350, in operation 510, part of
second dielectric layer 220 is formed on silicon layer 116. In
operation 520, metal silicide layer 118 is formed between
conductive layer 110 and second dielectric layer 220. Metal
silicide layer 118 is formed during the formation of second
dielectric layer 220. In an embodiment, metal silicide layer 118 is
formed where the silicon is transferred into metal silicide layer
118 during the process of forming second dielectric layer 220 in
operation 510.
[0063] Some embodiments of the present disclosure provide a
semiconductor device including a dielectric layer over a gate
structure of the semiconductor device. A conductive interconnect is
configured to couple the gate structure with an I/O region over the
conductive interconnect. A metal silicide layer is disposed between
the conductive interconnect and the dielectric layer, and the metal
silicide is a silicide form of a metal different from the
conductive interconnect.
[0064] Some embodiments of the present disclosure provide a
semiconductor device including a first dielectric layer. A
conductive interconnect is disposed within the first dielectric
layer. A metal silicide layer is disposed over the conductive
interconnect. A silicon layer is disposed on the periphery of the
metal silicide layer, and a second dielectric layer disposed over
the metal silicide layer and the silicon layer.
[0065] Some embodiments of the present disclosure provide a method
for manufacturing a semiconductor device, which include providing a
substrate. The method also includes forming a gate structure on the
substrate. The method further includes forming a first dielectric
layer over the gate structure of the semiconductor device. In
addition, the method includes forming a conductive interconnect in
a trench of the first dielectric layer thereby exposing a surface
of the conductive interconnect uncovered by the first dielectric
layer. The method also includes forming a conductive material on
the exposed surface, and forming a metal silicide layer to be a
silicide form of the conductive material by reacting the conductive
material with silicon.
[0066] The foregoing outlines features of several embodiments so
that those skilled in the art may better understand the aspects of
the present disclosure. Those skilled in the art should appreciate
that they may readily use the present disclosure as a basis for
designing or modifying other processes and structures for carrying
out the same purposes and/or achieving the same advantages of the
embodiments introduced herein. Those skilled in the art should also
realize that such equivalent constructions do not depart from the
spirit and scope of the present disclosure, and that they may make
various changes, substitutions, and alterations herein without
departing from the spirit and scope of the present disclosure.
* * * * *