U.S. patent application number 14/918698 was filed with the patent office on 2016-09-15 for composite solder ball, semiconductor package using the same, semiconductor device using the same and manufacturing method thereof.
The applicant listed for this patent is MEDIATEK Inc.. Invention is credited to Tao Cheng, Wen-Sung Hsu, Shih-Chin Lin.
Application Number | 20160263709 14/918698 |
Document ID | / |
Family ID | 54476802 |
Filed Date | 2016-09-15 |
United States Patent
Application |
20160263709 |
Kind Code |
A1 |
Cheng; Tao ; et al. |
September 15, 2016 |
COMPOSITE SOLDER BALL, SEMICONDUCTOR PACKAGE USING THE SAME,
SEMICONDUCTOR DEVICE USING THE SAME AND MANUFACTURING METHOD
THEREOF
Abstract
A semiconductor package includes a first substrate, a second
substrate, a composite solder ball and a first semiconductor
component. The composite solder ball includes a core, an
encapsulating layer and a barrier layer. The composite solder ball
is disposed between the first substrate and the second substrate
for electrically connecting the first substrate and the second
substrate. The barrier layer is disposed between the core and the
encapsulating layer. Wherein a melting point of the barrier layer
is higher than a melting point of the core, the melting point of
the core is higher than a melting point of the encapsulating layer.
The first semiconductor component is disposed between the first
substrate and the second substrate.
Inventors: |
Cheng; Tao; (Zhubei City,
TW) ; Hsu; Wen-Sung; (Zhubei City, TW) ; Lin;
Shih-Chin; (Taoyuan City, TW) |
|
Applicant: |
Name |
City |
State |
Country |
Type |
MEDIATEK Inc. |
Hsin-Chu |
|
TW |
|
|
Family ID: |
54476802 |
Appl. No.: |
14/918698 |
Filed: |
October 21, 2015 |
Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
|
|
62132683 |
Mar 13, 2015 |
|
|
|
Current U.S.
Class: |
1/1 |
Current CPC
Class: |
H01L 24/73 20130101;
H01L 23/49866 20130101; H01L 2225/1023 20130101; B23K 35/264
20130101; H01L 23/49894 20130101; H01L 24/16 20130101; H01L
2225/1041 20130101; B23K 35/262 20130101; H01L 2225/1058 20130101;
B23K 35/0244 20130101; H01L 2224/13639 20130101; H01L 2224/81801
20130101; H01L 25/105 20130101; B23K 35/30 20130101; H01L 2224/131
20130101; H01L 24/32 20130101; H01L 2224/32225 20130101; H01L
2924/2076 20130101; B23K 35/26 20130101; H01L 23/49816 20130101;
H01L 2224/13111 20130101; H01L 2224/13647 20130101; H01L 2224/13561
20130101; H01L 2224/32225 20130101; H01L 2924/014 20130101; H01L
2224/16225 20130101; H01L 2924/00 20130101; H01L 24/81 20130101;
B23K 2101/40 20180801; H01L 24/13 20130101; H01L 2224/13113
20130101; H01L 2224/16227 20130101; H01L 2224/13014 20130101; H01L
2224/13582 20130101; H01L 2224/16225 20130101; H01L 2924/15331
20130101; H01L 23/49833 20130101; H01L 2924/014 20130101; H01L
2224/131 20130101; H01L 2224/13611 20130101; H01L 2224/73204
20130101; H01L 2224/73204 20130101; H01L 2924/1434 20130101 |
International
Class: |
B23K 35/02 20060101
B23K035/02; B23K 35/26 20060101 B23K035/26; B23K 35/30 20060101
B23K035/30; H01L 23/00 20060101 H01L023/00 |
Claims
1. A composite solder ball, comprising: a core; an encapsulating
layer; and a barrier layer disposed between the core and the
encapsulating layer; wherein a melting point of the barrier layer
is higher than a melting point of the core, the melting point of
the core is higher than a melting point of the encapsulating
layer.
2. The composite solder ball as claimed in claim 1, wherein the
encapsulating layer has an outer diameter ranging between 120
micrometers and 130 micrometers.
3. The composite solder ball as claimed in claim 1, wherein the
core is made of tin, bismuth or a combination thereof.
4. The composite solder ball as claimed in claim 1, wherein the
core is made of a material in absence of copper.
5. The composite solder ball as claimed in claim 1, wherein the
encapsulating layer is made of an alloy material including at least
two of tin, silver and copper.
6. A semiconductor package, comprising: a first substrate; a second
substrate; a composite solder ball as claimed in claim 1, disposed
between the first substrate and the second substrate for
electrically connecting the first substrate and the second
substrate; and a first semiconductor component, disposed between
the first substrate and the second substrate.
7. The semiconductor package as claimed in claim 6, wherein the
encapsulating layer has an outer diameter ranging between 120
micrometers and 130 micrometers.
8. The semiconductor package as claimed in claim 6, wherein the
core is made of tin, bismuth or a combination thereof.
9. The semiconductor package as claimed in claim 6, wherein the
core is made of a material in absence of copper.
10. The semiconductor package as claimed in claim 6, wherein the
encapsulating layer is made of an alloy material including at least
two of tin, silver and copper.
11. The semiconductor package as claimed in claim 1, wherein the
second substrate is an interposer.
12. A semiconductor device, comprising: a semiconductor package as
claimed in claim 6; and a second semiconductor component, disposed
on the second substrate of the semiconductor package.
13. The semiconductor device as claimed in claim 12, wherein the
encapsulating layer has an outer diameter ranging between 120
micrometers and 130 micrometers.
14. The semiconductor device as claimed in claim 12, wherein the
core is made of tin, bismuth or a combination thereof.
15. The semiconductor device as claimed in claim 12, wherein the
core is made of a material in absence of copper.
16. The semiconductor device as claimed in claim 12, wherein the
encapsulating layer is made of an alloy material including at least
two of tin, silver and copper.
17. The semiconductor device as claimed in claim 12, wherein the
second substrate is an interposer.
18. The semiconductor device as claimed in claim 12, wherein the
second semiconductor component is a memory device.
19. A manufacturing method of a semiconductor package, comprising:
providing a first substrate; disposing a first semiconductor
component on the first substrate; providing a second substrate;
disposing a plurality of composite solder balls on the second
substrate; connecting the first substrate and the second substrate
by way of the composite solder balls facing the first substrate,
wherein the composite solder balls are disposed between the first
substrate and the second substrate.
20. The manufacturing method as claimed in claim 19, wherein the
encapsulating layer has an outer diameter ranging between 120
micrometers and 130 micrometers.
21. The manufacturing method as claimed in claim 19, wherein the
core is made of tin, bismuth or a combination thereof.
22. The manufacturing method as claimed in claim 19, wherein the
core is made of a material in absence of copper.
23. The manufacturing method as claimed in claim 19, wherein the
encapsulating layer is made of an alloy material including at least
two of tin, silver and copper.
24. The manufacturing method as claimed in claim 19, wherein the
second substrate is an interposer.
Description
[0001] This application claims the benefit of U.S. Provisional
application Ser. No. 62/132,683, filed Mar. 13, 2015, the
disclosure of which is incorporated by reference herein in its
entirety.
FIELD OF THE INVENTION
[0002] The invention relates to a solder ball, a semiconductor
package using the same, a semiconductor device using the same and a
manufacturing method thereof, and more particularly to a composite
solder ball, a semiconductor package using the same, a
semiconductor device using the same and a manufacturing method
thereof.
BACKGROUND OF THE INVENTION
[0003] In the electronics industry, high integration and multiple
functions with high performance become essential for new products.
And meanwhile, high integration may cause higher manufacturing
cost, since the manufacturing cost is in proportional to its size.
Therefore, demanding on miniaturization of integrated circuit (IC)
packages has become more and more critical.
[0004] Package-on-package (PoP) is now the fastest growing
semiconductor package technology since it is a cost-effective
solution to high-density system integration in a single package. In
a PoP structure, various packages are integrated in a single
semiconductor package to reduce the size. Accordingly, there exists
a need to provide a semiconductor package to overcomes, or at least
reduces the above-mentioned problems.
[0005] Therefore, it is important to increase the performance of
the 3D graphic processing circuit while reducing the consumption of
the electric power and extending the operating time of the mobile
device.
SUMMARY OF THE INVENTION
[0006] In one embodiment of the invention, a composite solder ball
is provided. The composite solder ball includes a core, an
encapsulating layer and a barrier layer. The barrier layer is
disposed between the core and the encapsulating layer. Wherein a
melting point of the barrier layer is higher than a melting point
of the core, the melting point of the core is higher than a melting
point of the encapsulating layer.
[0007] In another embodiment of the invention, a semiconductor
package is provided. The semiconductor package includes a first
substrate, a second substrate, a composite solder ball and a first
semiconductor component. The composite solder ball includes a core,
an encapsulating layer and a barrier layer. The composite solder
ball is disposed between the first substrate and the second
substrate for electrically connecting the first substrate and the
second substrate. The barrier layer is disposed between the core
and the encapsulating layer. Wherein a melting point of the barrier
layer is higher than a melting point of the core, the melting point
of the core is higher than a melting point of the encapsulating
layer. The first semiconductor component is disposed between the
first substrate and the second substrate.
[0008] In another embodiment of the invention, a semiconductor
device is provided. The semiconductor device includes a
semiconductor package and a second semiconductor component. The
second semiconductor component is disposed on the second substrate
of the semiconductor package. The semiconductor package includes a
first substrate, a second substrate, a composite solder ball and a
first semiconductor component. The composite solder ball includes a
core, an encapsulating layer and a barrier layer. The composite
solder ball is disposed between the first substrate and the second
substrate for electrically connecting the first substrate and the
second substrate. The barrier layer is disposed between the core
and the encapsulating layer. Wherein a melting point of the barrier
layer is higher than a melting point of the core, the melting point
of the core is higher than a melting point of the encapsulating
layer. The first semiconductor component is disposed between the
first substrate and the second substrate.
[0009] In another embodiment of the invention, a manufacturing
method of a semiconductor package is provided. The manufacturing
method includes the following steps. A first substrate is provided;
a first semiconductor component is disposed on the first substrate;
a second substrate is provided; a plurality of composite solder
balls are disposed on the second substrate; the first substrate is
connected to the second substrate by way of the composite solder
balls facing the first substrate, wherein the composite solder
balls are disposed between the first substrate and the second
substrate.
[0010] Numerous objects, features and advantages of the invention
will be readily apparent upon a reading of the following detailed
description of embodiments of the invention when taken in
conjunction with the accompanying drawings. However, the drawings
employed herein are for the purpose of descriptions and should not
be regarded as limiting.
BRIEF DESCRIPTION OF THE DRAWINGS
[0011] The above objects and advantages of the invention will
become more readily apparent to those ordinarily skilled in the art
after reviewing the following detailed description and accompanying
drawings, in which:
[0012] FIG. 1 illustrates a diagram of a semiconductor package
according to an embodiment of the invention;
[0013] FIG. 2 illustrates a diagram of a semiconductor package
according to another embodiment of the invention;
[0014] FIG. 3 illustrates a diagram of a semiconductor device
according to another embodiment of the invention;
[0015] FIGS. 4A to 4F illustrate manufacturing processes of the
semiconductor package of FIG. 1; and
[0016] FIG. 5 illustrates a manufacturing process of the
semiconductor package of FIG. 2.
DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS
[0017] FIG. 1 illustrates a diagram of a semiconductor package 100
according to an embodiment of the invention. The semiconductor
package 100 includes a first substrate 110, a second substrate 120,
a first semiconductor component 130, a plurality composite solder
balls 140, a package body 150 and a plurality of conductive
contacts 160.
[0018] The first substrate 110 is, for example, a multi-layered
coreless substrate. The first substrate 110 includes a plurality of
pads 111 for electrically connected to the composite solder balls
140. The second substrate 120 is, for example, an interposer.
[0019] The first semiconductor component 130 may be disposed on and
electrically connected to the first substrate 110 through the
composite solder balls 140. The second substrate 120 may be
electrically connected to the first semiconductor component 130
through the composite solder balls 140 and the second substrate
120.
[0020] In the present embodiment, the first semiconductor component
130 is coupled to an upper surface 110u of the first substrate 110
in a "face-down" orientation and electrically connected to the
first substrate 110 via a plurality of conductive contacts 131.
This configuration is sometimes referred to as "flip-chip". The
conductive contact 131 may be solder ball, conductive pillar,
etc.
[0021] In other embodiments, the first semiconductor component 130
may be coupled to the first substrate 110 in a "face-up"
orientation, and electrically connected to the first substrate 110
via a plurality of conductive bond wires (not shown). The first
semiconductor component 130 may be an active chip or a passive
component, such as a resistor, an inductor or a capacitor. In
another embodiment, the number of the first semiconductor component
130 may be several.
[0022] Each composite solder ball 140 includes a core 141, a
barrier layer 142 and an encapsulating layer 143. The barrier layer
142 is disposed between the core 141 and the encapsulating layer
143. For example, the barrier layer 142 directly or indirectly
encapsulates the core 141, and the encapsulating layer 143 directly
or indirectly encapsulates the barrier layer 142.
[0023] The melting point of the core 141 may be higher than the
melting point of the encapsulating layer 143, such that the core
141 may be prevented from melting and deforming during reflow
process, Therefore, it is possible to prevent an outer diameter D1
of the core 141 from expanding, and accordingly the minimum
interval P1 between adjacent two composite solder balls 140 do not
be narrowed, such that adjacent two composite solder balls 140 may
be prevented from being electrically short to each other, and the
density of the composite solder balls 140 may be increased.
[0024] In one embodiment, the core 141 may be made of a material
including tin, bismuth or a combination thereof. In another
embodiment, the core 141 may be made of a material in absence of
copper. As a result, the outer diameter D1 of the core 141 may be
reduced, such that the outer diameter D2 of the encapsulating layer
143 encapsulating the core 141 may be reduced and/or the thickness
of the semiconductor package 100 may be reduced. In one embodiment,
after reflow, the encapsulating layer 143 has the outer diameter D2
ranging between 120 .mu.m and 130 .mu.m.
[0025] In addition, the melting point of the barrier layer 142 may
be higher than the melting point of the core 141, such that the
barrier layer 142 can restrict the outer diameter D1 of the core
141 and accordingly can prevent the core 141 from over-deforming
during reflow process. Furthermore, since the barrier layer 142 can
restrict the outer diameter D1 of the core 141, the core 141 may be
made a material having hardness and/or strength lower than that of
the barrier layer 142. For example, the barrier layer 142 may be
made of a material including nickel whose hardness and/or strength
is larger than the core 141.
[0026] In addition, the encapsulating layer 143 may be pre-solder.
Under such design, the semiconductor package 100 may omit extra
pre-solder which is pre-applied on the first substrate 110 and/or
the second substrate 120. In one embodiment, the encapsulating
layer 143 may be made of an alloy material including at least two
of tin, silver and copper.
[0027] The package body 150 is formed between the first substrate
110 and the second substrate 120 and encapsulates the first
semiconductor component 130 and the composite solder balls 140.
[0028] The package body 150 can include, for example, a
Novolac-based resin, an epoxy-based resin, a silicone-based resin,
or another suitable encapsulant. Suitable fillers also can be
included, such as powdered SiO2.
[0029] The conductive contacts 160 are disposed on a bottom surface
110b of the first substrate 110. The semiconductor package 100 is
disposed on and electrically connected to an exterior circuit, such
as a circuit board. The conductive contact 160 may be solder ball,
conductive pillar, etc.
[0030] FIG. 2 illustrates a diagram of a semiconductor package 200
according to another embodiment of the invention. The semiconductor
package 200 includes the first substrate 110, the second substrate
120, the first semiconductor component 130, the composite solder
balls 140, an under fill 250 and a plurality of conductive contacts
160.
[0031] The under fill 250 is formed between the first semiconductor
component 130 and the first substrate 110 and encapsulates a
plurality of conductive contacts 131 of the first semiconductor
component 130.
[0032] In the present embodiment, the semiconductor package 200
omits the package body 150. In another embodiment, the
semiconductor package 200 may further includes the package body 150
encapsulating the first semiconductor component 130, the composite
solder balls 140 and the under fill 250.
[0033] FIG. 3 illustrates a diagram of a semiconductor device 300
according to another embodiment of the invention. The semiconductor
device 300 includes a semiconductor package 100 and a second
semiconductor component 360. The second semiconductor component 360
may be, for example, a memory, a semiconductor component rather
than memory, another semiconductor package, active component,
passive component, etc. The second semiconductor component 360 is
disposed on and electrically connected to the second substrate 120
of the semiconductor package 100 through a plurality of conductive
contacts 361. The conductive contact 361 may be solder ball,
pillar, etc.
[0034] FIGS. 4A to 4F illustrate manufacturing processes of the
semiconductor package 100 of FIG. 1.
[0035] Referring to FIG. 4A, the first substrate 110 is
provided.
[0036] Referring to FIG. 4B, the first semiconductor component 130
is disposed on the first substrate 110 using, for example, surface
mount technology (SMT).
[0037] Referring to FIG. 4C, the second substrate 120 is
provided.
[0038] Referring to FIG. 4D, a plurality of composite solder balls
140 are disposed on the second substrate 120 using, for example,
ball mounting technology. Each composite solder ball 140 includes
the core 141, the barrier layer 142 and the encapsulating layer
143. The barrier layer 142 is disposed between the core 141 and the
encapsulating layer 143. For example, the barrier layer 142
directly or indirectly encapsulates the core 141, and the
encapsulating layer 143 directly or indirectly encapsulates the
barrier layer 142.
[0039] Referring to FIG. 4E, the first substrate 110 is connected
to the second substrate 120 by way of the composite solder balls
140 facing the first substrate 110, wherein the composite solder
balls 140 are disposed between the first substrate 110 and the
second substrate 120 for electrically connecting the first
substrate 110 and the second substrate 120.
[0040] After reflow process, the encapsulating layer 143 of the
composite solder balls 140 is melted to solder with the pads 111 of
the first substrate 110. Since the melting point of the core 141 is
higher than the melting point of the encapsulating layer 143, the
reflowing temperature may be sufficiently high. For example, the
reflowing temperature may reach 245.degree. C. or higher, such that
the encapsulating layer 143 can firm formed on the pads 111 of the
first substrate 110, and the core 141 may be prevented from melting
and/or over-deforming. In another embodiment, the reflowing
temperature may approach or exceed the melting point of the core
141.
[0041] In addition, the melting point of the barrier layer 142 is
higher than the melting point of the core 141, such that, during
reflow process, the barrier layer 142 can restrict the outer
diameter D1 of the core 141 and accordingly can prevent the core
141 from over-deforming.
[0042] Referring to FIG. 4F, the package body 150 is disposed over
the upper surface 110u of the first substrate 110 and encapsulates
the first semiconductor component 130. The package body 150 can be
formed by various packaging technologies, such as, for example,
compression molding, injection molding, transfer molding or
dispensing technology.
[0043] Then, the conductive contacts 160 of FIG. 1 may be disposed
on the bottom surface of 110b of the first substrate 110 of FIG. 1
so as to form the semiconductor package 100 as illustrated in FIG.
1.
[0044] FIG. 5 illustrates a manufacturing process of the
semiconductor package 200 of FIG. 2. The under fill 250 is formed
between the first substrate 110 and the first semiconductor
component 130 and encapsulates the conductive contacts 131 using,
for example, dispensing technology. In addition, the other
formation steps of the semiconductor package 200 are similar to the
corresponding steps of the semiconductor package 100 of FIG. 1, and
the similarities are not repeated here.
[0045] While the invention has been described in terms of what is
presently considered to be the most practical and preferred
embodiments, it is to be understood that the invention needs not be
limited to the disclosed embodiment. On the contrary, it is
intended to cover various modifications and similar arrangements
included within the spirit and scope of the appended claims which
are to be accorded with the broadest interpretation so as to
encompass all such modifications and similar structures.
* * * * *