U.S. patent application number 15/083690 was filed with the patent office on 2016-07-21 for iii-nitride transistor with solderable front metal.
The applicant listed for this patent is Infineon Technologies Americas Corp.. Invention is credited to Michael A. Briere, Chuan Cheah.
Application Number | 20160211337 15/083690 |
Document ID | / |
Family ID | 44369021 |
Filed Date | 2016-07-21 |
United States Patent
Application |
20160211337 |
Kind Code |
A1 |
Cheah; Chuan ; et
al. |
July 21, 2016 |
III-Nitride Transistor with Solderable Front Metal
Abstract
Some exemplary embodiments of a III-nitride power device
including a HEMT with multiple interconnect metal layers and a
solderable front metal structure using solder bars for external
circuit connections have been disclosed. The solderable front metal
structure may comprise a tri-metal such as TiNiAg, and may be
configured to expose source and drain contacts of the HEMT as
alternating elongated digits or bars. Additionally, a single
package may integrate multiple such HEMTs wherein the front metal
structures expose alternating interdigitated source and drain
contacts, which may be advantageous for DC-DC power conversion
circuit designs using III-nitride devices. By using solder bars for
external circuit connections, lateral conduction is enabled,
thereby advantageously reducing device Rdson.
Inventors: |
Cheah; Chuan; (Torrance,
CA) ; Briere; Michael A.; (Scottsdale, AZ) |
|
Applicant: |
Name |
City |
State |
Country |
Type |
Infineon Technologies Americas Corp. |
El Segundo |
CA |
US |
|
|
Family ID: |
44369021 |
Appl. No.: |
15/083690 |
Filed: |
March 29, 2016 |
Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
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14505417 |
Oct 2, 2014 |
9312375 |
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15083690 |
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13804395 |
Mar 14, 2013 |
8853744 |
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14505417 |
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13018780 |
Feb 1, 2011 |
8399912 |
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13804395 |
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61337924 |
Feb 16, 2010 |
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Current U.S.
Class: |
1/1 |
Current CPC
Class: |
H01L 2224/3015 20130101;
H01L 2924/01006 20130101; H01L 2224/05639 20130101; H01L 2224/0615
20130101; H01L 23/293 20130101; H01L 2224/02166 20130101; H01L
24/30 20130101; H01L 29/4175 20130101; H01L 29/41758 20130101; H01L
2224/291 20130101; H01L 2924/01022 20130101; H01L 2924/04941
20130101; H01L 29/7787 20130101; H01L 2224/05639 20130101; H01L
2224/05166 20130101; H01L 2224/0616 20130101; H01L 2224/06177
20130101; H01L 2924/01033 20130101; H01L 27/088 20130101; H02M
3/158 20130101; H01L 2224/0401 20130101; H01L 2924/01013 20130101;
H01L 2924/00014 20130101; H01L 2224/3003 20130101; H01L 29/2003
20130101; H01L 2224/05556 20130101; H01L 24/32 20130101; H01L
2224/056 20130101; H01L 2924/13064 20130101; H01L 2924/19041
20130101; H01L 24/05 20130101; H01L 2924/00014 20130101; H01L
2224/291 20130101; H01L 2924/014 20130101; H01L 2224/05166
20130101; H01L 2224/29101 20130101; H01L 2924/1306 20130101; H01L
2924/13064 20130101; H01L 2224/05155 20130101; H01L 2224/05082
20130101; H01L 29/205 20130101; H01L 2224/29023 20130101; H01L
2224/30177 20130101; H01L 2224/05082 20130101; H01L 24/33 20130101;
H01L 2224/2919 20130101; H01L 23/4824 20130101; H01L 2224/05155
20130101; H01L 2924/1306 20130101; H01L 2924/14 20130101; H01L
2224/131 20130101; H01L 2224/05555 20130101; H01L 24/06 20130101;
H01L 2224/05567 20130101; H01L 2224/056 20130101; H01L 2224/29014
20130101; H01L 2924/0665 20130101; H01L 2924/0665 20130101; H01L
2924/00 20130101; H01L 2924/00014 20130101; H01L 2924/00014
20130101; H01L 2924/00014 20130101; H01L 2924/0665 20130101; H01L
2924/00 20130101; H01L 2924/00014 20130101; H01L 2924/00 20130101;
H01L 2924/01028 20130101; H01L 2224/05022 20130101; H01L 2224/04026
20130101; H01L 2224/29005 20130101; H01L 2224/0603 20130101; H01L
2224/131 20130101; H01L 2924/01004 20130101; H01L 2924/14 20130101;
H01L 2224/05556 20130101; H01L 2924/00 20130101; H01L 2924/00
20130101; H01L 2924/014 20130101; H01L 2224/05556 20130101; H01L
2924/014 20130101; H01L 2924/014 20130101; H01L 2924/014 20130101;
H01L 2924/00 20130101; H01L 2924/01029 20130101; H01L 2924/00014
20130101; H01L 2924/01047 20130101; H01L 2924/10253 20130101; H01L
2224/05563 20130101; H01L 24/29 20130101; H01L 2224/2919 20130101;
H01L 29/201 20130101; H01L 2924/01014 20130101; H01L 29/452
20130101; H01L 2224/29101 20130101; H01L 2924/01082 20130101 |
International
Class: |
H01L 29/417 20060101
H01L029/417; H02M 3/158 20060101 H02M003/158; H01L 29/778 20060101
H01L029/778; H01L 29/20 20060101 H01L029/20; H01L 29/205 20060101
H01L029/205 |
Claims
1-60. (canceled)
61. A III-nitride semiconductor device comprising: a source and a
drain over a III-nitride layer; a first metal layer over said
III-nitride layer, said first metal layer including a source
contact over said source; a via connecting said source contact to a
second metal layer situated over said first metal layer; a
solderable front metal over said second metal layer.
62. The III-nitride semiconductor device of claim 61, wherein said
first metal layer includes a drain contact over said drain.
63. The III-nitride semiconductor device of claim 62, wherein said
solderable front metal comprises spaced elongated digits configured
for external circuit connection.
64. The III-nitride semiconductor device of claim 61, wherein said
solderable front metal comprises solder bars.
65. The III-nitride semiconductor device of claim 61, wherein said
III-nitride semiconductor device is a high electron mobility
transistor (HEMT).
66. The III-nitride semiconductor device of claim 63, wherein said
spaced elongated digits alternately expose said source contact and
said drain contact.
67. The III-nitride semiconductor device of claim 63, comprising a
first transistor and a second transistor, wherein said solderable
front metal exposes alternating interdigitated source and drain
contacts of said first and second transistors.
68. The III-nitride semiconductor device of claim 61, further
comprising a passivation on said top metal layer, said passivation
surrounding said solderable front metal.
69. The III-nitride semiconductor device of claim 61, further
comprising a passivation on said top metal layer, said passivation
selected from the group consisting of epoxy, polyamide, and silicon
oxide.
70. The III-nitride semiconductor device of claim 61, wherein said
III-nitride layer comprises AlGaN.
71. The III-nitride semiconductor device of claim 61, wherein said
solderable front metal comprises Titanium-Nickel-Silver (TiNiAg)
tri-metal.
72. The III-nitride semiconductor device of claim 61, wherein said
III-nitride layer is situated over a silicon substrate.
73. The III-nitride semiconductor device of claim 61, wherein said
solderable front metal is soldered with solder bars to conductive
traces of a circuit board for external circuit connection.
74. The III-nitride semiconductor device of claim 61, wherein said
solderable front metal is soldered with solder bars to conductive
traces of a circuit board for implementing a DC-DC conversion
circuit.
75. A III-nitride semiconductor device comprising: a first high
electron mobility transistor (HEMT) including a solderable front
metal, said solderable front metal exposing a source contact and a
drain contact of said first HEMT, wherein said solderable front
metal is configured for external circuit connection.
76. The III-nitride semiconductor device of claim 75, further
comprising a second HEMT, wherein said solderable front metal of
said first HEMT and a solderable front metal of said second HEMT
expose alternating interdigitated source and drain contacts.
77. The III-nitride semiconductor device of claim 75, further
comprising a passivation on said top metal layer, said passivation
selected from the group consisting of epoxy, polyamide, and silicon
oxide.
78. The III-nitride semiconductor device of claim 75, wherein said
first HEMT is an AlGaN/GaN HEMT.
79. The III-nitride semiconductor device of claim 75, wherein said
solderable front metal comprises Titanium-Nickel-Silver (TiNiAg)
tri-metal.
80. The III-nitride semiconductor device of claim 75, wherein said
first HEMT is disposed on a silicon substrate.
Description
RELATED APPLICATIONS
[0001] The present application claims the benefit of and priority
to a pending provisional application entitled "III-Nitride Power
Device Having Solderable Front Metal with Source and Drain Solder
Bars," Ser. No. 61/337,924 filed on Feb. 16, 2010. The disclosure
in that pending provisional application is hereby incorporated
fully by reference into the present application.
BACKGROUND OF THE INVENTION
[0002] 1. Field of the Invention
[0003] The present invention relates generally to the field of
semiconductor devices and more particularly to the packaging of
semiconductor devices.
[0004] 2. Background Art
[0005] III-nitride power devices such as Gallium Nitride high
electron mobility transistors or GaN HEMTs are known in the art for
high power performance. However, the performance of such devices
has been constrained by the use of conventional interconnect
schemes. Thus, GaN HEMT devices utilizing multiple interconnect
metal layers have been developed in the art.
[0006] Such multi-level III-nitride power devices have used
conventional integration methods, such as solder ball arrays, for
integration onto a support surface such as a printed circuit board.
In particular, when integrating reduced footprint packages, it is
often expedient to use solder ball arrays to prevent problems such
as solder bridging. Unfortunately, such conventional integration
methods increase the Rdson, or the "on resistance," of the device
by limiting the flow of current through the circuit, thereby
negating the advantages of using multi-level III-nitride power
devices in the first instance.
[0007] Thus, a solution is needed for integrating multi-level
III-nitride power devices onto support surfaces while reducing
Rdson, thereby leveraging the high power performance capabilities
of III-nitride power devices.
SUMMARY OF THE INVENTION
[0008] A III-nitride power device with solderable front metal,
substantially as shown in and/or described in connection with at
least one of the figures, as set forth more completely in the
claims.
BRIEF DESCRIPTION OF THE DRAWINGS
[0009] FIG. 1 illustrates a cross-sectional view of a multi-level
III-nitride power device according to an embodiment of the
invention.
[0010] FIG. 2 illustrates a top view of a multi-level III-nitride
power device according to an embodiment of the invention.
[0011] FIG. 3 illustrates a top view of a substrate for receiving a
III-nitride power device according to an embodiment of the
invention.
[0012] FIG. 4 illustrates a cross-sectional view of a multi-level
III-nitride power device mounted on a substrate according to an
embodiment of the invention.
[0013] FIG. 5 illustrates a circuit diagram integrating a
multi-level III-nitride power device according to an embodiment of
the invention.
DETAILED DESCRIPTION OF THE INVENTION
[0014] The present invention is directed to a III-nitride power
device with solderable front metal. The following description
contains specific information pertaining to the implementation of
the present invention. One skilled in the art will recognize that
the present invention may be implemented in a manner different from
that specifically discussed in the present application. Moreover,
some of the specific details of the invention are not discussed in
order not to obscure the invention. The specific details not
described in the present application are within the knowledge of a
person of ordinary skill in the art.
[0015] The drawings in the present application and their
accompanying detailed description are directed to merely exemplary
embodiments of the invention. Further, to promote clarity and
readability, drawings may not be shown exactly to scale. To
maintain brevity, other embodiments of the present invention are
not specifically described in the present application and are not
specifically illustrated by the present drawings.
[0016] Referring to FIG. 1, a cross-sectional view of an exemplary
multi-level III-nitride power device according to one embodiment of
the invention is illustrated. In FIG. 1, power device 100 can
comprise a multi-level AlGaN/GaN High Electron Mobility Transistor
(HEMT) or Heterojunction Field Effect Transistor (HFET). As
illustrated in FIG. 1, power device 100 includes, among other
elements not shown, passivation 110, solderable front metals (SFM)
140a and 140b, metal layers 130a, 130b, 130c, 130d and 130e,
intermetal dielectric (IMD) layers 112a, 112b and 112c,
Tetraethooxysilane (TEOS) layers 114a and 114b, vias 132a, 132b,
132c and 132d, Aluminum Gallium Nitride (AlGaN) layer 124, Gallium
Nitride (GaN) layer 122, Silicon substrate 120, field nitride 126,
and gate nitride 128.
[0017] In FIG. 1, metal layer 130a may comprise, for example,
titanium nitride, or another suitable gate metal. Metal layer 130e
may comprise, for example, aluminum, or any other suitable metal.
IMD layers 112a-112c may comprise, for example, TEOS. Passivation
110 may comprise, for example, epoxy, polyimide, silicon oxide, or
another suitable material. Epoxy may be preferable to provide
sufficient thickness, such as 20 to 25 microns, for maintaining
structural integrity when soldering the die. As shown in FIG. 1,
passivation 110 encloses and extends around SFM 140a and 140b, for
example by about five microns. In one embodiment, passivation 110
may be configured to leave a soldering surface of approximately 200
microns wide for matching to the width of SFM 140a and 140b. SFM
140a and 140b, as the name suggests, are configured such that the
top or front exposed metal is readily solderable. For example, SFM
140a and 140b may each form a tri-metal with metal layer 130e in a
stacked configuration, suitable for use with high-lead solder such
as 92.5% lead solder. One such tri-metal may comprise TiNiAg, where
metal layer 130e comprises aluminum, and SFM 140a and 140b each
comprise Titanium as a bottom layer, Nickel as the middle layer,
and Silver as a top layer. The Titanium of the tri-metal SFM is
effective as a barrier layer interfacing with aluminum metal layer
130e, while the Silver dissolves into ions to provide increased
conductivity when soldering, leaving Nickel as the contact
layer.
[0018] As shown in FIG. 1, AlGaN layer 124 and GaN layer 122 are
disposed on top of a Silicon substrate 120 to form a high mobility
two-dimensional electronic gas (2 DEG). GaN based III-nitride power
devices are advantageous due to, for example, inherent high
break-down characteristics particularly suited for power management
applications such as DC-DC converters. FIG. 1 shows power device
100 configured as a four interconnect metal layer power device, but
alternative embodiments may comprise a power device with a
different number of interconnect metal layers. In the particular
cross section shown in FIG. 1, vias 132a and 132b can seen
connecting metal layer 130b to metal layer 130c, via 132c can be
seen connecting metal layer 130c to metal layer 130d, and via 132d
can be seen connecting metal layer 130d to metal layer 130e. While
it may appear that insufficient vias are provided for proper
connectivity, if the cross section of FIG. 1 were to be taken at a
different depth, additional vias would be made visible to provide
the necessary connections to fully connect the gate, source, and
drain connections of the III-nitride device externally or to the
outside world. By using the multi-interconnect metal layer
structure and the SFM 140a and 140b of III-nitride power device 100
shown in FIG. 1, efficient movement of current from source to drain
is enabled, thereby advantageously minimizing on resistance
(Rdson), which can be critical due to high currents passing through
the source and drain of III-nitride power device 100.
[0019] Referring now to FIG. 2, a top view of an exemplary
multi-level III-nitride power device in accordance with one
embodiment of the present invention is shown. In many power
applications, it may be desirable to integrate several HFETs (or
HEMTs) onto a single die. Thus, as shown in FIG. 2, power device
200 integrates two HFETs, a control FET 230 and a synch FET 240. In
this example, control FET 230 includes gate digits 236, source
digits 232a, 232b, 232c and 232d, and drain digits 234a, 234b and
234c. Synch FET 240 includes gate digit 246, source digits 222,
242a, 242b and 242c, and drain digits 244a, 244b, 244c and 244d. As
shown in FIG. 2, power device 200 exposes the spaced alternating
interdigitated source and drain digits from the SFMs on top of the
die. These elongated digits may then be soldered to copper traces
on a support board using long solder bars. In this fashion,
soldering surface area is optimized relative to using conventional
solder balls or conventional solder bumps, while minimizing solder
bridging. Although eight columns of digits are shown in FIG. 2,
alternative embodiments may use more or fewer digits according to
application requirements.
[0020] Referring now to FIG. 3, a top view of an exemplary
substrate for receiving the exemplary III-nitride power device in
accordance with one embodiment of the present invention is shown.
As shown in FIG. 3, substrate 300 includes a cross-section A-A
which can correspond to the cross-section shown in FIG. 4,
discussed below. Substrate 300 may receive several components
including III-nitride die 310 corresponding to power device 200 of
FIG. 2, gate driver integrated circuit (IC) 312, and capacitors
314a, 314b, 314c and 314d. Pin 1 connection of gate driver IC 312
is indicated by solder pad 301, with pins numbering upwards in the
clockwise direction. Gate driver IC 312 may comprise, for example,
the IRD2010 driver IC available from International Rectifier.
Substrate 300 further includes solder bars 354a, 354b, 356a, 356b,
358a, 358b, 360a, 360b, 344, 362, 346, 364, 348, 366, 322a, 322b,
and 350, which may correspondingly receive the SFMs exposed by
III-nitride die 310 corresponding to power device 200 when flipped
onto substrate 300. The substrate may help position the SFMs by
providing, for example, matched openings with 25 microns of empty
padding on all sides for solder fill.
[0021] The grey portions of substrate 300 below the solder bars are
copper traces, which may be preferably 1 to 2 oz per square inch or
thicker to improve conductivity and reduce resistance. Several vias
such as via 352 are also shown throughout substrate 300, and may
preferably comprise walls of at least 40 microns to improve
conductivity and reduce resistance. The vias may route to external
circuit connections such as to a printed circuit board. Although
the vias are depicted in FIG. 3 as the same size, they may actually
differ in size.
[0022] Solder bars 362, 364, and 366 will make contact to the SFMs
that are connected to the drain of control FET 230, which receives
Vin from gate driver IC 312. Solder bars 344, 346, 348 and 350 will
make contact to the SFMs that are connected to the source of synch
FET 240 or power ground (P-ground), distinguished from analog or
signal ground. While solder bars 344, 346, 348 and 350 may appear
to be isolated, they are actually grounded together by vias to an
unseen grounding layer. Solder bars 354a, 354b, 356a, 356b, 358a,
358b, 360a and 360b are connected to a switch node 336 which
connects the source of control FET 230 to the drain of synch FET
240. Switch node 336 also functions as the "gate return" for
control FET 230. Node 334 is connected to the gate of control FET
230, node 338 is connected to P-ground and also functions as the
"gate return" for synch FET 240, and node 340 is connected to the
gate of synch FET 240.
[0023] Node 332 connects gate driver IC 312 to capacitor 314c,
which may comprise a bootstrap or boost (BST) capacitor. Node 342
connects gate driver IC 312 to capacitor 314d, which may comprise a
bypass capacitor for filtering ripple noise. Capacitors 314a and
314b are also shown in FIG. 3, connected in parallel and receiving
Vin from gate driver IC 312. As shown in FIG. 3, solder pads 370a
through 370d and 372a through 372d are positioned appropriately on
substrate 300 to receive capacitors 314a through 314d.
[0024] Referring now to FIG. 4, a cross-sectional view of an
exemplary multi-level III-nitride power device mounted on a
substrate according to one embodiment of the invention is
illustrated. As discussed above, the cross section of FIG. 4 is
taken from cross section A-A of FIG. 3. III-Nitride die 410 is
flipped, with the exposed SFM resting directly on solder bars 404
and 406. Switch node 336 of FIG. 3 is shorted through copper trace
482, which connects the drain of synch FET 240 resting on solder
bar 404 and the source of control FET 230 resting on solder bar
406.
[0025] As can be seen in FIG. 4, using solder bars 404 and 406
running parallel with the SFM of III-nitride die 410 rather than
using conventional solder balls or bumps provides greater surface
area for conduction and heat dissipation, advantageously reducing
Rdson. Furthermore, since solder bars 404 and 406 are continuous in
lateral directions, current can be routed laterally through solder
bars 404 and 406, further increasing conduction. In contrast, if
conventional solder balls or bumps were utilized, then current
could not travel in the lateral direction since the balls would
introduce non-conductive gaps, requiring current to be rerouted
through copper trace 482 or III-nitride die 410.
[0026] Referring now to FIG. 5, a circuit diagram integrating an
exemplary multi-level III-nitride power device according to one
embodiment of the invention is illustrated. Control FET 510a,
labeled Q1, may correspond to control FET 230 of FIG. 2. Synch FET
510b, labeled Q2, may correspond to synch FET 240 of FIG. 2.
Capacitor 512a, labeled C1, may correspond to the
parallel-connected capacitors 314a and 314b in FIG. 3. Capacitor
512c, labeled C2, may correspond to capacitor 314c in FIG. 3.
Capacitor 512d, labeled C3, may correspond to capacitor 314d in
FIG. 3. Gate driver IC 514, shown as an IRD2010 driver IC by
International Rectifier, may correspond to gate driver IC 312 shown
in FIG. 3.
[0027] As discussed above, the SFMs fabricated and integrated on
the die of a III-nitride power device and connected to solder bars
on the package substrate together minimize Rdson and therefore
improve conductivity in the switch node (SW) between FETs 510a (Q1)
and 510b (Q2), and enable power circuit 500 shown in FIG. 5, which
can be, for example, a DC to DC buck converter (also referred to
generally as a "DC-DC conversion circuit" in the present
application), to operate more efficiently. Thus, as discussed
above, in the embodiments of FIGS. 1 through 5, the invention
achieves a III-nitride power device and package therefor that
result in, among other things, enhanced thermal and conductivity
performance including a reduced effective Rdson for the power
transistors used therein.
[0028] From the above description of the invention it is manifest
that various techniques can be used for implementing the concepts
of the present invention without departing from its scope.
Moreover, while the invention has been described with specific
reference to certain embodiments, a person of ordinary skill in the
art would appreciate that changes can be made in form and detail
without departing from the spirit and the scope of the invention.
For example, conducting and non-conducting cells can have varying
elements and configurations while still embodying the spirit of the
present invention. Thus, the described embodiments are to be
considered in all respects as illustrative and not restrictive. It
should also be understood that the invention is not limited to the
particular embodiments described herein but is capable of many
rearrangements, modifications, and substitutions without departing
from the scope of the invention.
* * * * *