U.S. patent application number 14/589650 was filed with the patent office on 2016-07-07 for split gate non-volatile flash memory cell having metal gates and method of making same.
The applicant listed for this patent is Silicon Storage Technology, Inc.. Invention is credited to Chun-Ming Chen, Chien-Sheng Su, Man-Tang Wu, Jeng-Wei Yang.
Application Number | 20160197088 14/589650 |
Document ID | / |
Family ID | 55069099 |
Filed Date | 2016-07-07 |
United States Patent
Application |
20160197088 |
Kind Code |
A1 |
Chen; Chun-Ming ; et
al. |
July 7, 2016 |
Split Gate Non-volatile Flash Memory Cell Having Metal Gates And
Method Of Making Same
Abstract
A non-volatile memory cell includes a substrate of a first
conductivity type, having a first region of a second conductivity
type, a second region of the second conductivity type spaced apart
from the first region, forming a channel region therebetween. A
floating gate is disposed over and insulated from a first portion
of the channel region which is adjacent the first region. A select
gate is disposed over a second portion of the channel region
adjacent to the second region, the select gate being formed of a
metal material and being insulated from the second portion of the
channel region by a layer of silicon dioxide and a layer of high K
insulating material. A control gate is disposed over and insulated
from the floating gate. An erase gate is disposed over and
insulated from the first region, and disposed laterally adjacent to
and insulated from the floating gate.
Inventors: |
Chen; Chun-Ming; (New Taipei
City, TW) ; Wu; Man-Tang; (Hsinchu County, TW)
; Yang; Jeng-Wei; (Zhubei, TW) ; Su;
Chien-Sheng; (Saratoga, CA) |
|
Applicant: |
Name |
City |
State |
Country |
Type |
Silicon Storage Technology, Inc. |
San Jose |
CA |
US |
|
|
Family ID: |
55069099 |
Appl. No.: |
14/589650 |
Filed: |
January 5, 2015 |
Current U.S.
Class: |
257/316 ;
438/261 |
Current CPC
Class: |
H01L 29/517 20130101;
H01L 29/66825 20130101; H01L 29/45 20130101; H01L 21/02186
20130101; H01L 29/511 20130101; H01L 27/11521 20130101; H01L 29/495
20130101; H01L 29/40114 20190801; H01L 29/7881 20130101; H01L
21/02189 20130101; H01L 27/11524 20130101; H01L 29/42328 20130101;
H01L 29/4916 20130101; H01L 29/788 20130101; H01L 21/02181
20130101 |
International
Class: |
H01L 27/115 20060101
H01L027/115; H01L 29/51 20060101 H01L029/51; H01L 29/49 20060101
H01L029/49; H01L 29/66 20060101 H01L029/66; H01L 21/28 20060101
H01L021/28; H01L 21/02 20060101 H01L021/02; H01L 29/788 20060101
H01L029/788; H01L 29/423 20060101 H01L029/423; H01L 29/45 20060101
H01L029/45 |
Claims
1. (canceled)
2. The memory cell of claim 8, wherein the high K insulating
material for the layers of high K insulating material is at least
one of HfO2, ZrO2, and TiO2.
3. The memory cell of claim 8, wherein the erase gate is formed of
a metal material.
4. (canceled)
5. A non-volatile memory cell comprising: a substrate of a first
conductivity type, having a first region of a second conductivity
type, a second region of the second conductivity type spaced apart
from the first region, forming a channel region therebetween; a
floating gate disposed over and insulated from a first portion of
the channel region which is adjacent the first region; a select
gate disposed over a second portion of the channel region which is
adjacent to the second region, the select gate being formed of a
metal material and being insulated from the second portion of the
channel region by a layer of silicon dioxide and a layer of high K
insulating material; a control gate disposed over and insulated
from the floating gate; and an erase gate disposed over and
insulated from the first region, and disposed laterally adjacent to
and insulated from the floating gate; wherein the erase gate is
formed of a polysilicon material; and silicide disposed on an upper
surface of the erase gate.
6. The memory cell of claim 5, wherein an upper surface of the
select gate is higher above the substrate than the upper surface of
the erase gate.
7. The memory cell of claim 8, further comprising: silicide
disposed on a portion of the substrate in the second region.
8. A non-volatile memory cell comprising: a substrate of a first
conductivity type, having a first region of a second conductivity
type, a second region of the second conductivity type spaced apart
from the first region, forming a channel region therebetween; a
floating gate disposed over and insulated from a first portion of
the channel region which is adjacent the first region; a select
gate disposed over a second portion of the channel region which is
adjacent to the second region, the select gate being formed of a
metal material and being insulated from the second portion of the
channel region by a layer of silicon dioxide and a layer of high K
insulating material; a control gate disposed over and insulated
from the floating gate; and an erase gate disposed over and
insulated from the first region, and disposed laterally adjacent to
and insulated from the floating gate; wherein the erase gate is
insulated from the floating gate by silicon dioxide and by a layer
of high K insulating material.
9. A non-volatile memory cell comprising: a substrate of a first
conductivity type, having a first region of a second conductivity
type, a second region of the second conductivity type spaced apart
from the first region, forming a channel region therebetween; a
floating gate disposed over and insulated from a first portion of
the channel region which is adjacent the first region; a select
gate disposed over a second portion of the channel region which is
adjacent to the second region, the select gate being formed of a
metal material and being insulated from the second portion of the
channel region by a layer of silicon dioxide and a layer of high K
insulating material; a control gate disposed over and insulated
from the floating gate; and an erase gate disposed over and
insulated from the first region, and disposed laterally adjacent to
and insulated from the floating gate; and a work function metal
layer extending along bottom and side surfaces of the select
gate.
10. The memory cell of claim 3, further comprising: a work function
metal layer extending along bottom and side surfaces of the select
gate; and a work function metal layer extending along bottom and
side surfaces of the erase gate.
11. A method of forming a non-volatile memory cell comprising:
forming, in a substrate of a first conductivity type, spaced apart
first and second regions of a second conductivity type, defining a
channel region therebetween; forming a floating gate disposed over
and insulated from a first portion of the channel region which is
adjacent the first region; forming a control gate disposed over and
insulated from the floating gate; forming a first block of
polysilicon disposed over and insulated from a second portion of
the channel region which is adjacent to the second region; forming
a second block of polysilicon disposed over and insulated from the
first region, and disposed laterally adjacent to and insulated from
the floating gate; removing the first block of polysilicon and
replacing the first block of poly silicon with a block of metal
material; and forming an insulation layer between the block of
metal material and the second portion of the channel region that
comprises a layer of silicon dioxide and a layer of high K
insulating material.
12. The method of claim 11, wherein the high K insulating material
is at least one of HfO2, ZrO2, and TiO2.
13. The method of claim 11, further comprising: removing the second
block of polysilicon and replacing the second block of polysilicon
with a second block of metal material.
14. The method of claim 13 wherein: the removing of the first block
of polysilicon and the removing of the second block of polysilicon
are performed in a same processing step; and the replacing of the
first block of polysilicon and the replacing of the second block of
polysilicon are performed in a same processing step.
15. The method of claim 11, further comprising: forming silicide on
an upper surface of the second block of polysilicon.
16. The method of claim 15, wherein an upper surface of the metal
block of material is higher above the substrate than the upper
surface of the second block of polysilicon.
17. The method of claim 11, further comprising: forming silicide on
a portion of the substrate in the second region.
18. The method of claim 11, wherein the second block of polysilicon
is insulated from the floating gate by silicon dioxide and by a
layer of high K insulating material.
19. The method of claim 11, further comprising: forming a work
function metal layer extending along bottom and side surfaces of
the block of metal material.
20. The method of claim 13, further comprising: forming a work
function metal layer extending along bottom and side surfaces of
the block of metal material; and forming a work function metal
layer extending along bottom and side surfaces of the second block
of metal material.
Description
TECHNICAL FIELD
[0001] The present invention relates to a non-volatile flash memory
cell which has a select gate, a floating gate, a control gate, and
an erase gate.
BACKGROUND OF THE INVENTION
[0002] Split gate non-volatile flash memory cells having a select
gate, a floating gate, a control gate and an erase gate are well
known in the art. See for example U.S. Pat. Nos. 6,747,310 and
7,868,375. An erase gate having an overhang over the floating gate
is also well known in the art. See for example, U.S. Pat. No.
5,242,848. All three of these patents are incorporated herein by
reference in their entirety.
[0003] Silicon dioxide has been used as a gate dielectric for
select gate, also called WL (word-line), of split gate non-volatile
flash memory. As flash memory cells have reduced in size, the
thickness of the silicon dioxide has become thinner to increase the
gate capacitance for higher current drive. However, as the select
gate oxide is reduced to below 2 nm, the oxide leakage current
increases significantly. As discussed below, replacing silicon
dioxide with gate last, or replacement metal gate (HKMG--High-K
Metal Gate) can alleviate the leakage and at the same time enhance
the select gate current drive for cell read current.
[0004] Accordingly, it is one of the objectives of the present
invention to improve the performance of memory cells as they
continue to shrink in size.
SUMMARY OF THE INVENTION
[0005] A non-volatile memory cell comprises a substrate of a first
conductivity type, having a first region of a second conductivity
type, a second region of the second conductivity type spaced apart
from the first region, forming a channel region therebetween, a
floating gate disposed over and insulated from a first portion of
the channel region which is adjacent the first region, a select
gate disposed over a second portion of the channel region which is
adjacent to the second region, the select gate being formed of a
metal material and being insulated from the second portion of the
channel region by a layer of silicon dioxide and a layer of high K
insulating material, a control gate disposed over and insulated
from the floating gate, and an erase gate disposed over and
insulated from the first region, and disposed laterally adjacent to
and insulated from the floating gate.
[0006] A method of forming a non-volatile memory cell comprises
forming, in a substrate of a first conductivity type, spaced apart
first and second regions of a second conductivity type, defining a
channel region therebetween, forming a floating gate disposed over
and insulated from a first portion of the channel region which is
adjacent the first region, forming a control gate disposed over and
insulated from the floating gate, forming a first block of
polysilicon disposed over and insulated from a second portion of
the channel region which is adjacent to the second region, forming
a second block of polysilicon disposed over and insulated from the
first region, and disposed laterally adjacent to and insulated from
the floating gate, removing the first block of polysilicon and
replacing the first block of polysilicon with a block of metal
material, and forming an insulation layer between the block of
metal material and the second portion of the channel region that
comprises a layer of silicon dioxide and a layer of high K
insulating material.
[0007] Other objects and features of the present invention will
become apparent by a review of the specification, claims and
appended figures.
BRIEF DESCRIPTION OF THE DRAWINGS
[0008] FIGS. 1A-1M are cross sectional views illustrating steps in
forming the memory cell of the present invention.
[0009] FIGS. 2A-2D are cross sectional views illustrating steps in
forming an alternate embodiment of the memory cell of the present
invention.
[0010] FIGS. 3A-3B are cross sectional views illustrating steps in
forming a second alternate embodiment of the memory cell of the
present invention.
DETAILED DESCRIPTION OF THE INVENTION
[0011] Referring to FIGS. 1A-1M there are shown cross-sectional
views of the steps in the process to make a memory cell in which
the select gate and the erase gate are formed of highly conductive
metal material. The process begins by forming a layer of silicon
dioxide (oxide) 12 on a substrate 10 of P type single crystalline
silicon. Thereafter a first layer 14 of polysilicon (or amorphous
silicon) is formed on the layer 12 of silicon dioxide, as
illustrated in FIG. 1A. The first layer 14 of polysilicon is
subsequently patterned in a direction perpendicular to the view of
FIG. 1A.
[0012] Another insulating layer 16, such as silicon dioxide (or
even a composite layer, such as ONO (oxide, nitride, oxide)) is
formed on the first layer 14 of polysilicon. A second layer 18 of
polysilicon is then formed on the oxide layer 16. Another
insulating layer 20 is formed on the second layer 18 of polysilicon
and used as a hard mask during subsequent dry etching. In the
preferred embodiment, the layer 20 is a composite layer, comprising
silicon nitride 20a, silicon dioxide 20b, and silicon nitride 20c.
The resulting structure is shown in FIG. 1B. The hard mask may be a
composite layer of silicon oxide 20b and silicon nitride 20c. The
hard mask may also be formed with a thick silicon nitride layer
20a.
[0013] Photoresist material (not shown) is coated on the structure,
and a masking step is performed exposing selected portions of the
photoresist material. The photoresist is developed and using the
photoresist as a mask, the structure is etched. Specifically, the
composite layer 20, the second layer 18 of polysilicon, the
insulating layer 16 are anisotropically etched, until the first
layer 14 of polysilicon is exposed. The resultant structure is
shown in FIG. 1C. Although only two "stacks": S1 and S2 are shown,
it should be clear that there are a number of such "stacks" that
are separated from one another.
[0014] Silicon dioxide 22 is formed on the structure. This is
followed by the formation of silicon nitride layer 24. The silicon
nitride 24 is anisotropically etched leaving a composite spacer 26
(which is the combination of the silicon dioxide 22 and silicon
nitride 24) alongside each of the stacks S1 and S2. Formation of
spacers is well known in the art, and involves the deposition of a
material over the contour of a structure, followed by an
anisotropic etch process, whereby the material is removed from
horizontal surfaces of the structure, while the material remains
largely intact on vertically oriented surfaces of the structure
(with a rounded upper surface). The resultant structure is shown in
FIG. 1D.
[0015] A layer of oxide is formed over the structure, followed by
an anisotropical etch leaving spacers 30 of the oxide alongside the
stacks S1 and S2. A photoresist 28 is formed over the regions
between the stacks S1 and S2, and other alternating pairs of stacks
S1 and S2. For the purpose of this discussion, the region between
the pair of stacks S1 and S2 will be called the "inner region" and
the regions outside of the inner region (i.e. between adjacent
pairs of stacks S1 and S2) will be referred to as the "outer
regions". The exposed spacers 30 in the outer regions are removed
by isotropic etch. The resulting structure is shown in FIG. 1E.
[0016] After the photoresist 28 is removed, the exposed portions
first polysilicon 14 in the inner and outer regions are
anisotropically etched. Part of oxide layer 12 will also be etched
(removed) during the poly over-etching. A thinner layer of
remaining oxide will preferably stay on the substrate 10 so as to
prevent damage to the substrate 10. The resultant structure is
shown in FIG. 1F.
[0017] A layer of oxide is formed over the structure, followed by
an anisotropical etch leaving spacers 31 of the oxide alongside the
stacks S1 and S2 and a layer 33 of oxide on substrate 34. Another
oxide layer is formed over the structure, thickening spacers 31 and
layer 33. Photoresist material 32 is then coated and masked leaving
openings in the inner regions between the stacks S1 and S2. Again,
similar to the drawing shown in FIG. 1E, the photoresist is between
other alternating pairs of stacks. The resultant structure is
subject to an ion implant 34 (i.e. into exposed portions of
substrate 10). The oxide spacers 31 adjacent to the stacks S1 and
S2 and oxide layer 33 in the inner region are then removed by e.g.
a wet etch. The resultant structure is shown in FIG. 1G.
[0018] The photoresist material 32 in the outer regions of the
stacks S1 and S2 is removed. A high-temperature thermal annealing
step is applied to activate the ion implant 34 and to form the
source junction (i.e. first or source region 34). Silicon dioxide
36 is formed everywhere. The structure is once again covered by
photoresist material 38 and a masking step is performed exposing
the outer regions of the stacks S1 and S2 and leaving photoresist
material 38 covering the inner region between the stacks S1 and S2.
An oxide anisotropical etch followed by isotropic wet etch are
performed, to remove oxide 36 and oxide 33 from the outer regions
of stacks S1 and S2, and possibly to reduce the thickness of the
oxide spacers 31 in the outer regions of the stacks S1 and S2. The
resultant structure is shown in FIG. 1H.
[0019] After photoresist material 38 is removed, an insulation
layer 40 is formed over the structure. Preferably, the insulation
layer includes a first layer of thin oxide as the interfacial layer
(IL) and a second layer of a high K material (i.e. having a
dielectric constant K greater than that of oxide, such as
HfO.sub.2, ZrO.sub.2, TiO.sub.2, Ta.sub.2O.sub.5, or other adequate
materials, etc.). The IL thickness may be varied to achieve
different threshold voltage for the select gate of the split-gate
flash cell. An optional thermal treatment may follow to enhance
moisture control on the gate dielectric. A capping layer, such as
TiN, TaN, TiSiN, may be deposited on the structure to protect the
high K material from damaging in the subsequent processing steps.
Polysilicon is then deposited over the structure, followed by a CMP
etch, resulting in a block 42 of polysilicon in the inner region of
the stacks S1 and S2, and blocks 44 of polysilicon in the outer
regions of the stacks S1 and S2. The resultant structure is shown
in FIG. 1I.
[0020] An N+ poly pre-implant may be performed. This is followed by
a photoresist coating, mask exposure and selective removal,
followed by selective poly etch, to remove a portion of poly blocks
44 (so that the remaining poly blocks 44 are properly sized for the
eventual select gates). An LDD implant is performed in the exposed
portions of substrate 10 adjacent poly blocks 44. Oxide and nitride
depositions, followed by nitride etch, are performed to form
insulation spacers 46 of oxide 48 and nitride 50 alongside poly
blocks 44. An N+ implant and anneal is then performed to form
second (drain) regions 52 in substrate 10. The resultant structure
is shown in FIG. 1J.
[0021] A metallization process is performed to form silicide 54 on
the exposed portions substrate 10 (along surface portion of second
regions 52). Silicide is also formed on the exposed upper surfaces
of poly blocks 42, 44. A layer 56 of nitride is formed over the
structure, followed by an inter-layer dielectric (ILD) material 58.
A CMP etch is then performed to remove nitride 56 and ILD 58 above
poly blocks 42 and 44 (which also removes the silicide on those
poly blocks). The resultant structure is shown in FIG. 1K.
[0022] A poly etch is then performed to remove poly blocks 42 and
44, leaving open trenches behind. Work function metal gate material
60, such as TiAlN.sub.1-x, is deposited on the structure. Its work
function can be further tuned by changing oxygen vacancies or
nitrogen concentration. The select gate threshold voltage of the
split-gate flash is adjusted through the tuning of the work
function. A thick layer of metal (e.g. aluminum, Ti, TiAlN, TaSiN,
etc.) is deposited on the structure, followed by a CMP etch back,
leaving metal block 62 filling the trench over first region 34 and
metal blocks 64 filling trenches adjacent second regions 52. A
post-metal thermal treatment may be applied to optimize the
performance of the memory cell. The resultant structure is shown in
FIG. 1L. It should be noted that the formation of the layer of high
K material such as HfO.sub.2, ZrO.sub.2, TiO.sub.2, etc. as part of
insulation layer 40 could be formed just before the formation of
layer 60 instead of earlier as described above with respect to FIG.
1L.
[0023] An insulation layer 66 (e.g. ILD) is formed over the
structure. Contact openings are formed through the ILD layer 66
down to and exposing the silicide 54 using an appropriate photo
resist coating, mask exposure, selective photo resist etch and ILD
etch. The contact openings are filled with conductive material
(e.g. tungsten) using an appropriate deposition and CMP etch to
form electrical contacts 68. Metal contact lines 70 are then formed
over ILD layer 66 and in contact with the electrical contacts 68.
The resultant structure is shown in FIG. 1M.
[0024] As shown in FIG. 1M, the memory cells are formed in pairs
that share a common first region 34 and common erase gate 62. Each
memory cell includes a channel region 72 extending between the
first and second regions 34 and 52, and have a first portion
disposed under the floating gate 14 and a second portion disposed
under the select gate 64. The control gate 18 is disposed over the
floating gate 14. By having erase gates 62 and select gates 64
being formed of metal, and silicide 54 connecting contacts 68 with
second regions 52, along with insulation layer 40 formed of oxide
and a high K film underneath the select gates 64, the speed and
performance of the memory cell is enhanced over memory cells with
conventional polysilicon gates and conventional oxide as the gate
dielectric under the select gates.
[0025] FIGS. 2A-2D illustrate an alternate embodiment where the
same processing steps described above with respect to FIGS. 1A-1M
are performed except where noted. Starting with the structure of
FIG. 1H, and with respect to the process steps discussed above with
respect to FIG. 1I, after the photoresist material 38 is removed,
and after the insulation layer 40 is formed over the structure,
photo resist 76 can be formed over the outer regions of stacks S1
and S2, whereby an etch is performed to remove the layer of high K
material of insulation layer 40 in the inner region of stacks S1
and S2, (but maintains the layer of high K material of insulation
layer 40 underneath where the select gates will be formed), as
illustrated in FIG. 2A.
[0026] After the remaining processing discussed above with respect
to FIG. 1I is completed, photo resist 78 is formed over poly blocks
44, followed by a poly etch to recess the upper surface of poly
blocks 42, as illustrated in FIG. 2B. The structure is then
processed as discussed above through the formation of silicide 54,
nitride 56 and ILD 58 with respect to FIG. 1K above. However, since
poly block 42 is recessed, that results in silicide 54 remaining on
poly block 42, and nitride 56 and ILD 58 being formed on poly block
42, as illustrated in FIG. 2C. Then the remaining processing steps
as discussed above are performed, resulting in the final structure
shown in FIG. 2D. Because poly block 42 is protected from the poly
etch that removes poly blocks 44, poly block 42 remains intact as
the erase gate. Moreover, its conductivity is enhanced by the
formation of silicide 54 on its upper surface. Therefore, this
embodiment combines a metal select gate 64 with a silicide enhanced
polysilicon erase gate 42. It also removes the high K film between
the erase gate 42 and floating gate 14 for better control over the
thickness of the tunnel oxide therebetween.
[0027] FIGS. 3A-3B illustrate a second alternate embodiment where
the same processing steps described above with respect to FIGS.
1A-1M are performed except where noted. This embodiment starts with
the same processing for forming the structure of FIG. 2A, where the
layer of high K material in the inner region of stacks S1 and S2 is
removed. The remaining processing steps described above with
respect to FIGS. 1I-1M are then performed, except that before the
poly etch used to remove poly blocks 42 and 44, photoresist 80 is
formed over poly block 42 to prevent its removal, as shown in FIG.
3A. Because poly block 42 is protected from the poly etch that
removes poly blocks 44, poly block 42 remains fully intact as the
erase gate. Then, the remaining processing steps as discussed above
with respect to FIGS. 1K to 1M are performed, resulting in the
final structure shown in FIG. 3B. This embodiment combines a metal
select gate 64 with a full sized polysilicon erase gate 42, and the
high K film between the erase gate 42 and floating gate 14 is
removed for better control over the thickness of the tunnel oxide
therebetween.
[0028] It is to be understood that the present invention is not
limited to the embodiment(s) described above and illustrated
herein, but encompasses any and all variations falling within the
scope of the appended claims. For example, references to the
present invention herein are not intended to limit the scope of any
claim or claim term, but instead merely make reference to one or
more features that may be covered by one or more of the claims.
Materials, processes and numerical examples described above are
exemplary only, and should not be deemed to limit the claims.
Further, as is apparent from the claims and specification, not all
method steps need be performed in the exact order illustrated or
claimed, but rather in any order that allows the proper formation
of the memory cell of the present invention. Lastly, single layers
of material could be formed as multiple layers of such or similar
materials, and vice versa.
[0029] It should be noted that, as used herein, the terms "over"
and "on" both inclusively include "directly on" (no intermediate
materials, elements or space disposed therebetween) and "indirectly
on" (intermediate materials, elements or space disposed
therebetween). Likewise, the term "adjacent" includes "directly
adjacent" (no intermediate materials, elements or space disposed
therebetween) and "indirectly adjacent" (intermediate materials,
elements or space disposed there between), "mounted to" includes
"directly mounted to" (no intermediate materials, elements or space
disposed there between) and "indirectly mounted to" (intermediate
materials, elements or spaced disposed there between), and
"electrically coupled" includes "directly electrically coupled to"
(no intermediate materials or elements there between that
electrically connect the elements together) and "indirectly
electrically coupled to" (intermediate materials or elements there
between that electrically connect the elements together). For
example, forming an element "over a substrate" can include forming
the element directly on the substrate with no intermediate
materials/elements therebetween, as well as forming the element
indirectly on the substrate with one or more intermediate
materials/elements therebetween.
* * * * *