U.S. patent application number 14/579763 was filed with the patent office on 2016-06-23 for devices for utilizing symfets for low-power information processing.
This patent application is currently assigned to University of Notre Dame du Lac. The applicant listed for this patent is University of Notre Dame du Lac. Invention is credited to X. Sharon Hu, Joseph J. Nahas, Michael Niemier, Behnam Sedighi.
Application Number | 20160182055 14/579763 |
Document ID | / |
Family ID | 56083268 |
Filed Date | 2016-06-23 |
United States Patent
Application |
20160182055 |
Kind Code |
A1 |
Sedighi; Behnam ; et
al. |
June 23, 2016 |
DEVICES FOR UTILIZING SYMFETS FOR LOW-POWER INFORMATION
PROCESSING
Abstract
A Boolean gate includes at least one symmetric tunneling
field-effect transistor (SymFET) for low-power information
processing. SymFETs are ideal for applications that demand low
power and have moderate speed requirements, and demonstrate better
dynamic energy efficiency than CMOS circuits. Negative differential
resistance (NDR) behavior of SymFETs leads to hysteresis in
inverters and buffers, and can be used to build simple
Schmitt-triggers. Further, pseudo-SymFET loads may be utilized in
circuits similar to all-n-type or dynamic logic. For example,
latches and flip-flops as well as NAND, NOR, IMPLY, and MAJORITY
gates may employ SymFETs. Such SymFET-based devices require fewer
transistors than static CMOS-based designs.
Inventors: |
Sedighi; Behnam; (San Diego,
CA) ; Niemier; Michael; (Granger, IN) ; Hu; X.
Sharon; (Granger, IN) ; Nahas; Joseph J.;
(Austin, TX) |
|
Applicant: |
Name |
City |
State |
Country |
Type |
University of Notre Dame du Lac |
Notre Dame |
IN |
US |
|
|
Assignee: |
University of Notre Dame du
Lac
Notre Dame
IN
|
Family ID: |
56083268 |
Appl. No.: |
14/579763 |
Filed: |
December 22, 2014 |
Current U.S.
Class: |
326/2 |
Current CPC
Class: |
H03K 19/195 20130101;
H01L 29/0895 20130101; H01L 29/1606 20130101; H01L 29/66977
20130101; B82Y 10/00 20130101; H01L 29/127 20130101; H01L 29/778
20130101; H01L 29/7613 20130101 |
International
Class: |
H03K 19/195 20060101
H03K019/195; H01L 29/778 20060101 H01L029/778; H01L 29/08 20060101
H01L029/08; H01L 29/16 20060101 H01L029/16 |
Claims
1. A Boolean logic device comprising: at least two SymFETs, with
each of the at least two SymFETs including a top gate, a back gate,
an insulator, a first graphene layer, a second graphene layer, a
first oxide layer, and a second oxide layer, the insulator being
disposed between the first and second graphene layers, the first
and second graphene layers being disposed between the first and
second oxide layers, the first and second oxide layers being
disposed between the top and back gates, wherein conductivity of
each of the at least two SymFETs is controlled at least in part by
a first voltage supplied to the top gate and a second voltage
supplied to the back gate; wherein the at least two SymFETs are
configured in at least one of a parallel or series circuit
arrangement such that input voltage is transformed to an output
voltage.
2. A Boolean logic device of claim 1, wherein the circuit inverts
the input voltage and the circuit is bistable for at least one
non-zero value of the input voltage.
3. A Boolean logic device of claim 2, further comprising: an
electrical drain in electrical communication with a first of the at
least two SymFETs; and a feedback loop disposed between the
electrical drain and the back gate of the first of the at least two
SymFETs.
4. A Boolean logic device of claim 1 wherein the at least two
SymFETs define a first SymFET and a second SymFET, the Boolean
logic device further comprising: a third SymFET and a fourth
SymFET, with the third and fourth SymFETs including a top gate, a
back gate, an insulator, a first graphene layer, a second graphene
layer, a first oxide layer, and a second oxide layer, the insulator
being disposed between the first and second graphene layers, the
first and second graphene layers being disposed between the first
and second oxide layers, the first and second oxide layers being
disposed between the top and back gates, wherein conductivities of
the first and second SymFETs are controlled at least in part by a
first voltage, wherein conductivities of the third and fourth
SymFETs are controlled at least in part by a second voltage;
wherein the first, second, third, and fourth SymFETs are configured
in a circuit such that the output voltage is false only if the
first and second voltages are true.
5. A Boolean logic device of claim 1 wherein the at least two
SymFETs define a first SymFET and a second SymFET, the Boolean
logic device further comprising: a third SymFET including a top
gate, a back gate, an insulator, a first graphene layer, a second
graphene layer, a first oxide layer, and a second oxide layer, the
insulator being disposed between the first and second graphene
layers, the first and second graphene layers being disposed between
the first and second oxide layers, the first and second oxide
layers being disposed between the top and back gates, wherein
conductivity of the first SymFET is controlled at least in part by
a first voltage, wherein conductivity of the second SymFET is
controlled at least in part by a second voltage; wherein the first,
second, and third SymFETs are configured in a circuit such that the
output voltage is true only if both the first and second voltages
are false.
6. A Boolean logic device of claim 5, further comprising a clocked
input.
7. A Boolean logic device of claim 1 wherein the at least two
SymFETs define a first SymFET and a second SymFET, the Boolean
logic device further comprising: a first voltage source applying a
first voltage to the top gates of the first and second transistors;
and a source terminal applying a second voltage, the source
terminal coupled to the first SymFET, wherein an output of the
circuit is false only if the first voltage is true and the second
voltage is false.
8. A Boolean logic device of claim 1 wherein the at least two
SymFETs define a first SymFET and a second SymFET, the Boolean
logic device further comprising: a third SymFET and a fourth
SymFET, with the third and fourth SymFETs including a top gate, a
back gate, an insulator, a first graphene layer, a second graphene
layer, a first oxide layer, and a second oxide layer, the insulator
being disposed between the first and second graphene layers, the
first and second graphene layers being disposed between the first
and second oxide layers, the first and second oxide layers being
disposed between the top and back gates, wherein the first and
second SymFETs are in parallel, wherein the fourth SymFET is in
series with the second SymFET, wherein the third SymFET is in
series with the first SymFET, wherein the input voltage is supplied
to the top gates of the second SymFET and the fourth SymFET and a
bias voltage is supplied to the back gates of the first and second
SymFETs, wherein a second input voltage is supplied to the top
gates of the first and third SymFETs, wherein a drain voltage is
coupled to the second and fourth SymFETs, wherein the first and
third SymFETs are grounded, wherein the back gate of the third
SymFET is grounded, wherein the back gate of the fourth SymFET is
supplied with the drain voltage, wherein a first conductor extends
between the first and second SymFETs and a second conductor extends
between the third and fourth SymFETS, wherein the first and second
conductors are coupled to one another at which point the output
voltage is measured.
9. A Boolean logic device of claim 1 wherein the at least two
SymFETs define a first SymFET and a second SymFET, the Boolean
logic device further comprising: a third SymFET and a fourth
SymFET, with the third and fourth SymFETs including a top gate, a
back gate, an insulator, a first graphene layer, a second graphene
layer, a first oxide layer, and a second oxide layer, the insulator
being disposed between the first and second graphene layers, the
first and second graphene layers being disposed between the first
and second oxide layers, the first and second oxide layers being
disposed between the top and back gates, wherein a first conductor
extends between the first and fourth SymFETs and a second conductor
extends between the second and third SymFETs, with the first and
second conductors being coupled, the output voltage taken from the
first and second conductors, wherein a clocked input voltage is
supplied to the third and fourth SymFETs and a drain voltage is
supplied to the back gates of the third and fourth SymFETs, wherein
a first bias voltage is supplied to a back gate of the first
SymFET, and a second bias voltage is supplied to a top gate of the
third SymFET, wherein the input voltage is supplied to the top gate
of the first SymFET, wherein outputs of the first and second
SymFETs are grounded, wherein the top and back gates of the second
SymFET are grounded, wherein the top gate of the fourth SymFET is
coupled to the first conductor.
10. A Boolean MAJORITY gate comprising: a first SymFET including a
top gate, a back gate, an insulator, a first graphene layer, a
second graphene layer, a first oxide layer, and a second oxide
layer, the insulator being disposed between the first and second
graphene layers, the first and second graphene layers being
disposed between the first and second oxide layers, the first and
second oxide layers being disposed between the top and back gates;
a second SymFET including a top gate, a back gate, an insulator, a
first graphene layer, a second graphene layer, a first oxide layer,
and a second oxide layer, the insulator being disposed between the
first and second graphene layers, the first and second graphene
layers being disposed between the first and second oxide layers,
the first and second oxide layers being disposed between the top
and back gates; a third SymFET including a top gate, a back gate,
an insulator, a first graphene layer, a second graphene layer, a
first oxide layer, and a second oxide layer, the insulator being
disposed between the first and second graphene layers, the first
and second graphene layers being disposed between the first and
second oxide layers, the first and second oxide layers being
disposed between the top and back gates; a first input supplying a
first voltage to the first SymFET; a second input supplying a
second voltage to the second SymFET; and a third input supplying a
third voltage to the third SymFET, wherein the first, second, and
third SymFETs are configured to be in parallel in a circuit.
11. A Boolean MAJORITY gate of claim 8 further comprising a fourth
input supplying a bias voltage to the top and back gates of the
first, second, and third SymFETs.
12. A Boolean logic latch comprising: a first SymFET including a
top gate, a back gate, an insulator, a first graphene layer, a
second graphene layer, a first oxide layer, and a second oxide
layer, the insulator being disposed between the first and second
graphene layers, the first and second graphene layers being
disposed between the first and second oxide layers, the first and
second oxide layers being disposed between the top and back gates;
a second SymFET including a top gate, a back gate, an insulator, a
first graphene layer, a second graphene layer, a first oxide layer,
and a second oxide layer, the insulator being disposed between the
first and second graphene layers, the first and second graphene
layers being disposed between the first and second oxide layers,
the first and second oxide layers being disposed between the top
and back gates; a first input supplying a first voltage to the
first SymFET; a second input supplying a second voltage to the
second SymFET; and a third input supplying a bias voltage to the
top and back gates of the first and second SymFETs, wherein the
first and second SymFETs are configured to be in parallel in a
circuit.
13. A Boolean logic latch of claim 12 further comprising an
inverter between the second input and the second SymFET.
Description
FIELD OF THE DISCLOSURE
[0001] The present disclosure relates generally to the field of
low-power information processing hardware and, more specifically,
to devices for utilizing symmetric tunneling field-effect
transistors (SymFETs) for low-power information processing.
BACKGROUND OF RELATED ART
[0002] In the pursuit of low-power information processing hardware,
many new post-complementary metal-oxide-semiconductor (CMOS)
transistors have been created in the past few decades. One
desirable property for these new devices is a large on-current to
off-current ratio, which enables low-power, low-voltage operation.
Initial studies and experiments on a class of emerging field effect
transistor (FET) technologies that operate upon the principle of
tunneling between 2-D materials have indicated their potential for
low-power operation. However, current-voltage characteristics (or
"I-V curves") of these devices appear to be dissimilar to those of
today's metal-oxide-semiconductor field-effect transistors
(MOSFETs), and instead exhibit bell-curve characteristics. Further,
double-layer graphene transistors, such as SymFETs, and bilayer
pseudo-spin FETs (BiSFETs) may all possess at least some of the
aforementioned characteristics. Such behavior is also observed in
some molecular transistors and single-electron transistors. To
date, though, little if any work has considered how such devices
might be employed for the purposes of digital logic, which will
ultimately help to determine the "fate" of these new device
technologies. For example, scientists have not yet described how to
leverage the use of SymFETs in sequential circuits. Therefore, it
is both important and desirable to utilize new SymFET-based devices
that are superior to CMOS designs with regards to compactness,
speed, and/or energy efficiency.
[0003] Until now, little has been done in the way of designing
circuits comprised of SymFETs and other devices with similar
graphene-insulator-graphene structures. New topologies involving
such devices can benefit from unique I-V curves. Known attempts to
incorporate graphene-insulator-graphene structures to date have not
proven helpful. For example, one recent gate design uses BiSFETs at
a supply voltage of 25 millivolts (mV), but a 25 mV supply is
likely to prove challenging when considering supply, substrate, and
device noises, where, in practice, the ripple on supply rails often
amounts to a few tens of mV. On the other hand, some researchers
have proposed a static random-access memory (SRAM) cell without
access transistors. Due to the negative differential resistance
(NDR) of that device, the circuit is bistable while having only two
transistors as opposed to four in a similar CMOS SRAM cell.
[0004] Therefore, a need exists for several new Boolean gates that
are practical and take advantage of unique I-V curves. Even simple
gates, such as an inverter, for example, exhibit new properties
(i.e., hysteresis) when realized by way of SymFETs. The present
disclosure concerns several new circuits with a topology different
from those of popular CMOS designs. To quantify the performance of
these new SymFET-based gates and determine their potential
benefits, the present disclosure benchmarks these gates against
existing CMOS-functional equivalents. The present disclosure also
examines the relationship between SymFET and resonant tunneling
diodes (RTDs) to verify the feasibility of adopting RTD-based
circuits. In turn, the present disclosure will aid in developing
new circuits with other SymFET-like transistors and also assist in
improving future transistors.
BRIEF DESCRIPTION OF THE DRAWINGS
[0005] FIG. 1A is an exploded graphic perspective view of an
example SymFET.
[0006] FIG. 1B is a circuit diagram of the example SymFET of FIG.
1A.
[0007] FIG. 2 is a chart plotting current against voltage for
various voltages applied to top and back gates of the example
SymFET of FIGS. 1A-1B.
[0008] FIG. 3A is a circuit diagram of an example SymFET-based
inverter.
[0009] FIG. 3B is chart showing voltage in/out signals of the
example SymFET-based inverter of FIG. 3A when loaded by a
fanout-of-4 (FO4) inverter at V.sub.DD=0.3 V.
[0010] FIGS. 4A-4C together are a series of charts showing the
variation in currents at first and second transistors T.sub.1,
T.sub.2 of the example SymFET-based inverter of FIG. 3A where
V.sub.DD=0.3 V, with quiescent points shown by a star, along with a
chart in FIG. 4D plotting the transfer characteristics of the
SymFET-based inverter of FIG. 3A.
[0011] FIGS. 5A-5C together are a series of charts showing the
variation in currents at first and second transistors T.sub.1,
T.sub.2 of the example SymFET-based inverter of FIG. 3A where
V.sub.DD=0.5 V, with quiescent points shown by a star, along with a
chart in FIG. 5D plotting the transfer characteristics of the
SymFET-based inverter of FIG. 3A.
[0012] FIG. 6A shows a circuit diagram for an example
Schmitt-trigger inverter.
[0013] FIG. 6B shows a chart plotting the drain current of a first
transistor T.sub.1 of the example Schmitt-trigger inverter against
the same current based on the example SymFET-based inverter of FIG.
3A.
[0014] FIG. 6C shows a chart indicating the transfer
characteristics of the example Schmitt-trigger inverter for
V.sub.DD=0.3 V.
[0015] FIG. 7A is a circuit diagram of an example SymFET-based
buffer.
[0016] FIG. 7B is a chart plotting voltage out against voltage in
for the example SymFET-based buffer of FIG. 7A.
[0017] FIG. 8A is a circuit diagram of another example SymFET-based
buffer designed to eliminate or at least minimize hysteresis.
[0018] FIG. 8B is a chart plotting voltage out against voltage in
for the example SymFET-based buffer of FIG. 8A.
[0019] FIG. 9A is a circuit diagram of an example SymFET-based NAND
gate.
[0020] FIG. 9B is a circuit diagram of a pseudo-SymFET logic style
gate.
[0021] FIG. 9C is a chart plotting the I-V curve of the
pseudo-SymFET logic style gate of FIG. 9B, where a nonlinear load
resistance was implemented by SymFET.
[0022] FIG. 9D is a circuit diagram of an example pseudo-SymFET OR
gate.
[0023] FIGS. 9E-9F together show input and output charts, where the
output of a pseudo-SymFET NOR gate is compared with the output of a
gate with linear resistive load (i.e., V.sub.DD=0.4 V; size of a
third transistor T.sub.3 is twice that of first and second
transistors T.sub.1, T.sub.2; load is a FO4 inverter).
[0024] FIG. 10A is a circuit diagram of a dynamic pseudo-SymFET NOR
gate.
[0025] FIGS. 10B-10D together show the simulated input/output of a
NOR gate, where the size of T.sub.3 is three times that of first
and second transistors T.sub.1, T.sub.2 and the load is a FO4
inverter.
[0026] FIG. 11A is a circuit diagram for a SymFET-based IMPLY
gate.
[0027] FIG. 11B is a circuit diagram for a CMOS-based IMPLY
gate.
[0028] FIG. 11C shows a corresponding truth table applicable to
both the SymFET- and CMOS-based IMPLY gates of FIGS. 11A-11B.
[0029] FIGS. 11D-11F together show several charts plotting input
and output for the respective SymFET- and CMOS-based IMPLY gates of
FIGS. 11A-11B.
[0030] FIG. 12A is a circuit diagram of an example NAND-based XOR
gate.
[0031] FIG. 12B is a circuit diagram of an example IMPLY-based XOR
gate.
[0032] FIG. 13A is a circuit diagram of an example resistive
network, which serves as the basis for a MAJORITY gate.
[0033] FIG. 13B is a circuit diagram of an example SymFET-based
MAJORITY gate.
[0034] FIG. 13D is a corresponding truth table for the example
SymFET-based MAJORITY gate of FIG. 13B.
[0035] FIGS. 13D-13E together show an input voltage chart and an
output voltage chart based on the example SymFET-based MAJORITY
gate of FIG. 13B.
[0036] FIG. 13F is a chart plotting the absolute values of current
versus voltage for a nonlinear SymFET-based resistor.
[0037] FIG. 13G is a chart plotting total current versus voltage
for the example SymFET-based MAJORITY gate of FIG. 13B.
[0038] FIG. 14 is an exploded graphic perspective view of an
example diode-connected SymFET.
[0039] FIG. 15 is a circuit diagram of an example full adder
cell.
[0040] FIG. 16A is a circuit diagram of an example SymFET-based
reset/set (RS) latch.
[0041] FIG. 16B is a model showing how two transistors of the
example SymFET-based RS latch of FIG. 16A are being used.
[0042] FIG. 16C is a chart plotting the current through a first and
second transistor T.sub.1, T.sub.2 of the example SymFET-based RS
latch of FIG. 16A against output voltage when A=0 and
B=V.sub.DD.
[0043] FIG. 16D is a truth table of the example SymFET-based RS
latch of FIG. 16A.
[0044] FIG. 17A is a circuit diagram of an RS latch with an
inverter.
[0045] FIG. 17B is a truth table for the RS latch of FIG. 17A.
[0046] FIG. 17C is a circuit diagram for a conventional RS latch
having eight transistors.
[0047] FIGS. 18A-18B show a simulated transient response of the
example SymFET-based RS latch of FIG. 16A.
[0048] FIG. 19A is a circuit diagram of another example
SymFET-based latch.
[0049] FIG. 19B is a truth table for the example SymFET-based latch
of FIG. 19A.
[0050] FIGS. 19C-19E together show several charts plotting current
versus voltage at different input values for a latch without
speedup transistors.
[0051] FIGS. 20A-20C together show input and output voltages for
latches with and without speedup.
[0052] FIGS. 21A-21C together show the I-V curves of transistors
from the example SymFET-based latch of FIG. 19A where
I.sub.D13=I.sub.DS1+I.sub.DS3 and
I.sub.S24=I.sub.SD2+I.sub.SD4.
[0053] FIG. 22A is a circuit diagram of an RTD-like device based on
SymFETs.
[0054] FIG. 22B is a chart plotting the sum of the currents in two
SymFETs T.sub.1, T.sub.2 of the device of FIG. 22A against input
voltage.
[0055] FIG. 23A is a circuit diagram of an RTD-based MOBILE
inverter/DFF.
[0056] FIGS. 23B-23D show several charts plotting current versus
output voltage for a low A input as a clocked input gradually
increases.
[0057] FIG. 24A is a circuit diagram of an example SymFET-based
MOBILE device.
[0058] FIG. 24B is a chart plotting input through the SymFETs
against output voltage of the SymFET-based MOBILE device of FIG.
24A for a high clock input.
[0059] FIG. 24C is a chart similar to FIG. 24B, but shows a
combined current of I.sub.DS1+I.sub.DS2.
[0060] FIGS. 24D-24F together show input/output waveforms of the
example MOBILE circuit of FIG. 24A showing that the output F is
high only if input A is low at the rising edge of the clocked
input.
[0061] FIG. 25A is a chart showing power dissipation of a
SymFET-based inverter at 100 MHz with an FO4 inverter as load.
[0062] FIG. 25B is a chart showing the propagation delay of a
SymFET-based inverter measured from 50% input to 50% output.
[0063] FIG. 25C is a chart illustrating the delay-energy
relationship at different supply voltages.
[0064] FIG. 25D is a chart showing energy dissipation of
SymFET-based inverters (squares) in comparison with that of
CMOS-based inverters at 100 MHz.
DETAILED DESCRIPTION
[0065] The following description of example devices is not intended
to limit the scope of the description to the precise form or forms
detailed herein. Instead the following description is intended to
be illustrative so that others may follow its teachings.
Device Description and Model
[0066] FIG. 1A shows a physical structure of an example SymFET 100
along with an electrical diagram 102 in FIG. 1B representing the
example SymFET 100. In some examples, operation of the SymFET 100
shown in FIGS. 1A-1B is summarized as follows. Tunneling occurs
between two example graphene layers 104, 106 separated by an
example thin insulator 108. The voltages associated with an example
top-gate (TG) 110, which is disposed above an example first oxide
layer 112, and an example back-gate (BG) 114, which is disposed
below an example second oxide layer 116, change the carrier
type/density of the graphene layers 104, 106 by electrostatic
field. In the example, shown in FIGS. 1A-1B, the graphene layer 104
is associated with a source 118, while the graphene layer 106 is
associated with a drain 120. Because tunneling probability depends
on occupied/empty states on both sides of the tunneling barrier,
voltages of the top and back gates 110, 114 can modulate the
drain-source current (I.sub.DS). In addition, FIG. 2 illustrates
I-V characteristics 200 of the example SymFET 100 shown in FIGS.
1A-1B under various load conditions. Peak currents for each
respective I.sub.DS-drain-source voltage (V.sub.DS) curve depend on
the voltages at the top and back gates 110, 114.
[0067] To build a tabular representation of I.sub.DS in terms of
the terminal voltages for a device constructed with undoped
graphene sheets, the present disclosure employs the
previously-published analytical models described in P. Zhao et al.,
"SymFET: A Proposed Symmetric Graphene Tunneling Field-Effect
Transistor," IEEE Trans. Electron Devices, vol. 60, no. 3, pp.
951-957 (March 2013), R. M. Feenstra et al., "Single-particle
tunneling in doped graphene-insulator-graphene junctions," J. Appl.
Phys., vol. 111, no. 4, p. 043711 (April 2012), and S. C. de la
Barrera et al., "Theory of graphene-insulator-graphene tunnel
junctions," J. Vac. Sci. Technol. B, vol. 32, 04E101, (July/August
2014), all of which are hereby incorporated by reference in their
entireties. The results are incorporated in a Verilog-A model such
that the 4-terminal device can be used in simulation program with
integrated circuit emphasis (SPICE) simulations.
[0068] In some examples, the device capacitances are constant and
are based on planar capacitance between the TG 110 and the source
118, between the BG 114 and the drain 120, and between the drain
120 and the source 118. Moreover, in the examples disclosed below,
both the TG 110 and the BG 114 have an effective oxide thickness
(EOT) of 1.2 nanometers (nm). In some examples, the thin insulator
108 acting as a tunneling barrier is comprised of 1.34 nm-thick
Boron-Nitride (i.e., 4 layers of h-BN). Still further, coherence
length determines what percentage of the graphene layers 104, 106
are structurally perfect. And in these examples, the active device
area is assumed to be a square and the coherence length is 0.75
times the square side. This follows because researchers are
generally limited to large graphene sheets, which prevents
researchers from fully accounting for edge effects. Therefore,
unless otherwise stated, the minimum-size transistor in the
examples below has been conservatively selected to be 100 nm-by-100
nm, though considerations for scaling to smaller dimensions are
also disclosed below.
[0069] Yet further, those having ordinary skill in the art will
recognize that the aforementioned design parameters are merely
examples and that the characteristics of the disclosed devices may
vary. For instance, in some examples the disclosed devices may be
asymmetric with no BG, even though N-type and P-type transistors
may be required. In other words, to achieve the same
functionalities, a SymFET with a constant V.sub.BG can be replaced
with a device without a BG but with a doped drain (or source).
Inverter/Buffer
[0070] Turning now to FIG. 3A, an example inverter circuit 300
having a first SymFET T.sub.1 and a second SymFET T.sub.2 is shown.
If a bias voltage (V.sub.B) is set close to half of a positive
supply voltage (V.sub.DD) of the second SymFET T.sub.2 (i.e.,
V.sub.DD/2), then for an input voltage (V.sub.in) close to zero the
first SymFET T.sub.1 is off because a top gate voltage (V.sub.TG)
minus a back gate voltage (V.sub.BG) differential is negative
(V.sub.TG-V.sub.BG<0), and the second SymFET T.sub.2 is on. As a
result, an output voltage (V.sub.out) will be close to the positive
supply voltage V.sub.DD of the second SymFET T.sub.2. As shown in a
voltage-time chart 302 in FIG. 3B, a high-level input leads to a
low-level output. FIG. 3B illustrates the relationship between
input and output signals of the example inverter circuit 300 when
loaded by a fanout-of-4 (FO4) inverter at V.sub.DD=0.3 V.
Furthermore, FIGS. 4A-4C illustrate how stable quiescent operating
points 400 and V.sub.out of the example inverter circuit 300 can be
determined using a characteristic of transistors where V.sub.DD is
small. In particular, FIGS. 4A-4C show the respective currents
through T.sub.1 and T.sub.2 at various input voltages V.sub.in when
V.sub.DD=0.3 V. FIG. 4D shows a chart 402 illustrating the transfer
characteristics of the example inverter 300 when V.sub.DD=0.3 V.
The operation of the example inverter circuit 300 is similar to
that of a CMOS inverter. Notably, the current in the off transistor
is not zero, and consequently the output levels will not be equal
to ground and V.sub.DD. This is no problem so long as the noise
margin is sufficiently large, namely, where V.sub.DD is greater
than 0.2 V. Still, the leakage current results in static power
dissipation.
[0071] FIGS. 5A-5D are similar to FIGS. 4A-4D, but show stable
quiescent operating points 500 of the example inverter circuit 300
when V.sub.DD is somewhat higher at 0.5 V. FIGS. 5A-5C show the
respective currents through T.sub.1 and T.sub.2 at various input
voltages V.sub.in when V.sub.DD=0.5 V. When V.sub.in=V.sub.DD/2,
the example inverter circuit 300 becomes bistable due to NDR. More
specifically, when the input signal V.sub.in is close to
V.sub.DD/2, the circuit 300 has two possible outputs for the same
input when V.sub.DD=0.5 V. This condition is also shown in a chart
502 plotting V.sub.out against V.sub.in where V.sub.DD=0.5 V. FIG.
5C, moreover, also shows a third possible, but unstable, point
where I.sub.DS1=I.sub.DS2 when V.sub.in=0.6 V.sub.DD. This point is
unstable because it lies on the NDR region of the I-V curve. The
bistability manifests itself as the hysteresis in the
characteristic of the gate, resulting in a Schmitt-trigger
inverter. For example, when output is high, and V.sub.in is
increasing, the output remains high even for an input close to
V.sub.DD/2. But when input approaches roughly 0.6 V.sub.DD, the
circuit 300 changes from bistable to monostable and the output
V.sub.out toggles to a low level, as shown in the chart 502.
[0072] In some instances, a low-voltage Schmitt-trigger inverter
may be required. Therefore, in some examples, a positive feedback
600 from a BG 602 to a drain 604 can be incorporated into an
example Schmitt-trigger inverter circuit 606 as shown in FIG. 6A.
As shown in an I.sub.out-V.sub.out curve 608 of FIG. 6B, the
feedback 600 brings the current of transistors T.sub.1 and T.sub.2
down at large |V.sub.DS| and makes the I.sub.out-V.sub.out curve
608 similar to that of FIGS. 4A-4C, where Vin=V.sub.DD/2. The
attained hysteresis for a small V.sub.DD of 0.3V is observed in a
chart 610 plotting V.sub.out against V.sub.in in FIG. 6C. As those
having ordinary skill in the art will recognize, the difference
between the example circuit 300 in FIG. 3A and the example circuit
606 in FIG. 6A can be explained when the input is increasing and
just passes V.sub.DD/2. For the circuit 300, the value of
V.sub.TG1-V.sub.BG1=V.sub.in-V.sub.DD/2 becomes positive and hence
I.sub.DS1 becomes larger than I.sub.DS2, whereas for the circuit
606, V.sub.TG-V.sub.BG of T.sub.1 is still negative for
V.sub.in.apprxeq.V.sub.DD/2 as the BG 602 is connected to an output
node 612 coupled to V.sub.out.
[0073] An example buffer 700 is illustrated in FIG. 7A. Compared to
an inverter, the role of TG and BG terminals of transistors T.sub.1
and T.sub.2 are interchanged in the example buffer 700. The buffer
700 can also exhibit hysteresis in its characteristic, as shown in
a chart 702 plotting V.sub.out against V.sub.in. If the hysteresis
is undesirable, an example circuit 800 shown in FIG. 8A may be used
instead. In the example circuit 800, added negative feedback 802
eliminates the bistability evident in the example buffer 700. A
chart 804 plotting V.sub.out against V.sub.in demonstrates that the
example circuit 800 does not involve hysteresis. Further, those
having ordinary skill in the art will recognize that with static
CMOS logic it is not possible to construct circuits similar to
those illustrated in FIGS. 7A and 8A. As a result, two inverters
are often cascaded to build a buffer.
NAND/NOR/IMPLY
[0074] An example NAND gate 900 is shown in FIG. 9A. Although the
example NAND gate 900 provides desirable functionality, it is not
any less complex than its static CMOS counterpart. That said, more
compact gates are made possible by using the nonlinear behavior of
SymFETs to build pseudo-SymFET gates (similar to pseudo-nMOS style
logic).
[0075] In FIG. 9B, an example SymFET 902 with feedback 904 is used
as the load. When compared with the conventional NAND gate 900
shown in FIG. 9A using conventional logic, the SymFET 902 using
pseudo-SymFET logic lowers the number of transistors required. For
instance, if a conventional static CMOS circuit has N transistors,
a pseudo-SymFET circuit will only require (N/2)+1 transistors.
Further, the input capacitance of the gate is also cut by one half.
The benefit of using a SymFET load compared with a linear resistor
can be explained by way of an I-V curve 906 having a bell-curve
shape 908 shown in FIG. 9C. In this example, the current passing
through the device will be small (close to I.sub.v1) for a low
output level. In contrast, for a resistor, the current will be the
largest when the output of the gate is low, resulting in large
leakage. Similarly, in pseudo-N-type metal-oxide-semiconductor
(pseudo-NMOS) circuits, the current is the largest when the output
signal is low, since MOSFETs do not have NDR.
[0076] An example pseudo-SymFET NOR gate 910 having three SymFETs
T.sub.1, T.sub.2, and T.sub.3 is shown in FIG. 9D. If the third
SymFET T.sub.3 is replaced with a 200 k.OMEGA. resistor, a similar
output DC level and swing is achieved as depicted in FIGS. 9E-9F.
However, the average power dissipation when using SymFET and
resistive loads is 0.16 .mu.W and 0.51 .mu.W, respectively, for the
input waveform shown in FIGS. 9E-9F. Hence, there is more
significant leakage when a resistor is employed. More significant
improvements with respect to power would be possible if I.sub.v1
was reduced. However, a small I.sub.v1 also has an adverse effect,
namely, when the output changes from low to high, the load
capacitance is initially charged with a current of
.apprxeq.I.sub.v1. This results in a slow rise time as seen in
FIGS. 9E-9F, wherein the low-to-high delay with the SymFET-based
and resistor-based loads is 1.6 ns and 0.46 ns, respectively.
[0077] To enhance the speed of the pseudo-SymFET gates, one might
think to increase the size of the load transistor to have a larger
I.sub.v1. However, this could result in an incorrect output because
the pull-down network might not be able to bring the output voltage
down from a high state. Instead, in some examples a clocked-supply
is used, as in resistance thermometer detector (RTD)-based
circuits. The resulting circuit, which is referred to herein as
"dynamic pseudo-SymFET logic" 1000 and includes three SymFETs
T.sub.1, T.sub.2, and T.sub.3, is shown in FIG. 10. In this
example, an output signal is reset to zero during each clock cycle.
The delay of the dynamic pseudo-SymFET circuit 1000 is reduced to
0.39 ns, whereas the power consumed from a clock input CLK is 0.12
.mu.W. As shown in FIGS. 10B-10D, if the size of the third SymFET
T.sub.3 is three times that of the first and second SymFETs T.sub.1
and T.sub.2, the pseudo-SymFET NOR gate 910 of FIG. 9D can produce
a wrong output, but the dynamic pseudo-SymFET gate 1000 functions
correctly. Besides a larger third SymFET T.sub.3, another aspect of
the dynamic pseudo-SymFET logic 1000 helps improve the rise time of
the circuit. More specifically, as the clock input CLK is rising,
an output node is simultaneously being charged. When the clock
input CLK reaches V.sub.DD, the output voltage is somewhat higher
than zero, and |V.sub.DS3|=V.sub.R is smaller than V.sub.DD. As a
result, I.sub.DS3 will be larger than I.sub.v1 (see, e.g., FIG.
9C). Subsequently, the output node will be charged by a current
larger than that of FIG. 9D.
[0078] The IMPLY gate is another universal gate besides NAND and
NOR that may be implemented with SymFETs. To that end, FIG. 11A
shows an example IMPLY gate 1100 implemented by way of first and
second SymFETs T.sub.1 and T.sub.2, whereas FIG. 11B shows an
example IMPLY gate 1102 based on CMOS elements. In both circuits,
an output F can be low only when A is high and B is low, and
therefore the first SymFET T.sub.1 is on, as reflected in a truth
table 1104 of FIG. 11C. However, unlike the SymFET-based IMPLY gate
1100, the CMOS-based IMPLY gate 1102 has a shortcoming that often
precludes its usage. Specifically, when A is high and B transitions
from low to high, the charging of the output capacitive load is
performed via a CMOS transistor T.sub.1 in FIG. 11B. Moreover, as F
increases and approaches V.sub.DD V.sub.TH (i.e., where V.sub.TH is
the threshold voltage), the CMOS transistor T.sub.1 is almost
turned off, causing incomplete settling. By contrast, the
SymFET-based IMPLY gate 1100 of FIG. 11A does not have this problem
because it does not have a large V.sub.TH. This much is
demonstrated in FIGS. 11D-11F, where the functionality of the
SymFET-based IMPLY gate 1100 at a V.sub.DD of 0.3 V, and 130-nm
CMOS-based IMPLY gate 1102 at a V.sub.DD of 1 V are examined. In
short, the SymFET-based IMPLY gate 1100 does not have this
disadvantage inherent with the CMOS-based IMPLY gate 1102. One
advantage of the example SymFET-based IMPLY gate 1100 is its fewer
transistors in comparison with NAND or NOR gates. Traditional
realization of IMPLY gates requires an inverter and a NAND gate,
amounting to six transistors. For instance, two XOR gates 1200,
1202 are shown in FIGS. 12A-12B. The realization using the
NAND-based design in FIG. 12A has sixteen transistors, whereas the
IMPLY-based design in FIG. 12B has eight transistors.
MAJORITY Gate
[0079] Another useful gate that is popular at least in the context
of cellular automata and spintronics is the MAJORITY gate. It is
possible to construct a SymFET-based MAJORITY gate with as few as
three devices. The starting point for the SymFET-based MAJORITY
gate is an example resistive network 1300 shown in FIG. 13A. If
C.sub.in1=V.sub.in2=0 V and V.sub.in3=V.sub.DD in the example
resistive network 1300, the output voltage V.sub.out will be as
follows:
V.sub.out=V.sub.DD(R.sub.1.parallel.R.sub.2)/[(R.sub.1.parallel.R.sub.2)-
+R.sub.3]V.sub.DD/3
[0080] To convert the circuit into a MAJORITY gate for this input
combination, the output voltage level V.sub.out should be brought
close to zero. The voltage across R.sub.1 and R.sub.2 is smaller
than that of R.sub.3, and if resistors are replaced with nonlinear
elements whose resistances increase with voltage, R.sub.3 will
become larger than R.sub.1 and R.sub.2 and the output V.sub.out
will be pushed toward ground. An example SymFET-based circuit 1302
of FIG. 13B is designed for this purpose. If input levels are 0 and
V.sub.DD, both gates of first, second, and third SymFETs T.sub.1,
T.sub.2, T.sub.3 are set to V.sub.B=V.sub.DD/2 (see the case of
V.sub.TG=V.sub.BG in FIG. 2 for the I-V curve of the device). The
transient response of the example SymFET-based circuit 1302 when
loaded with an FO4 inverter is shown in FIGS. 13D-13E. When both
V.sub.inB and V.sub.inC are zero, an output F is also zero
independent of input V.sub.inA. Moreover, V.sub.inA changes the
output F when one and only one of the V.sub.inB or V.sub.inC inputs
is high. Here, each of the transistors T.sub.1, T.sub.2, T.sub.3
behaves like a symmetric nonlinear resistor with an
I.sub.DS-V.sub.DS curve 1304 like that illustrated in FIG. 13F. If
V.sub.inA=V.sub.inB=V.sub.inC=0 V, the output F will be zero since
there is no path to charge the output F. Similarly when all of the
inputs V.sub.inA, V.sub.inB, and V.sub.inC are set to V.sub.DD, the
output voltage F will equal V.sub.DD as well. In another example,
if the inputs V.sub.inA=V.sub.inB=0 V and V.sub.inC=V.sub.DD (i.e.,
001), T.sub.3 has a large |V.sub.DS|, and a large resistance as
seen in FIG. 13F.
[0081] Further, FIG. 13G provides still more insight as to the
operation of the example SymFET-based circuit 1302. FIG. 13G shows
a total current 1306 discharging an output node
(I.sub.SD1+I.sub.SD2=2.times.I.sub.SD1) and a current 1308 charging
the output (I.sub.DS3). An intersection 1310 of the two curves
1306, 1308 gives the output voltage F, which is close to zero as
desired. The quiescent current of the transistors T.sub.1, T.sub.2,
T.sub.3 is I.sub.SD1=I.sub.SD2.apprxeq.I.sub.v1/2 and
I.sub.DS3.apprxeq.I.sub.v1. Even though a small I.sub.v1 is ideal
with respect to power dissipation considerations, the two curves
should not have more than one intersection for correct operation.
This means that in most examples I.sub.v1 will be greater than
I.sub.pk/2.
[0082] An example diode-connected SymFET 1400 (e.g., where the TG
and the BG are shorted, respectively, to the drain and the source)
may in some instances exhibit the same behavior as shown in FIG.
13F. This in turn eliminates the need for V.sub.inB. Even a single
graphene-insulator-graphene junction without any gate exhibits this
characteristic, and hence the example diode-connected SymFET 1400
of FIG. 14 can be utilized as a MAJORITY gate.
[0083] Combining inverters and MAJORITY gates enables the creation
of an example full adder cell 1500, as shown in FIG. 15. The
outputs of the MAJORITY gates are buffered to isolate the gates
from each other. The example full adder cell circuit 1500 is
designed to be cascadable by providing output carry (C.sub.o) and
its inverted signal (C.sub.o). The example full adder cell circuit
1500 has fifteen transistors in total as opposed to twenty-eight in
a conventional CMOS adder cell such as the Mirror Adder.
[0084] The next few topologies for sequential circuit design
utilizing SymFETs can offer low transistor count and low dynamic
power dissipation.
RS Latch
[0085] FIG. 16A shows an example SymFET-based reset/set (RS) latch
1600 that includes two-transistor circuits T.sub.1 and T.sub.2.
Here, two SymFETs T.sub.1 and T.sub.2 are used like nonlinear
resistors R.sub.1 and R.sub.2 as shown in a circuit 1602 of FIG.
16B. If inputs A and B in FIG. 16B have the same logic level, an
output F will have the same level, independent of whether the
resistors R.sub.1 and R.sub.2 are linear or nonlinear. If one input
(e.g., A) is low and the other one (e.g., B) is high, the circuit
1602 is bistable and, as shown in a chart 1604 in FIG. 16C, has two
stable quiescent points 1606, 1608. I-V curves 1610, 1612 of the
two transistors T.sub.1, T.sub.2 have three intersections, one
intersection 1614 of which is unstable because it lies on an NDR
region of the I-V curves 1610, 1612. As a result, the output
voltage F can be either low or high when one and only one of the
two inputs A, B is high, and is determined by its previous
state.
[0086] A truth table 1616 of the example SymFET-based RS latch 1600
is represented in FIG. 16D, where "F*" refers to the previous "F"
value. The truth table 1616 of the SymFET-based RS latch 1600
resembles that of a latch. In fact, adding an inverter 1700 to the
SymFET-based RS latch 1600 of FIG. 16A results in an RS latch 1702
as shown in FIG. 17A that is known in the art. A truth table 1704
corresponding to the RS latch 1702 is shown in FIG. 17B. In
addition, FIG. 17C shows a conventional RS latch 1706, which has
eight transistors. By way of comparison, the example SymFET-based
RS latch 1600 has only four transistors. A simulated transient
response 1800 of the example SymFET-based RS latch 1600 is shown in
FIGS. 18A-18B, where a 10%-to-90% rise time is 0.8 ns.
Latch 2
[0087] FIG. 19A shows another example SymFET-based latch 1900, with
a corresponding truth table 1902 in FIG. 19B. First and second
transistors T.sub.1, T.sub.2 form a core part of the example
SymFET-based latch 1900, whereas third and fourth transistors
T.sub.3, T.sub.4 are used primarily to speedup the example
SymFET-based latch 1900. As shown in the truth table 1902, the
SymFET-based latch 1900 has three valid input combinations,
although a combination where R=0 and S=1 is not allowed. Operation
of the SymFET-based latch 1900 (without speedup) can be explained
using FIGS. 19C-19E. For example, if R=S=0, then the first
transistor T.sub.1 is off and the second transistor T.sub.2 is on.
Consequently, output capacitance is charged, and a final output
voltage V.sub.Q is close to V.sub.DD. Further, if R=1 and S=0, the
SymFET-based latch 1900 is bistable. Depending on the previous Q,
the output voltage V.sub.Q can be either low or high.
[0088] FIGS. 20A-20C shows transient simulation results 2000 of the
SymFET-based latch 1900 without the speedup transistors T.sub.3,
T.sub.4. The transient simulation results 2000 reveal large rise
and fall times. The reason behind the large rise and fall times is
the small charge and discharge current. For instance, consider a
case where output is initially low and then input is set to R=S=0.
The output capacitance must be charged, but the charging current
(i.e., the difference between the currents of T.sub.1 and T.sub.2
(I.sub.2-I.sub.1 in FIGS. 19C-19E)) is small for a large range of
output voltages.
[0089] To accelerate the transient response of the SymFET-based
latch 1900, the third and fourth transistors T.sub.3, T.sub.4 are
employed. In some examples, the BGs of the third and fourth
transistors T.sub.3, T.sub.4 are connected to their respective
source terminals, and therefore V.sub.TG3-V.sub.BG3 is larger than
V.sub.TG1-V.sub.BG1 for high-level R. This shifts the peak current
of an I.sub.DS-V.sub.DS curve of the third transistor T.sub.3 to a
higher V.sub.DS. The sum currents I.sub.DS1+I.sub.DS3 and
I.sub.SD2+I.sub.SD4 will have two peaks, as shown in FIGS. 21A-21C.
Comparing FIGS. 19C-19E (i.e., the I-V curve of the first and
second transistors T.sub.1 and T.sub.2 with no speedup transistors)
and FIGS. 21A-21C (i.e., the I-V curve of transistors where
I.sub.D13=I.sub.DS1+I.sub.DS3 and I.sub.S24=I.sub.SD2+I.sub.SD4)
shows that operation of the SymFET-based latch 1900 after adding
the speedup transistors T.sub.3, T.sub.4 does not change in
principle. The main difference is that charge and discharge
currents will be higher. In the aforementioned example, wherein an
output node was supposed to be charged, adding the fourth
transistor T.sub.4 increases the charging current from
I.sub.2-I.sub.1 to I.sub.24-I.sub.1 at certain output voltages
(i.e., I.sub.24=I.sub.2+I.sub.4). On average, the charge current is
significantly larger. The effect of speedup transistors can also
been in FIGS. 20A-20C, where the rise time of the SymFET-based
latch 1900 is reduced from 5.1 ns to 0.83 ns after adding speedup
transistors.
Mobile DFF
[0090] Furthermore, some features of SymFETs resemble that of
resistance temperature detectors (RTDs), and SymFETs can achieve
RTD-like behavior. FIG. 22A shows an example circuit 2200 built by
placing two SymFETs T.sub.1, T.sub.2 in parallel. As such, the
current passing through the circuit 2200 is the sum of the currents
in the first and second SymFETs T.sub.1, T.sub.2. FIG. 22B shows a
chart 2202 plotting input current I.sub.i against input voltage
V.sub.i. In this example, each of the transistors T.sub.1, T.sub.2
contributes to peaks 2204, 2206 in a total current 2208 and an
N-shaped curve expected from an RTD is obtained for a properly
designated voltage range. Those having ordinary skill in the art
will appreciate that the shape of total current curve 2208 can be
tuned by adjusting the bias voltages V.sub.B1, V.sub.B2 in the
circuit 2200.
[0091] That said, there are still other ways to achieve this
functionality without replacing an RTD with two SymFETs. By way of
example, one of the most popular RTD-based logic elements is a
monostable-bistable transition logic element (MOBILE). MOBILEs have
a self-latching property. For instance, a circuit 2300 shown in
FIG. 23 works both as an inverter and as an edge-triggered
flip-flop (DFF). The example circuit 2300 includes a switch 2302,
implemented by a transistor, and three RTDs D.sub.1, D.sub.2, and
D.sub.3, which should be properly sized such that their peak
currents satisfy the following conditions:
I.sub.pk2<I.sub.pk3 and I.sub.pk1+I.sub.pk2>I.sub.pk3.
[0092] In this example, operation of the circuit 2300 relies
heavily on NDR regions of the three RTDs D.sub.1, D.sub.2, and
D.sub.3, as reflected in charts 2304, 2306, 2308 of FIGS. 23B-23D.
When a clock input CLK is a small voltage, the circuit 2300 is
monostable and an output F is low. As the clock input CLK increases
(e.g., from much less than V.sub.DD to 2.times.V.sub.pk to V.sub.DD
shown in FIGS. 23B-23D), a driving current curve
(I.sub.D1+I.sub.D2) will intersect with a load current curve
(I.sub.D3) in an NDR region, resulting in metastability. When the
clock input CLK becomes high enough, the output reaches one of two
stable points. The example shown in FIGS. 23B-23D corresponds to a
low A (e.g., I.sub.D1=0) and a high final output voltage.
[0093] Still further, an example SymFET-based MOBILE 2400 is shown
in FIG. 24A. A first SymFET T.sub.1 acts as both the switch A and
the first RTD D.sub.1 from FIG. 23A. Moreover, a fourth SymFET
T.sub.4 may be omitted in some examples, but utilized in others.
The fourth SymFET T4 helps to discharge the output faster when a
clock input CLK switches from high to low. Proper operation of the
example SymFET-based MOBILE circuit 2400 depends on sizing of the
first, second, and third SymFETs T.sub.1, T.sub.2, T.sub.3 as well
as bias voltages (V.sub.B1-2). In some examples, there are many
ways to satisfy the conditions that I.sub.pk2<I.sub.pk3 and that
I.sub.pk1+I.sub.pk2>I.sub.pk3. In the example SymFET-based
MOBILE 2400 here, the second and third SymFETs T.sub.2, T.sub.3 are
minimum-size transistors, while in other examples they may be
larger. Nonetheless, when input is low, I.sub.DS1 is negligible.
V.sub.DD-V.sub.B2 is positive (0.3 V), but the gate voltages of the
second SymFET T.sub.2 are both grounded. This insures that a peak
current of the second SymFET T.sub.2 is smaller than that of the
third SymFET T.sub.3 as desired (I.sub.pk2<I.sub.pk3). Further,
V.sub.B1 is selected to be V.sub.IH-0.3 V so that the gate
differential of T.sub.1 and T.sub.3 are equal, when input is high.
The size of the second SymFET T.sub.2 is twice that of the first
SymFET T.sub.1 and, therefore, a peak current of the second SymFET
T.sub.2 is higher than that of the third SymFET T.sub.3. This in
turn insures that a high-level input will result in a low-level
output. FIGS. 24B and 24C show current through the SymFETs of the
MOBILE circuit 2400 for a high clock input CLK (e.g., equal to
V.sub.DD=1 V). The SymFET-based MOBILE circuit 2400 is bistable for
both input logic levels.
[0094] With reference now to FIGS. 24D-24F, input/output waveforms
2402 of the example MOBILE circuit 2400 are shown. Input levels
have been selected to be 0.1 V and 0.7 V, similar to worst-case
output levels. Those having ordinary skill in the art will
understand that altering A does not change the output, even when
the clock input CLK is high.
Benchmarking
[0095] The quantitative performance of the aforementioned example
SymFET-based gates was evaluated using SPICE simulations. As shown
below, Table I compares the metrics of several inverters and
buffers in terms of peak-to-peak output swing (V.sub.o,pp),
propagation delay (T.sub.pd), average dynamic energy per output
switching (E.sub.DYN), and static power dissipation
(P.sub.STAT).
TABLE-US-00001 TABLE I PERFORMANCE OF INVERTERS/BUFFERS V.sub.o,pp
T.sub.pd T.sub.rise, T.sub.fall E.sub.DYN P.sub.STAT Circuit (V)
(ns) (ns) (fJ) (nW) Inv. FIG. 3A 0.25 0.28 0.64 0.13 71 Inv. FIG.
6A 0.19 0.32 0.61 0.1 45 Buf. FIG. 7A 0.17 0.20 1.3 0.08 68 Buf.
FIG. 8A 0.13 0.13 0.85 0.03 120 Inv. FIG. 9D* 0.23 0.91 1.5, 0.83
0.15 68 Inv. FIG. 9A* 0.22 0.29.dagger. 0.7, 0.57
0.12/.07.dagger-dbl. 62 *without T2. .dagger.: from CLK to F (from
A to F for others). .dagger-dbl.: depends on capability of CLK to
absorb power (see the text). Note: all simulations are done with a
FO4 inverter of FIG. 3A as driver and load of the gate under test
at V.sub.DD = 0.3 V (= high level of CLK). Rise/fall times
(T.sub.rise, T.sub.fall) are measured from 10% to 90% of the output
levels.
[0096] Some of the example gates have a smaller output swing (and
hence a smaller noise margin), which results in lower dynamic
energy dissipation. As in CMOS designs, each gate might be suitable
for a certain application. For example, the example inverter of
FIG. 9 has a larger delay compared with that in FIG. 3A, but also
has a smaller input capacitance. In another example, the clocked
inverter of FIG. 10A might be viewed as an adiabatic circuit. That
is, when the clocked input CLK goes low, the charge stored at the
output node F will return back to the value at the clock input CLK
node. Depending on whether the clock input CLK generator circuitry
is capable of absorbing this charge or simply directs it to ground,
two different dynamic energy values are provided in Table I.
[0097] In Table II, the performances of three example SymFET-based
adders based on conventional topology (mirror adder), a dynamic
pseudo-SymFET design, and a MAJORITY gate are compared.
TABLE-US-00002 TABLE II PERFORMANCE OF 1-BIT SYMFET-BASED
FULL-ADDERS T.sub.pd E.sub.DYN P.sub.STAT P.sub.TOT PDP Area* (ns)
(fJ) (.mu.W) (.mu.W) (fJ) (.mu.m.sup.2) Conventional (0.3 V) 1.4
0.4 0.64 0.72 1.0 0.64 Dyn. pseudo-Sym. (0.4 V) 1.1 0.95 0.61 0.8
0.88 0.49 Majority (0.4 V) 0.65 0.37 1.1 1.2 0.78 0.42 *assuming
total area (including wirings) is twice the area of transistors.
Note: In SPICE simulation, a 100 MHz signal is applied to A while B
is Low and Ci is High. The adder is cascaded with a similar
one.
[0098] For the purposes of Table II, a slightly higher supply
voltage is used for the MAJORITY-based adder in order to have the
same output swing in both circuits. The MAJORITY-based adder has a
better power-delay product (PDP) and occupies less area, but has
higher static power dissipation. Those having ordinary skill in the
art will recognize that at this test frequency (i.e., 100 MHz), the
power dissipation is dominated by leakage.
[0099] Likewise, it is informative to benchmark the performance of
SymFET technologies against CMOS technologies. Due to the different
structure of the SymFET, it is non-trivial to select a certain CMOS
technology node for a comparison. In the examples that follow, a
100-nm SymFET device is compared with 90-nm and 130-nm CMOS
technologies. According to a manual of several standard cell
libraries for said technologies, the dynamic energy of the
minimum-size inverter and full-adder cell are, respectively, 4 to 6
fJ and 10 to 20 fJ. The dynamic energy of a CMOS DFF is 20 to 30
fJ. Compared with the E.sub.DYN in Tables I, II, and IV, the
SymFET-based circuits are approximately one order of magnitude more
energy efficient. This is especially impressive for the MOBILE DFF,
which has a delay close to those given for standard cell DFFs
(around 0.1 ns). However, in some examples, the leakage of CMOS
standard cells is smaller (in sub-nW range for low-leakage
CMOS).
[0100] Moreover, an inverter of FIG. 3A was used as a basis for
further comparison. The results shown in FIG. 25 involve a 100-nm
SymFET device and a 130 nm CMOS device. All results belong to a
minimum-size inverter that is both driven and loaded with FO4
inverters. More particularly, FIG. 25A shows power dissipation of a
SymFET-based inverter. The dynamic power dissipation rapidly
changes with supply (cf., CV.sup.2). In this example, a
relationship appears between propagation delay of the SymFET-based
gate and V.sub.DD, shown in FIG. 25B, which is quite different than
the behavior of CMOS inverters. An explanation follows with
reference back to FIG. 2. If V.sub.DD (and consequently the gate
voltage of the transistor) is large, the peak in the I.sub.DS curve
is pushed to higher V.sub.is values. This means that for a large
V.sub.DD, the current drive capability of the SymFET-based inverter
is relatively small in a large output voltage range and the gate
becomes slow. FIG. 25C shows both delay and energy at different
supply voltages. In this example, the SymFET has a better
performance-energy tradeoff, if the desired delay is not
demanding.
[0101] Next, the performance of the inverters is compared at
several technology nodes. The data for CMOS is from A. Stillmaker
et al., "Toward more accurate scaling estimates of CMOS circuits
from 180 nm to 22 nm," Technical Report ECE VCL 2011 4 VLSI
Computation Lab, Univ. of Cali., Davis,
http://www.ece.ucdavis.edu/vcl/pubs, which is hereby incorporated
by reference in its entirety. The SymFET dimensions and other
properties are given in Table III, wherein EOT is also reduced with
device dimension to enhance the electrostatic control of the
gates.
TABLE-US-00003 TABLE III SYMFET SCALING Dimensions Gate Oxide
V.sub.DD Inverter delay 100 nm-by-100 nm EOT = 1.2 nm 0.3 V 0.28 ns
50 nm-by-50 nm EOT = 1.0 nm 0.36 V 0.49 ns 20 nm-by-20 nm EOT = 0.7
nm 0.49 V 1.2 ns
[0102] As the SymFET area is reduced, its characteristic changes
somewhat (off-current increases). To keep the voltage swings in a
practical range (i.e., >0.25 V), the supply voltage (Table III)
was increased. When compared with the CMOS device in FIG. 25D, the
SymFET exhibits more than an order of magnitude improvement in
dynamic energy. One having ordinary skill in the art will recognize
that if operation frequency increases, the impact of leakage in
total energy will be reduced and "Total" energy points will move
toward "Dynamic" energy points. However, it is also possible to
reduce the dynamic energy dissipation of CMOS gates by an order of
magnitude by lowering VDD by a factor of 3.1, where the resulting
VDD of 0.3 to 0.4 V would make their delay larger than that of the
SymFET gates (see FIG. 25C). Consequently, SymFETs prove more
energy efficient than CMOS at least when clock frequencies of a few
hundred MHz and delays on the order of few tenths of nanoseconds
are desired.
[0103] What's more, FIG. 25D indicates that dynamic energy of the
SymFET scales rapidly with device dimension. When the SymFET is
scaled by .lamda. (<1), its area and hence both capacitance and
current drive are reduced by two. Energy and delay are scaled
as
E DYN ( .alpha. C L V SW V DD ) scaled .lamda. 2 E DYN ##EQU00001##
T pd ( .alpha. C L V SW I ON - I OFF ) scaled T pd
##EQU00001.2##
where C.sub.L is the load capacitance, V.sub.SW is the output
swing, and I.sub.ON and I.sub.OFF are the on-current and
off-current of the transistor. The above equation suggests that
delay will not be scaled with technology. Table III shows that
simulated T.sub.ps increases with scaling. This is a consequence of
higher gate capacitance, which is inversely proportional to EOT,
and also lower I.sub.ON-I.sub.OFF attributable to the higher
off-current.
[0104] Yet another tool can be used to modify the performance of
the SymFETs and trade off delay with leakage, namely, the thickness
of the tunneling barrier. In some examples, 1.34 nm BN was used as
discussed in L. Britnell et al., "Field-effect tunneling transistor
based on vertical graphene heterostructures," Science, vol. 335,
no. 6071, pp. 947-950, February 2012, which is hereby incorporate
by reference in its entirety. Further, if fabrication technology
and breakdown voltage of the insulator allow for a thinner barrier,
tunneling current will substantially increase. For instance, if
barrier thickness is reduced to 0.67 nm (i.e., 2 layers of BN),
then delay of the inverter will be reduced by at least 10,000
times, even though the leakage current may increase
proportionally.
[0105] Similar to Tables I and II above, the performance of SymFET
latch and MOBILE DFF devices were also evaluated, as shown in Table
IV below.
TABLE-US-00004 TABLE IV PEFORMANCE OF INVERTERS/BUFFERS V.sub.DD
V.sub.o,pp T.sub.pd E.sub.DYN P.sub.STAT (V) (V) (ns) (fJ) (nW) RS
Latch FIG. 17A 0.5 >0.4 0.41 0.5 270 Latch FIG. 19A 1 0.84 1.8 2
640 Inv./DFF FIG. 24A 1* 0.71 0.06 2.9/0.7.dagger. 480 *high level
of CLK. .dagger.: depends on capability of CLK to absorb power (see
the text). Note: all simulations are done with a FO4 inverter of
FIG. 3A as load.
[0106] Therefore, several new topologies for circuit design
involving SymFETs have proven that they can offer low transistor
count and low dynamic power dissipation. More specifically,
SymFET-based inverters provide a lower switching energy compared
with the iso-delay CMOS-based circuits, due in large part to their
low operating supply voltage.
[0107] Although certain example devices have been described herein,
the scope of coverage of this patent is not limited thereto. On the
contrary, this patent covers all devices, methods, apparatus,
systems, and articles of manufacture fairly falling within the
scope of the appended claims either literally or under the doctrine
of equivalents.
* * * * *
References