U.S. patent application number 14/580836 was filed with the patent office on 2016-06-23 for packaged semiconductor device having attached chips overhanging the assembly pad.
The applicant listed for this patent is Texas Instruments Incorporated. Invention is credited to Reynaldo Corpuz Javier, Alok Kumar Lohia, Andy Quang Tran.
Application Number | 20160181180 14/580836 |
Document ID | / |
Family ID | 56130312 |
Filed Date | 2016-06-23 |
United States Patent
Application |
20160181180 |
Kind Code |
A1 |
Lohia; Alok Kumar ; et
al. |
June 23, 2016 |
PACKAGED SEMICONDUCTOR DEVICE HAVING ATTACHED CHIPS OVERHANGING THE
ASSEMBLY PAD
Abstract
A semiconductor device (200) comprising a semiconductor chip
(201) has an electrically active side (201a) and an opposite
electrically inactive side (201b); the active side bordered by an
edge having a first length (202a), and the inactive side bordered
by a parallel edge having a second length (202b) smaller than the
first length; a substrate has an assembly pad (210) bordered by a
linear edge having a third length (210a) equal to or smaller than
the first length; the inactive chip side attached to the pad so
that the edge of the first length is parallel to the edge of the
third length; the active side of the attached chip forms an
overhang over the pad, when the third length is smaller than the
first length.
Inventors: |
Lohia; Alok Kumar; (Dallas,
TX) ; Javier; Reynaldo Corpuz; (Plano, TX) ;
Tran; Andy Quang; (Grand Prairie, TX) |
|
Applicant: |
Name |
City |
State |
Country |
Type |
Texas Instruments Incorporated |
Dallas |
TX |
US |
|
|
Family ID: |
56130312 |
Appl. No.: |
14/580836 |
Filed: |
December 23, 2014 |
Current U.S.
Class: |
257/676 ;
438/107; 438/126; 438/462 |
Current CPC
Class: |
H01L 21/565 20130101;
H01L 23/4952 20130101; H01L 24/32 20130101; H01L 2924/181 20130101;
H01L 23/49575 20130101; H01L 21/78 20130101; H01L 24/85 20130101;
H01L 2924/10157 20130101; H01L 23/3107 20130101; H01L 25/0657
20130101; H01L 29/0657 20130101; H01L 2924/00014 20130101; H01L
2224/48091 20130101; H01L 2225/0651 20130101; H01L 2924/00014
20130101; H01L 2224/48091 20130101; H01L 2924/10155 20130101; H01L
2224/291 20130101; H01L 23/49548 20130101; H01L 2224/2919 20130101;
H01L 2224/73265 20130101; H01L 2224/73265 20130101; H01L 2924/00
20130101; H01L 2924/00014 20130101; H01L 2924/014 20130101; H01L
2924/00014 20130101; H01L 2224/32145 20130101; H01L 2224/45015
20130101; H01L 2924/207 20130101; H01L 2924/00 20130101; H01L
2224/48247 20130101; H01L 2224/32245 20130101; H01L 2224/48247
20130101; H01L 2924/00014 20130101; H01L 2924/00012 20130101; H01L
2924/0781 20130101; H01L 2224/45099 20130101; H01L 2224/293
20130101; H01L 2924/181 20130101; H01L 2224/2929 20130101; H01L
2224/32245 20130101; H01L 24/48 20130101; H01L 2225/06582 20130101;
H01L 21/4825 20130101; H01L 2924/00014 20130101; H01L 2224/2919
20130101; H01L 23/49513 20130101; H01L 24/29 20130101; H01L 25/50
20130101; H01L 2224/293 20130101; H01L 23/3114 20130101; H01L
2224/48247 20130101; H01L 23/49541 20130101; H01L 2224/291
20130101; H01L 2224/2929 20130101; H01L 2224/32145 20130101; H01L
2225/06555 20130101; H01L 2224/73265 20130101 |
International
Class: |
H01L 23/495 20060101
H01L023/495; H01L 25/00 20060101 H01L025/00; H01L 23/00 20060101
H01L023/00; H01L 21/78 20060101 H01L021/78; H01L 21/56 20060101
H01L021/56 |
Claims
1. A semiconductor device comprising: a semiconductor chip having
an electrically active side and an opposite electrically inactive
side, the active side bordered by an edge having a first length,
the inactive side bordered by a parallel edge having a second
length smaller than the first length; a substrate having an
assembly pad bordered by a linear edge having a third length
smaller than the first length; and the electrically inactive side
attached to the pad, wherein the electrically active side of the
attached chip forms an overhang over pad.
2. (canceled)
3. The device of claim 1 wherein the overhang is along one edge of
the attached chip.
4. The device of claim 1 wherein the overhang is along all four
edges of the attached chip.
5. The device of claim 1 further including terminals surrounding
the assembly pad, wherein the attached chip is connected to
respective terminals by bonding wires.
6. The device of claim 5 wherein the assembly pad and the terminals
are parts of a metal leadframe.
7. The device of claim 5 wherein the assembly pad and the terminals
are metal layers and are integral to a laminated substrate.
8. The device of claim 5 further including a package encapsulating
the chip, the bonding wires, and at least portions of the assembly
pad and terminals.
9. A semiconductor device comprising: a first semiconductor chip
having an electrically active side and an opposite electrically
inactive side, the active side bordered by an edge having a first
length, the inactive side bordered by a parallel edge having a
second length smaller than the first length; a second semiconductor
chip having an electrically active side and an opposite
electrically inactive side, the active side bordered by an edge
having a third length equal to, smaller than, or greater than the
first length, the inactive side bordered by a parallel edge having
a fourth length smaller than the third length; the inactive chip
side of the first chip attached to the active side of the second
chip so that the edge of the first length is parallel to the edge
of the third length; an assembly pad having a top side bordered by
an edge with a fifth length equal to or smaller than the third
length; and the inactive chip side of the second chip attached to
the top pad side so that the edge of the third length is parallel
to the edge of the fifth length, wherein the chips are assembled as
a stack on the pad.
10. The device of claim 9 wherein the third length is equal to or
smaller than the first length and the active side of the attached
first chip forms an overhang over the active side of the second
chip.
11. The device of claim 9 wherein the fifth length is smaller than
the third length and the active side of the attached second chip
forms an overhang over the top pad side.
12. The device of claim 9 further including terminals surrounding
the assembly pad, wherein the attached chips are connected to
respective terminals by bonding wires.
13. The device of claim 12 wherein the assembly pad and the
terminals are parts of a metal leadframe.
14. The device of claim 12 wherein the assembly pad and the
terminals are metal layers and are integral to a laminated
substrate.
15. The device of claim 12 further including a package
encapsulating the chips, the bonding wires, and at least portions
of the assembly pad and terminals.
16. A method for fabricating a semiconductor chip comprising:
providing a semiconductor wafer of a first thickness having an
electrically active side and an opposite electrically inactive
side, the wafer including a plurality of device chips having linear
borders between adjacent chips; backgrinding the inactive wafer
side to reduce the first wafer thickness to a smaller second
thickness; forming on the inactive wafer side a grid of linear
grooves arrayed in parallel rows intersecting with parallel
columns, the rows and columns at right angle to each other, the
grooves having edges spaced by a first width and a depth smaller
than the second thickness; and forming on the active wafer side a
matching grid of linear slits arrayed in parallel rows intersecting
with parallel columns, the slits having edges spaced by a second
width smaller than the first width and a depth merging with
respective grooves, wherein merged slits and grooves form cuts
singulating discrete rectangular chips from the wafer.
17. The method of claim 16, wherein each singulated chip has an
electrically active side bordered by an edge having a first length,
and an opposite electrically inactive side bordered by a parallel
edge having a second length smaller than the first length.
18. The method of claim 17 wherein the active side forms an
overhang over the inactive side.
19. The method of claim 16 wherein the technique to form the
grooves is selected from a group including laser saw, mechanical
saw with wide blade, chemical etchant, and liquid jet.
20. The method of claim 16 wherein the technique to form the slits
is a mechanical saw with thin blade.
21. A method for fabricating a semiconductor device comprising:
providing a semiconductor chip having an electrically active side
and an opposite electrically inactive side, the active side
bordered by an edge having a first length, the inactive side
bordered by a parallel edge having a second length smaller than the
first length; providing a substrate having an assembly pad bordered
by a linear edge having a third length smaller than the first
length; and attaching the inactive chip side to the pad.
22. The method of claim 21 wherein the substrate further includes
terminals surrounding the assembly pad.
23. The method of claim 22 further including the processes of:
connecting the chip to respective substrate terminals by bonding
wires; and encapsulating the chip and bonding wires in a packaging
compound.
24. A method for fabricating a semiconductor device comprising:
providing a first semiconductor chip having an electrically active
side and an opposite electrically inactive side, the active side
bordered by an edge having a first length, the inactive side
bordered by a parallel edge having a second length smaller than the
first length; providing a second semiconductor chip having an
electrically active side and an opposite electrically inactive
side, the active side bordered by an edge having a third length
equal to, smaller, or greater than the first length, the inactive
side bordered by a parallel edge having a fourth length smaller
than the third length; attaching the inactive chip side of the
first chip to the active side of the second chip so that the edge
of the first length is parallel to the edge of the third length;
providing a substrate having an assembly pad bordered by a linear
edge with a fifth length equal to or smaller than the third length;
and attaching the inactive chip side of the second chip to the pad
so that the edge of the third length is parallel to the edge of the
fifth length.
25. The method of claim 24 wherein the third length is equal to or
smaller than the first length and the active side of the attached
first chip forms an overhang over the active side of the second
chip.
26. The method of claim 24 wherein the fifth length is smaller than
the third length and the active side of the attached second chip
forms an overhang over the pad.
27. The method of claim 24 wherein the substrate further includes
terminals surrounding the assembly pad.
28. The method of claim 27 further including the processes of:
connecting the chips to respective substrate terminals by bonding
wires; and encapsulating the chips and bonding wires in a packaging
compound.
Description
FIELD
[0001] Embodiments of the invention are related in general to the
field of semiconductor devices and processes, and more specifically
to the structure and fabrication method of packaged semiconductor
devices with single or stacked chips overhanging the assembly
pad.
DESCRIPTION OF RELATED ART
[0002] It is common practice in fabricating semiconductor devices
that semiconductor chips are attached to substrate pads with an
adhesive material such as a solder or a polymeric compound. In this
attachment process, first a controlled amount of adhesive material
is deposited on the pad, and then the chip is placed on top of the
material while enough pressure is applied to distribute the
material uniformly and allow a small amount of material to bulge
from the chip edges. For the visual process quality control by
inspectors, this bulge is indispensable as a signal of defect-free
assembly.
[0003] As a consequence of this generally accepted quality control
practice, chip areas have to be at least slightly smaller than
assembly pad areas to allow enough space for the bulges of adhesive
material. Whenever a new product requires a larger chip area than
the preceding product, a new generation of assembly pads has to be
provided with a pad area larger than the one required before. In
order to satisfy this need, time and money have to be expended.
SUMMARY
[0004] Applicants realized that the ongoing market pressures for
greater flexibility in satisfying customer needs and for faster
product turn-around time need a quantum jump in assembling
semiconductor chips on substrate pads. Applicant saw that until now
a semiconductor chip has been considered an inseparable unit,
wherein the active side and the passive side (which is to be
attached) form an immutable hexahedron with straight sidewalls.
[0005] By considering the passive chip side independent from the
active side, applicants solved the problem of requiring an enlarged
assembly pad every time the chip size is increased, when they
discovered a methodology of diminishing the area of the passive
side for the attachment process while retaining the area of the
active side for the circuitry.
[0006] In the methodology, the singulation of chips from a
semiconductor wafer is performed in two steps. The inactive side of
the wafer receives a grid of linear grooves of a first width and a
depth smaller than the wafer thickness. Then, the active side of
the wafer receives a matching grid of linear slits of a second
width smaller than the first width and a depth merging the slits
with the respective grooves, thereby singulating chips from the
wafer.
[0007] As a result of the two-step singulation process, each chip
has a large-area active side while exhibiting an overhang over the
smaller-area passive side. As a hexahedron with concave curved
sidewalls, the chip maintains the active side required by the
circuitry while obtaining a passive area acceptable to the
available assembly pad.
BRIEF DESCRIPTION OF THE DRAWINGS
[0008] FIG. 1 shows a cross section of a packaged semiconductor
device having a chip attached to a substrate pad, wherein the
active chip side is greater than the inactive chip side, forming an
overhang, and at least as large as the pad.
[0009] FIG. 2 illustrates a cross section of another packaged
semiconductor device having a chip attached to a substrate pad,
wherein the active chip side is greater than the inactive chip
side, forming an overhang, and greater than the pad, forming an
overhang over the pad.
[0010] FIG. 3 depicts a cross section of yet another packaged
semiconductor device having two chips vertically assembled and the
stack attached to a substrate pad, wherein the active chip sides
are greater than the inactive chip sides, forming overhangs, and
also greater than the pad, forming also overhangs over the pad.
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS
[0011] FIG. 1 illustrates an exemplary embodiment of the invention,
a packaged semiconductor device generally designated 100. The
device has an overall length of 4.0 mm and a thickness 141 of 0.6
mm. The device includes a semiconductor chip 101, which has an
electrically active side 101a and an opposite electrically inactive
side 101b (which may, however, include ground potential). As an
example, the chip thickness 120 may be about 0.20 mm. More
generally, active side 101a may be characterized as the patterned
side, and inactive side 101b may be characterized as the
un-patterned side. The semiconductor material may be silicon,
silicon germanium, gallium arsenide, gallium nitride, or any other
III-V or II-VI compound used for electronic devices. Both the
active side and the inactive side of the chip have rectangular or
square peripheries but are not of identical size; active side 101a
has a larger circumference than inactive side 101b. Considering
analogous parallel lengths, the smaller size of the inactive side
relative to the active side is indicated in the cross section of
FIG. 1 by the shorter length 102b compared to the greater length
102a of the active side. The active side 101a is bordered by an
edge with a first length, which, for brevity, is also designated
102a. The inactive side 101b is bordered by a parallel edge having
a second length 102b smaller than the first length.
[0012] In some devices, the inactive or un-patterned side may be
smaller than the active or patterned side not along all four edges,
but only along one, two, or three edges. In still other devices,
the shorter lengths may not be parallel to the greater lengths, but
form an angle relative to the greater lengths.
[0013] FIG. 1 indicates that the surface 130 of the transition from
the larger active chip side to the smaller inactive chip side may
be curved in a concave sense. In other devices, the chips may have
a linear transition surface, or a surface which starts at the edge
parallel to the active chip side and then gradually changes into a
concave shape. In all cases, the chip material close to the active
surface forms an overhang over the inactive chip side. In the
example of FIG. 1, the overhanging semiconductor material may have
a thickness 121 of about 0.17 mm; in other devices, thickness 121
is 0.10 mm.
[0014] In other embodiments, the semiconductor chip may have
triangular sides or any other geometric configuration. In all
cases, though, the electrically active side has a larger area than
the electrically inactive or passive area, and the analogous side
edges are greater for the active side than for the inactive
side.
[0015] FIG. 1 indicates that chip 101 is attached to suitable site
of a substrate. The substrate may be the chip pad 110 of a metal
leadframe, as shown by the example of FIG. 1. Alternatively the
site may be an attachment pad of a laminated substrate, or it may
be the metallized pad of a board. In these and other examples, the
substrate provides an assembly pad bordered by a linear edge having
a third length. In FIG. 1, the third length is shown as length
110a; in this example, length 110a is 2.5 mm. As FIG. 1 shows, the
third length is equal to parallel first length shown as 102a,
allowing the chip to use the full lateral dimension of the pad. In
other embodiments (see FIG. 2), the third length is smaller than
the parallel first length.
[0016] As FIG. 1 indicates, the inactive chip side 101b is attached
to the pad so that the chip edge of first length is parallel to the
pad edge of third length. For many devices, a layer of a conductive
adhesive polymer is preferred as attachment material; other devices
use a solder layer. The layer preferably has a thickness of about
25 .mu.m.
[0017] In the device example of FIG. 1, chip 101 is connected by
bonding wires 160 to terminals of device 100, which are exemplified
by leadframe leads 150. In laminated substrates, leads 150 are
replaced by metallic terminal pads. Chip 101, bonding wires 160 and
portions of pad 110 and leads 150 are encapsulated in a packaging
compound 170, preferably an epoxy-based molding compound.
[0018] In contrast, FIG. 2 shows an exemplary embodiment 200,
wherein a significant overhang is formed between the active chip
side 201a and the attachment pad 210. The active chip side with the
edge of first length, represented by 202a, is between about 3.05 mm
and 3.55 mm, while third length 210a of the pad is 2.5 mm. The
inactive chip side has an edge of second length 202b of about 2.25
mm allowing attachment to pad 210. As FIG. 2 illustrates, the
overhang of the chip over the attachment pad may be formed by an
undercut with a surface 230 configured to transit gently from the
greater active chip side to the narrower inactive side; in the
example of FIG. 2, a portion of linear surface approximately
parallel to surface 201a morphs into a concave portion extending to
surface 201b. The methods for forming these and other surface
contours see below. In some devices, the overhang may be along one
edge of the attached chip; in other devices, the overhang may be
along more than one edges, for instance along all four edges.
[0019] Similar to exemplary device 100, FIG. 2 indicates that in
device 200 the substrate for attaching chip 201 may be a metal
leadframe with pad 210 and leads 250 as terminals of packaged
device 200. FIG. 1 indicates that chip 101 is attached to suitable
site of a substrate. Alternatively, attachment site 210 may be a
metallized pad of a laminated substrate, or it may be the
metallized pad of a board. In these and other examples, the
substrate provides an assembly pad bordered by a linear edge having
a third length. As FIG. 2 shows, the third length is parallel to
first length.
[0020] As FIG. 2 displays, the inactive chip side 102b is attached
to the pad by an adhesive layer, which may be a conductive polymer
or a solder layer. The layer preferably has a thickness of about 25
.mu.m. In exemplary device 200, chip 201 is connected by bonding
wires 260 to leads 250 as terminals of device 200. Chip 201,
bonding wires 260 and portions of pad 210 and leads 250 are
encapsulated in a packaging compound 270, preferably an epoxy-based
molding compound. The device thickness 241 may, for instance, be
0.6 mm; other devices may be thicker or even thinner.
[0021] Another embodiment of the invention, generally designated
300, is illustrated in FIG. 3. Device 300 has a first semiconductor
chip 301 with an electrically active side 301a and an opposite
electrically inactive side 301b. The active side is bordered by an
edge having a first length 302a, the inactive side is bordered by a
parallel edge having a second length 302b smaller than the first
length 302a. In the example of FIG. 3, the first length may be
about 3.05 mm, and the second length may be about 2.25 mm. In other
devices, the lengths may be greater or smaller. The active side
forms an overhang over the inactive side, which may be shaped as a
concave undercut. The thickness 320 of first chip 301 may be about
0.2 mm; greater or smaller thicknesses are being employed.
[0022] Device 300 further has a second semiconductor chip 305 with
an electrically active side 305a and an opposite electrically
inactive side 305b. The active side is bordered by an edge having a
third length 306a, which may be equal to, smaller than, or greater
than the first length 302a; in the example of FIG. 3, third length
306a is equal to first length 302a. The inactive side of second
chip 305 is bordered by a parallel edge having a fourth length 306b
smaller than the third length 306a.
[0023] As FIG. 3 shows, the inactive chip side 301b of the first
chip 301 is attached to the active side 305a of the second chip
305. The attachment is performed so that the edge of the first
length 302a is parallel to the edge of the third length 305a. For
many devices, a layer of a conductive adhesive polymer is preferred
as attachment material; other devices use a solder layer. The layer
preferably has a thickness of about 25 .mu.m. First chip 301 and
second chip 305 form a stack of chips. As FIG. 3 illustrates, the
distance 307, i.e. the separation between the chips, is the sum of
the thicknesses of the attachment layer and the undercut of the
first chip. Distance 307 may be about 0.10 mm high; at any rate,
distance 307 has to be large enough to accommodate the wire arch
resulting from the wire bonding operation.
[0024] The second chip 305 is attached to suitable site of a
substrate. The substrate may be the chip pad 310 of a metal
leadframe, as shown for the exemplary device 300. Alternatively,
the site may be an attachment pad of a laminated substrate, or it
may be the metallized pad of a board. In these and other examples,
the substrate provides an assembly pad bordered by a linear edge
having a fifth length. In FIG. 3, the fifth length is shown as
length 310a; in this example, length 310a is 2.50 mm. For the
exemplary device 300 in FIG. 3, the fifth length is smaller than
parallel first length 301a and third length 306a, allowing the chip
stack to use the space beyond the lateral dimension of pad 310. In
other embodiments, the overhang of one or both chips may be longer
and even extend over a portion of the leads 350. In yet other
embodiments, fifth length 310a may be equal to third length
306a.
[0025] Embodiments include devices wherein the third length is
equal to or smaller than the first length and the active side of
the attached first chip forms an overhang over the active side of
the second chip. Further, embodiments include devices wherein the
fifth length is smaller than the third length and the active side
of the attached second chip forms an overhang over the top pad
side.
[0026] As FIG. 3 indicates, the inactive chip side 306b is attached
to pad 310 so that the chip edge of third length 306a is parallel
to the pad edge of fifth length 310a. Consequently, chips 301 and
305 are assembled as a stack on pad 310. For many devices, a layer
of a conductive adhesive polymer is preferred as attachment
material; other devices use a solder layer. The layer preferably
has a thickness of about 25 .mu.m.
[0027] In the device example of FIG. 3, chips 301 and 305 are
connected by bonding wires 360 to terminals of device 300, which
are exemplified by leadframe leads 350. In laminated substrates,
leads 350 are replaced by metallic terminal pads. Chips 301 and
305, bonding wires 360 and portions of pad 310 and leads 350 are
encapsulated in a packaging compound 370, preferably an epoxy-based
molding compound. The height 341 of the packaged device 300 may be
about 0.90 mm; however, devices may have a greater or smaller
height. Length 340 of the packaged device 300 may be about 4.0 mm;
however, devices may have a greater or smaller length.
[0028] Another embodiment of the invention is a method for
fabricating a semiconductor chip with an overhang of the chip side
containing the active elements over the opposite side free of
active elements. The method starts by providing a semiconductor
wafer of a first thickness, which has an electrically active side
and an opposite electrically inactive side. The active side
includes a plurality of sites, which will become chips, containing
elements such as transistors, diodes, and integrated circuitry; the
fabrication of the active elements is completed. The sites have
linear borders between adjacent chips. As an example, the sites may
have rectangular configuration with linear borders between the each
adjacent site.
[0029] In the next process, the inactive wafer side is subjected to
a backgrinding technique in order to reduce the first thickness of
the wafer to a second thickness smaller than the first
thickness.
[0030] Next, a grid of linear grooves is formed in the
semiconductor material of the inactive wafer side. The grooves are
arrayed in parallel rows intersecting with parallel columns so that
the rows and columns are at right angles to each other. The
technique to form the grooves is selected from a group including
laser sawing, mechanical sawing with a relatively wide blade,
chemical etching, and hitting with liquid jets. The grooves such
generated have edges spaced by a first width and a depth smaller
than the second thickness. Dependent on device type, first width
may be between 0.2 mm and 1.0 mm or more. Preferably, the grooves
have a rounded bottom; alternatively, the bottom may be more
triangular or cornered.
[0031] In the next process, a matching grid of linear slits is
formed on the active wafer side. The slits are arrayed in parallel
rows intersecting with parallel columns. The preferred technique to
form the slits is a mechanical saw with thin blade. The slits have
edges spaced by a second width smaller than the first width and a
depth deep enough so that the slits can merge with the respective
grooves. Preferably, each slit is administered about in the middle
of the respective groove penetrating the wafer from the opposite
side. After the merger of slit and grooves, the merged slits and
grooves represent effective cuts for singulating discrete
rectangular chips from the wafer.
[0032] The resulting chips have overhangs of the active side over
the inactive side. Each singulated chip has an electrically active
side bordered by an edge having a first length, and an opposite
electrically inactive side bordered by a parallel edge having a
second length smaller than the first length.
[0033] Another embodiment of the invention is a method for
fabricating a semiconductor device with a single chip with an
overhang attached to a substrate. The method starts by providing a
semiconductor chip with an electrically active side and an opposite
electrically inactive side. The active side is bordered by an edge
having a first length, the opposite inactive side is bordered by a
parallel edge having a second length smaller than the first length.
Consequently, the active side forms an overhang over the inactive
side. For some exemplary chips, the second length may be 2.25 mm
and the first length 3.55 mm, creating a relatively long overhang
of 0.65 mm on each chip end.
[0034] Next, a substrate is provided, which has an assembly pad
bordered by a linear edge having a third length equal to or smaller
than the first length. A preferred substrate is a metal leadframe.
Alternatively, the substrate may made by laminating metal and
insulating layers into a multilayer composite. In addition to the
assembly pad, the substrate has a plurality of leads, which serve a
terminals of the completed device; the leads are in the proximity
of the pad and may surround the pad.
[0035] In the next process, the inactive chip side is attached to
the pad so that the edge of the first length is parallel to the
edge of the third length. Thereafter, the chip is connected to
respective substrate terminals by bonding wires. Then, the chip and
the bonding wires are encapsulated in a packaging compound, for
instance in an epoxy-based molding compound.
[0036] Another embodiment of the invention is a method for
fabricating a semiconductor device having a set of vertically
stacked chips with overhangs attached to a substrate. The method
starts by providing a first semiconductor chip with an electrically
active side and an opposite electrically inactive side. The active
side is bordered by an edge with a first length, the inactive side
is bordered by a parallel edge having a second length smaller than
the first length. As a consequence, the active side forms an
overhang over the inactive side. For some exemplary chips, the
second length may be 2.25 mm and the first length 3.55 mm, creating
a relatively long overhang of 0.65 mm on each chip end.
[0037] Next, a second semiconductor chip is provided, which has an
electrically active side and an opposite electrically inactive
side, the active side bordered by an edge having a third length
equal to, smaller, or greater than the first length, the inactive
side bordered by a parallel edge having a fourth length smaller
than the third length.
[0038] In the next process, the inactive chip side of the first
chip is attached to the active side of the second chip so that the
edge of the first length is parallel to the edge of the third
length. Consequently, the first chip is vertically stacked on the
second chip, forming a vertical chip set. For devices wherein the
third length is equal to or smaller than the first length, the
active side of the attached first chip forms an overhang over the
active side of the second chip. After the stack set has been
assembled, there has to be enough space between the overhang of the
first chip and the active side of the second chip to span bonding
wires from the second chip to substrate leads without contact
between the wires and the underside surface of the overhang.
[0039] Next, a substrate is provided, which has an assembly pad
bordered by a linear edge with a fifth length equal to or smaller
than the third length. The substrate may be a metal leadframe or a
laminated board. The substrate includes a plurality of leads or
terminals in the proximity of the assembly pad. The inactive chip
side of the second chip is attached to the pad so that the edge of
the third length is parallel to the edge of the fifth length. For
devices wherein the fifth length is smaller than the third length,
the active side of the attached second chip forms an overhang over
the pad. As mentioned, the adhesive layer is preferably formed by a
conductive polymer, but may also be formed by solder; in both
cases, the preferred thickness of the adhesive layer is about 0.025
mm.
[0040] In the next process, the first chip and the second chip are
connected to respective substrate terminals by bonding wires.
Thereafter, the chips and the bonding wires are encapsulated in a
packaging compound, preferably by an epoxy-based molding
compound.
[0041] While this invention has been described in reference to
illustrative embodiments, this description is not intended to be
construed in a limiting sense. Various modifications and
combinations of the illustrative embodiments, as well as other
embodiments of the invention, will be apparent to persons skilled
in the art upon reference to the description. As an example, the
invention applies to products using any type of semiconductor chip,
discrete or integrated circuit, and the material of the
semiconductor chip may comprise silicon, silicon germanium, gallium
arsenide, or any other semiconductor or compound material used in
integrated circuit manufacturing.
[0042] For products with more than one chip, the invention applies
to two, three or more chips. The invention applies to products with
chips of equal thickness and to products, wherein the chips have
different thicknesses. The invention applies to products with chips
of equal overhangs, and to products, wherein the chips have
different overhangs.
[0043] As another example, the invention applies to any
semiconductor device family which uses QFN/SON leadframes, or a
leadframe with pins. The invention further applies to any amount of
overhang over to the attachment pads/
[0044] It is therefore intended that the appended claims encompass
any such modifications or embodiment.
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