Javier; Reynaldo Corpuz

Patent Applications and Registrations

Patent applications and USPTO patent grants for Javier; Reynaldo Corpuz.The latest application filed is for "exposed pad integrated circuit package".

Company Profile

3.8.15

Javier; Reynaldo Corpuz - Plano TX

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Exposed Pad Integrated Circuit Package App 20220092767 - Javier; Reynaldo Corpuz ; et al.	2022-03-24
Exposed pad integrated circuit package Grant 11,195,269 - Javier , et al. December 7, 2	2021-12-07
Flat no-lead packages with electroplated edges Grant 10,580,723 - Javier , et al.	2020-03-03
Flat No-Lead Packages with Electroplated Edges App 20190295935 - Javier; Reynaldo Corpuz ; et al.	2019-09-26
Flat no-lead packages with electroplated edges Grant 10,366,947 - Javier , et al. July 30, 2	2019-07-30
Packaged semiconductor device having stacked attached chips overhanging the assembly pad Grant 9,768,098 - Lohia , et al. September 19, 2	2017-09-19
Semi-hermetic semiconductor package Grant 9,721,859 - Tran , et al. August 1, 2	2017-08-01
Flat No-Lead Packages with Electroplated Edges App 20170162489 - Javier; Reynaldo Corpuz ; et al.	2017-06-08
Flat No-lead Packages With Electroplated Edges App 20170062315 - JAVIER; REYNALDO CORPUZ ; et al.	2017-03-02
Semi-hermetic Semiconductor Package App 20170062297 - TRAN; ANDY QUANG ; et al.	2017-03-02
Flat no-lead packages with electroplated edges Grant 9,576,886 - Javier , et al. February 21, 2	2017-02-21
Exposed Pad Integrated Circuit Package App 20160286652 - Javier; Reynaldo Corpuz ; et al.	2016-09-29
Packaged Semiconductor Device Having Stacked Attached Chips Overhanging The Assembly Pad App 20160233147 - Lohia; Alok Kumar ; et al.	2016-08-11
Packaged Semiconductor Device Having Attached Chips Overhanging The Assembly Pad App 20160181180 - Lohia; Alok Kumar ; et al.	2016-06-23
Flat no-lead packages with electroplated edges Grant 9,373,569 - Javier , et al. June 21, 2	2016-06-21
Packaged Semiconductor Devices Having Solderable Lead Surfaces Exposed By Grooves In Package Compound App 20160071788 - Lohia; Alok Kumar ; et al.	2016-03-10
Structure And Method Of Packaged Semiconductor Devices With Bent-lead Qfn Leadframes App 20160005712 - Tran; Andy Quang ; et al.	2016-01-07
Packaged semiconductor devices having solderable lead surfaces exposed by grooves in package compound Grant 9,219,019 - Lohia , et al. December 22, 2	2015-12-22
Structure And Method Of Packaged Semiconductor Devices With Qfn Leadframes Having Stress-absorbing Protrusions App 20150262919 - Tran; Andy Quang ; et al.	2015-09-17
Packaged Semiconductor Devices Having Solderable Lead Surfaces Exposed By Grooves In Package Compound App 20150262903 - Lohia; Alok Kumar ; et al.	2015-09-17
Structure And Method Of Packaged Semiconductor Devices With Bent-lead Qfn Leadframes App 20150262918 - Tran; Andy Quang ; et al.	2015-09-17
Semiconductor Device Having Three Terminal Miniature Package App 20150014832 - Javier; Reynaldo Corpuz ; et al.	2015-01-15
Packaged Integrated Circuits And Methods To Form A Stacked Integrated Circuit Package App 20090072373 - Javier; Reynaldo Corpuz ; et al.	2009-03-19

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