U.S. patent application number 14/924782 was filed with the patent office on 2016-06-16 for nanowire field effect transistor with inner and outer gates.
The applicant listed for this patent is International Business Machines Corporation. Invention is credited to Anirban Basu, Guy M. Cohen, Amlan Majumdar, Jeffrey W. Sleight.
Application Number | 20160172441 14/924782 |
Document ID | / |
Family ID | 55275497 |
Filed Date | 2016-06-16 |
United States Patent
Application |
20160172441 |
Kind Code |
A1 |
Basu; Anirban ; et
al. |
June 16, 2016 |
NANOWIRE FIELD EFFECT TRANSISTOR WITH INNER AND OUTER GATES
Abstract
A semiconductor device comprising a suspended semiconductor
nanowire inner gate and outer gate. A first epitaxial dielectric
layer surrounds a nanowire inner gate. The first epitaxial
dielectric layer is surrounded by an epitaxial semiconductor
channel. The epitaxial semiconductor channel surrounds a second
dielectric layer. A gate conductor surrounds the second dielectric
layer. The gate conductor is patterned into a gate line and defines
a channel region overlapping the gate line. The semiconductor
device contains source and drain regions adjacent to the gate
line.
Inventors: |
Basu; Anirban;
(Lagrangeville, NY) ; Cohen; Guy M.; (Ossining,
NY) ; Majumdar; Amlan; (White Plains, NY) ;
Sleight; Jeffrey W.; (Ridgefield, CT) |
|
Applicant: |
Name |
City |
State |
Country |
Type |
International Business Machines Corporation |
Armonk |
NY |
US |
|
|
Family ID: |
55275497 |
Appl. No.: |
14/924782 |
Filed: |
October 28, 2015 |
Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
|
|
14571348 |
Dec 16, 2014 |
9263260 |
|
|
14924782 |
|
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|
Current U.S.
Class: |
438/158 |
Current CPC
Class: |
H01L 29/0673 20130101;
H01L 29/42392 20130101; H01L 29/40114 20190801; H01L 29/0676
20130101; H01L 29/78696 20130101; H01L 51/0048 20130101; H01L
29/7782 20130101; H01L 29/401 20130101; H01L 29/66742 20130101;
H01L 29/0657 20130101; H01L 21/0259 20130101; H01L 29/0669
20130101; H01L 29/775 20130101 |
International
Class: |
H01L 29/06 20060101
H01L029/06; H01L 29/66 20060101 H01L029/66; H01L 29/423 20060101
H01L029/423; H01L 29/40 20060101 H01L029/40 |
Claims
1. A method of forming a semiconductor structure comprising:
etching a trench region in a substrate layer, wherein the trench
region is along a first length of the substrate layer; forming a
nanowire layer directly above the substrate layer along a width of
the substrate layer and in mechanical contact with a top surface of
the substrate layer except above the trench region, wherein a width
of the nanowire layer above the trench region is less than a width
of portions of the nanowire in mechanical contact with the top
surface of the substrate layer; and forming a gate structure having
a bottom surface directly above and in mechanical contact with the
top surface of the substrate layer in a portion of the trench
region, wherein a length of the gate structure is substantially
parallel to the first length of the substrate layer, and wherein
the gate structure surrounds a first surface of the nanowire layer
corresponding to an outer surface of a portion of the nanowire
layer above the trench region, and wherein the gate structure
comprises (i) an inner gate dielectric layer having an inner
surface surrounding the first surface of the nanowire layer, (ii) a
channel layer having an inner surface surrounding an outer surface
of the inner gate dielectric layer, (iii) an outer gate dielectric
layer having an inner surface surrounding an outer surface of the
channel layer, (iv) an outer gate electrode having an inner surface
surrounding an outer surface of the first outer gate dielectric
layer, and (v) a second outer gate dielectric layer directly below
and in mechanical contact with a bottom surface of the outer gate
electrode, wherein a bottom surface of the second outer gate layer
is in mechanical contact with the top surface of the substrate
layer.
2. The method of claim 1, wherein forming the gate structure
comprises: depositing the inner dielectric layer on an exposed
outer surface of the nanowire layer; depositing the channel layer
on the outer surface of the inner dielectric layer; and forming a
gate stack above a central portion of the nanowire layer above the
outer surface of the channel layer, wherein the gate stack
comprises: the first outer gate dielectric layer and the outer gate
electrode.
3. The method of claim 1, further comprising: depositing a first
spacer layer adjacent to a first sidewall of the gate structure;
and depositing a second spacer layer adjacent to a second sidewall
of the gate structure.
4. The method of claim 1, further comprising: depositing a doped
semiconductor layer on an exposed portion of the outer surface of
the layer; depositing a first wide spacer layer adjacent to a first
sidewall of the gate structure, whereby the first wide spacer layer
is directly above a first portion of the layer adjacent to the gate
structure; depositing a second wide spacer layer adjacent to a
second sidewall of the gate structure, whereby the second wide
spacer layer is directly above a second portion of the layer
adjacent to the gate structure; and directionally removing the
inner gate dielectric layer and the channel layer from portions of
the semiconductor device not below the first and second wide spacer
layers.
5. The method of claim 4, further comprising: removing the first
and second wide spacer layers from the semiconductor device;
depositing a palanarizing dielectric layer on exposed surfaces of
the semiconductor device; forming a first contact layer in the
planarizing dielectric layer having a bottom surface in electrical
contact with a top surface of the doped semiconductor layer
adjacent to a first sidewall of the gate structure; forming a
second contact layer in the planarizing dielectric layer having a
bottom surface in electrical contact with a top surface of the
doped semiconductor layer adjacent to a second sidewall of the gate
structure; forming a third contact layer in the planarizing
dielectric layer having a bottom surface in electrical contact with
a top surface the nanowire structure adjacent to the first sidewall
of the gate structure; and forming a fourth contact layer in the
planarizing dielectric layer having a bottom surface in electrical
contact with a top surface the nanowire structure adjacent to the
second sidewall of the gate structure, wherein forming the first,
second, third, and fourth contact layers comprises removing a
portion of the planarizing dielectric layer to form corresponding
trench regions in the planarizing dielectric layer, and depositing
the first, second, third, and fourth contact layers in the
corresponding trench regions.
6. The method of claim 1, further comprising: forming the second
outer gate dielectric layer between a bottom surface of the gate
structure and the top surface of the substrate layer along a
central portion of the trench region.
7. The method of claim 1, further comprising: depositing a hard
mask layer on a top portion of the gate stack.
8. The method of claim 1, wherein the nanowire layer is formed
using a single-crystal semiconductor.
Description
CROSS REFERENCE TO RELATED APPLICATION
[0001] This application is a Divisional application of U.S. patent
application Ser. No. 14/571,348 filed Dec. 16, 2014.
BACKGROUND
[0002] The present invention relates generally to semiconductor
fabrication, and more particularly, to nanowire field effect
transistor (NFET) structures and methods of fabrication.
[0003] Nanotechnology has gained widespread use in the
semiconductor industry as a way to meet scaled technology
requirements. For example, nanowires are currently being used to
form the channel regions in field-effect transistors (FETs).
SUMMARY
[0004] Embodiments of the present invention disclose a method, and
a nanowire semiconductor device with inner and outer gates. A
semiconductor device comprising a suspended semiconductor nanowire
inner gate and a first epitaxial dielectric layer which surrounds a
nanowire inner gate. The first epitaxial dielectric layer surrounds
an epitaxial semiconductor channel. The epitaxial semiconductor
channel further surrounds a second dielectric layer. A gate
conductor surrounds the second dielectric layer, where the gate
conductor is patterned into a gate line and defines a channel
region overlapping the gate line. The semiconductor device contains
source and drain regions adjacent to the gate line.
BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWINGS
[0005] FIG. 1 is cross sectional schematic view depicting a
starting wafer of a semiconductor device, according to an
embodiment of the present disclosure.
[0006] FIG. 2A is a top view and FIG. 2B is a cross sectional
schematic view depicting a process for forming a patterned layer on
semiconductor device, according to an embodiment of the present
disclosure.
[0007] FIG. 3A is a top view and FIG. 3B is a cross sectional
schematic view depicting a partial etching process and suspension
of a layer on semiconductor device, according to an embodiment of
the present disclosure.
[0008] FIG. 4A is a top view and FIG. 4B is a cross sectional
schematic view depicting an application of layers on semiconductor
device, according to an embodiment of the present disclosure.
[0009] FIG. 5A is a top view and FIG. 5B is cross sectional
schematic view depicting an outer gate dielectric layer deposition
on semiconductor device, according to an embodiment of the present
disclosure.
[0010] FIG. 5C is a cross sectional schematic view of the outer and
inner gate, according to an embodiment of the invention.
[0011] FIG. 6A is a top view and FIG. 6B is a cross sectional
schematic view depicting deposition of sidewall spacers on a
semiconductor device, according to an embodiment of the present
disclosure.
[0012] FIG. 7A is a top view and FIG. 7B is a cross sectional
schematic view depicting deposition of a heavily doped
semiconductor layer on a semiconductor device, according to an
embodiment of the present disclosure.
[0013] FIG. 8A is a top view and FIG. 8B is a cross sectional
schematic view depicting deposition and etching of a spacer on a
semiconductor device, according to an embodiment of the present
disclosure.
[0014] FIG. 9A is a top view and FIG. 9B is a cross sectional
schematic view depicting etching of dielectric material on a
semiconductor device, according to an embodiment of the present
disclosure.
[0015] FIG. 10A is a top view and FIG. 10B is a cross sectional
schematic view depicting etching of dielectric material on a
semiconductor device, according to an embodiment of the present
disclosure.
[0016] FIG. 11A is a top view and FIG. 11B is cross sectional
schematic view depicting deposition of a planarizing dielectric on
a semiconductor device, according to an embodiment of the present
disclosure.
[0017] FIG. 12A is a top view and FIG. 12B is cross sectional
schematic view depicting formation of contacts on a semiconductor
device, according to an embodiment of the present disclosure.
DETAILED DESCRIPTION
[0018] Detailed embodiments of the claimed structures and methods
are disclosed herein; however, it can be understood that the
disclosed embodiments are merely illustrative of the claimed
structures and methods that may be embodied in various forms. This
invention may, however, be embodied in many different forms and
should not be construed as limited to the exemplary embodiments set
forth herein. Rather, these exemplary embodiments are provided so
that this disclosure will be thorough and complete and will fully
convey the scope of this invention to those skilled in the art.
[0019] For purposes of the description hereinafter, the terms
"upper", "lower", "right", "left", "vertical", "horizontal", "top",
"bottom", and derivatives thereof shall relate to the disclosed
structures and methods, as oriented in the drawing figures. It will
be understood that when an element such as a layer, region, or
substrate is referred to as being "on", "over", "beneath", "below",
or "under" another element, it may be present on or below the other
element or intervening elements may also be present. In contrast,
when an element is referred to as being "directly on", "directly
over", "directly beneath", "directly below", or "directly
contacting" another element, there may be no intervening elements
present. Furthermore, the terminology used herein is for the
purpose of describing particular embodiments only and is not
intended to be limiting of the invention. As used herein, the
singular forms "a," "an," and "the" are intended to include the
plural forms as well, unless the context clearly indicates
otherwise.
[0020] In the interest of not obscuring the presentation of
embodiments of the present invention, in the following detailed
description, some processing steps or operations that are known in
the art may have been combined together for presentation and for
illustration purposes and in some instances may have not been
described in detail. In other instances, some processing steps or
operations that are known in the art may not be described at all.
It should be understood that the following description is rather
focused on the distinctive features or elements of various
embodiments of the present invention.
[0021] In nanowire FETs with an outer gate-all-around structure,
the charge centroid and the maximum leakage point in the
sub-threshold regime is the center of the nanowire. In the
sub-threshold regime, if one can move the charge centroid and the
maximum leakage point to the outer channel region and thus, get
closer to the gate, it may lead to improved gate control over the
nanowire channel and thus, lead to better control of short-channel
effects.
[0022] In order to form the above-mentioned structure, one needs to
epitaxially deposit the inner gate dielectric atop the inner gate
electrode and then the epitaxially deposit the nanowire channel
atop the inner gate dielectric such that the channel is
crystalline. The above-mentioned structure cannot be implemented in
Si/SiGe material system for NFETs because, in spite of bandgap
difference between Si and SiGe, the conduction band offset is
essentially zero. Therefore, it is not possible to form an inner
gate dielectric in the Si/SiGe material system.
[0023] FIG. 1 is cross sectional schematic view depicting a
starting wafer of a semiconductor device, according to an
embodiment of the present disclosure. Substrate 101 comprises of a
host wafer 102, a dielectric film 104, and a thin layer of a
single-crystal semiconductor 106. It should be noted that the
drawings provided are not to scale and the exemplary thickness of
the layers may vary where the thickness described is not meant to
limit the scope of the disclosure. The host wafer 102 may range in
thickness from 1000 to 600 microns, the dielectric film 102 may
range in thickness of 0.1 micron, and the semiconductor layer 106
may be 0.01 to 0.05 microns thick.
[0024] In an embodiment, the host wafer 102 can be a silicon (Si)
wafer, and the dielectric film 104 may be silicon dioxide
(SiO.sub.2). The single-crystal semiconductor layer 106 can be a
III-V semiconductor such as indium gallium arsenide (InGaAs),
indium arsenide (InAs), or gallium antimonide (GaSb). Since the
dielectric film 104 is placed under III-V layer 106 it is also
referred to as a buried oxide (BOX).
[0025] The substrate 101 can be formed by techniques known in the
art, such as wafer bonding, and layer transfer. Utilizing such
techniques, the single-crystal semiconductor layer 106 may be first
epitaxially grown on a native donor substrate. For example, in an
embodiment in which the single-crystal semiconductor layer 106 is
chosen to be In.sub.0.53Ga.sub.0.47As, it may be epitaxially grown
on an indium phosphide (InP) substrate. It should be noted that a
person having ordinary skill in the art will recognize that InP is
said to be a native substrate for In.sub.xGa.sub.1-xAs since, at an
indium content of x=0.53, the two materials are lattice matched.
Furthermore, lattice matching of the single-crystal semiconductor
layer 106 with respect to the donor wafer does not need to be
maintained if the single-crystal semiconductor layer 106 is kept
below a critical thickness. The critical thickness may be defined
as the layer thickness below which the lattice mismatched between
the layer and the substrate is accommodated by elastic strain.
Furthermore, if the layer thickness exceeds the critical thickness
some of the strain may be relieved by the formation of dislocation.
The formation of dislocations (plastic deformation) is typically
undesired.
[0026] The single-crystal semiconductor layer 106 may be heavily
doped so it may be used as a conductive gate material. In an
embodiment, doping of the single-crystal semiconductor layer 106
may be achieved using impurities that substitute a group III or a
group V atom. For example, in an embodiment in which the
single-crystal semiconductor layer 106 is composed of
In.sub.0.53Ga.sub.0.47As, impurities such as silicon (Si), tin
(Sn), selenium (Se), and tellurium (Te) may be used to make a
n-type semiconductor in which majority carriers would be electrons.
Carbon (C), beryllium (Be), or zinc (Zn) may be used to make a
p-type doped semiconductor in which a majority carriers would
comprise holes.
[0027] In an embodiment, the host wafer 102 with a dielectric film
104 formed thereon may be bonded to the single-crystal
semiconductor layer 106. Using the previous example, the host wafer
102 may be composed of silicon. The dielectric film 104 may be
composed of SiO.sub.2. The dielectric film 104 may be bonded to the
single-crystal semiconductor layer 106, which may be composed of
In.sub.0.53Ga.sub.0.47As. The bonding may be in the form of a
covalent bond formed between the surface of the dielectric film 104
and the single-crystal semiconductor layer 106. In an embodiment,
the single-crystal semiconductor layer 106 may be formed on a donor
substrate (not shown), composed of, for example InP, which may then
be removed, leaving the single-crystal semiconductor layer 106
bonded to the dielectric layer 104. The resulting substrate 101 may
be referred to as a semiconductor-on-insulator substrate. Removal
of the donor substrate may be done by etching or by a method known
in the art as SmartCut.TM.. The SmartCut.TM. method relies on an
ion implantation of hydrogen and annealing to induce the separation
of the donor wafer from the transferred layer.
[0028] FIG. 2A is a top view and FIG. 2B is a cross sectional
schematic view depicting a patterned layer on semiconductor device,
according to an embodiment of the present disclosure. The
single-crystal semiconductor layer 106 (FIG. 1) may be patterned as
shown in the top view of FIG. 2A to form a patterned single-crystal
semiconductor layer 106A. In an embodiment, the definition and
patterning of the single-crystal semiconductor layer 106 (FIG. 1)
may be done by techniques know in the art, such as lithography and
reactive ion etching (RIE). The RIE process chemistry may be
preferably chosen to have etching selectivity with respect to
dielectric layer 104. After the patterned single-crystal
semiconductor layer 106A is formed, the dielectric film 104 may be
exposed at region 200 where the single-crystal semiconductor layer
106 was etched.
[0029] FIG. 3A is a top view and FIG. 3B is a cross sectional
schematic view depicting a partial etching process and suspension
of a layer on semiconductor device, according to an embodiment of
the present disclosure. In an embodiment, the dielectric layer 104
may be partially etched below the patterned single-crystal
semiconductor layer 106A, thereby creating a support opening 300 to
allow the suspension of a center portion of the patterned
single-crystal semiconductor layer 106A. The dimensions of the
etching depth of dielectric film 104 may be calculated based on a
width of the patterned single-crystal semiconductor layer 106A,
according to the embodiment of the invention. For example, if the
patterned single-crystal semiconductor layer 106A has a width
W.sub.301, then dielectric layer 104 may be laterally etched to
undercut the dielectric by at least half of the width W.sub.301 of
the patterned single-crystal semiconductor layer 106A. The etching
dimension may be represented as the following:
ED = w 2 Eq . 1 ##EQU00001##
where ED represents the etching dimensions and w represents the
width of the patterned single-crystal semiconductor layer 106A. In
an embodiment in which the dielectric film 104 is composed of
SiO.sub.2, diluted hydrofluoric acid (DHF) can be used to undercut
the SiO.sub.2 and suspend the center part of the patterned
single-crystal semiconductor layer 106A. It should be noted that a
person having ordinary skill in the art will recognize that the
etch chemistry utilized has to be selective with respect to the
patterned single-crystal semiconductor layer 106A. Utilizing such
selective etch chemistry, for example DHF, will allow etching a
pattern in SiO.sub.2 without removing portions of the patterned
single-crystal semiconductor layer 106A.
[0030] FIG. 4A is a top view and FIG. 4B is a cross sectional
schematic views depicting an application of layers on semiconductor
device, according to an embodiment of the present disclosure. In an
embodiment, a wide bandgap semiconductor inner gate dielectric
layer 201 may be epitaxially grown and wrapped around the suspended
portion of the patterned single-crystal semiconductor layer 106A.
The wide bandgap semiconductor inner gate dielectric layer 201
serves may serve as a gate dielectric. In an embodiment in which
the patterned single-crystal semiconductor layer 106A is composed
of In.sub.0.53Ga.sub.0.47As, the inner gate dielectric layer 201
may be In.sub.xAl.sub.1-xAs. When x=0.5 In.sub.xAl.sub.1-xAs is
latticed matched to In.sub.0.53Ga.sub.0.47As.
[0031] The inner gate dielectric layer 201 may be very thin, having
a thickness of less than 3 nm. Accordingly, the wide bandgap inner
gate dielectric layer 201 may be grown strained with a larger Al
content to allow for a wider bandgap. In an embodiment in which
x=1, the bandgap (i.e., the energy separation between F conduction
band minima and top of the valence band) can be as large as 2.95
eV. Other wide bandgap materials such as phosphides or nitrides may
be used. For example, GaP has a bandgap of 2.26 eV, and AlN has a
bandgap of about 6.2 eV. Alloys, such as ZnCdSe or
Zn.sub.xCd.sub.yMg.sub.1-x-ySe may be particularly utilized as wide
bandgap material for inner gate dielectric layer 201 since they may
be grown latticed matched to InP, and have a bandgap of 2.1 to 2.9
eV with a conduction band offset as large as 80%. In an embodiment,
the growth of inner gate dielectric layer 201 may be accomplished
by using a chemical vapor deposition (CVD) or an atomic layer
deposition (ALD) methods allowing for a conformal deposition of the
layer. These methods may also allow for the selective deposition of
the wide bandgap material for inner gate dielectric layer 201.
Selective deposition may be described as application of the wide
bandgap material forming the of the inner gate channel layer 201
only over the patterned single-crystal semiconductor layer 106A. In
other words, no deposition takes place over the dielectric layer
104.
[0032] In another embodiment, the growth of the inner gate
dielectric layer 201 can be done using a metal-organic chemical
vapor deposition (MOCVD) reactor with trimethylindium (TMIn) as the
indium source, trimethylgallium (TEG) as the gallium source, arsine
(AsH.sub.3) as the arsenic source, phosphine (PH.sub.3) as the
phosphorus source and trimethylaluminum (TMA) as a source for
aluminum. In this embodiment, the growth temperatures may typically
range from 400.degree. C. to 650.degree. C.
[0033] A narrow bandgap semiconductor channel layer 203 may be
epitaxially grown so as to conform to the inner gate dielectric
layer 201. The narrow bandgap semiconductor channel layer 203 may
serve as the device channel. In an embodiment, the channel layer
203 may be composed of In.sub.0.53Ga.sub.0.47. Other high mobility
carrier semiconductors such as InAs may also be utilized. In an
embodiment, the growth of the inner gate dielectric layer 201 and
the channel layer 203 may be pre-formed sequentially in the same
growth chamber without breaking the vacuum.
[0034] FIG. 5A is a top view and FIG. 5B is a cross sectional
schematic view depicting an outer gate dielectric layer deposition
on the semiconductor device, according to an embodiment of the
present disclosure. FIG. 5A depicts the top view of the outer gate
after deposition of a second dielectric layer 205, a gate conductor
207, and the definition of a gate line 208. A hard mask 209 may be
used to pattern and define the gate line 208 using a method of
etching such as RIE. The details of the layer deposition between
channel layer 203 and inner gate 106A are described in more details
in FIG. 5C.
[0035] FIG. 5B depicts an outer gate dielectric layer 205 which may
be deposited over the channel layer 203 (depicted in FIG. 4B). The
outer gate dielectric layer 205 can be epitaxially deposited
similarly to the inner gate dielectric 201, described previously.
Alternatively, an amorphous gate dielectric material, such as
HfO.sub.2 or Al.sub.2O.sub.3, may be used. A gate conductor layer
207 may be formed using a conformal deposition over the outer gate
dielectric layer 205. The gate line 208 may be then formed by
conventional techniques, such as lithography and RIE. The gate line
208 may define the channel region of the device. In an exemplary
embodiment of the invention, the RIE process used to define the
gate line 208 may be performed in two stages. In the first stage,
directional (anisotropic) etching may be used to define the gate
line 208 with near vertical sidewalls. Utilizing the directional
etch technique, however, does not clear the gate stack material
under the suspended structure in areas outside the channel region.
The second stage of the RIE is therefore utilized, using a more
isotropic etch that trims the gate line but also undercuts and
removes the gate material under the portions of the suspended
structure outside the channel region. The gate line 208 may be
capped with the hard mask 209, which may be made of a dielectric
such as Si.sub.3N.sub.4.
[0036] FIG. 5C is a cross sectional schematic view of the outer and
inner gate, according to an embodiment of the invention. The outer
gate may comprise an outer gate dielectric layer 205 in direct
contact with, and surrounding on all sides of, the channel layer
203. The channel layer 203 may be in direct contact with, and
deposited so that it may surround the inner gate dielectric layer
201 on all directions. The inner gate dielectric layer 201 may be
directly deposited onto, and may be in direct contact with, the
patterned single-crystal semiconductor layer 106A. The gate
conductor layer 207 may be formed using a conventional conformal
deposition over the outer gate dielectric layer 205. The gate line
208 may be capped with a hard mask 209 material directly deposited
onto the gate conductor layer 207.
[0037] FIG. 6A is a top view and FIG. 6B is a cross sectional
schematic view depicting deposition of sidewall spacers on a
semiconductor device, according to an embodiment of the present
disclosure. Sidewall spacers 301 may be formed adjacent to the gate
line 208 (depicted in 5C). The spacers may be formed by first
depositing a dielectric layer such as SiO.sub.2 or Si.sub.3N.sub.4
and then performing a directional etch such as RIE to remove the
dielectric layer from horizontally planar surfaces. Vertical
surfaces may therefore be left covered with a dielectric sidewall
composed of the sidewall spacers 301. It should be noted that the
sidewall spacers 301 depicted in FIGS. 6A and 6B, are for
illustration purposes and generally can have a slightly different
shape from those shown. For example, the sidewall spacers 301 can
have different shape corners that can be naturally formed during
the directional etching process as is known in the art.
[0038] FIG. 7A is a top view and FIG. 7B is a cross sectional
schematic view depicting deposition of a heavily doped
semiconductor layer on a semiconductor device, according to an
embodiment of the present disclosure. A heavily doped semiconductor
layer 401 may be epitaxially deposited over the exposed regions of
channel layer 203 extending outside the channel region as defined
by the gate line 208 (depicted in 5C). In an exemplary embodiment,
the heavily doped semiconductor layer 401 may be formed from
In.sub.0.53Ga.sub.0.47As and may be doped with silicon to achieve
n-type doping. In-situ silicon doping may be practiced during the
deposition of the In.sub.0.53Ga.sub.0.47As layer. In an embodiment,
MOCVD growth may be used to form the heavily doped semiconductor
layer 401 and silane (SiH.sub.4) may be added to the gas mixture
during the growth of to obtain Si doping. Other precursors that may
be used are silicon tetrabromide (SiBr.sub.4) and silicon
tetrachloride (SiCl.sub.4). It should be noted that a person having
ordinary skill in the art will recognize that the deposition of the
heavily doped semiconductor layer 401 is selective so the material
of the heavily doped semiconductor layer 401 is only added over
channel layer 203 and no deposition takes place over dielectric
film 104A or sidewall spacers 301.
[0039] FIG. 8A is a top view and FIG. 8B is a cross sectional
schematic view depicting deposition and etching of a spacer on a
semiconductor device, according to an embodiment of the present
disclosure. A dielectric layer (not shown) may be blanket deposited
over the wafer and etched back to form a wide spacer 501. Examples
of dielectric material that may be used to form the dielectric
layer include Si.sub.3N.sub.4, SiO.sub.2, a spin-on-glass (SOG), or
a low-K dielectric. The dielectric material for wide spacer 501
should be chosen as to allow for an adequate filling under the
suspended portion of the device, including the support opening 300
(FIGS. 3A and 3 B). The width of the wide spacer 501 may be defined
by the size of the device source and drain regions.
[0040] FIG. 9A is a top view and FIG. 9B is a cross sectional
schematic view depicting etching of dielectric material on a
semiconductor device, according to an embodiment of the present
disclosure. Utilizing several conventional isotropic etching steps,
portions of layers 401, 203 and 201 may be selectively removed with
respect to the inner gate layer 106A. In an embodiment, the
portions of the layers 401, 203 and, 201, that are removed may be
in regions not covered by the wide spacer 501.
[0041] FIG. 10A is a top view and FIG. 10B is a cross sectional
schematic view depicting regions of recessed dielectric material on
a semiconductor device, according to an embodiment of the present
disclosure. The dielectric material of wide spacer 501 is recessed,
exposing inner gate layer 106A, and support opening 300 located on
dielectric film 104A. The removal of wide spacer 501 can be
accomplished by utilizing a wet etching process that is selective
with respect to gate layer 106A and layer 401. For example, if wide
spacer 501 is formed of SiO.sub.2, then diluted HF can be used to
recess wide spacer 501.
[0042] FIG. 11A is a top view and FIG. 11B is a cross sectional
schematic view depicting deposition of a planarizing dielectric on
a semiconductor device, according to an embodiment of the present
disclosure. A planarizing dielectric 601 is deposited over the
wafer covering the entire wafer including the previously exposed
inner gate layer 106A, and support opening 300 located on
dielectric film 104A. Layer 601 may be formed of a low-k dielectric
and may be deposited by methods such as CVD. Alternatively, layer
601 may be deposited by spin coating of the dielectric and
planarized using chemical mechanical polishing (CMP). The CMP
slurry may be chosen such that it has a minimal polish rate with
respect to gate line 208 in order to polish layer 601 and stop on
gate line 208.
[0043] FIG. 12A is a top view and FIG. 12B is a cross sectional
schematic view depicting formation of contacts on a semiconductor
device, according to an embodiment of the present disclosure. In an
embodiment, contacts 701A may be formed in the planarizing
dielectric 601 in direct contact with the inner gate layer 106A,
outer gate 701B (FIG. 12A) and source and drain (701C). The
contacts 701A may be formed using standard via etch and metal fill
followed by metal polish. Fabrication of each contact may include
multiple process steps and generally conclude with a chemical
mechanical polishing (CMP) step used to remove excess material and
prepare the surface of a planarizing dielectric to accept
succeeding contacts.
[0044] The descriptions of the various embodiments of the present
invention have been presented for purposes of illustration, but are
not intended to be exhaustive or limited to the embodiments
disclosed. Many modifications and variations will be apparent to
those of ordinary skill in the art without departing from the scope
and spirit of the described embodiments. The terminology used
herein was chosen to best explain the principles of the embodiment,
the practical application or technical improvement over
technologies found in the marketplace, or to enable others of
ordinary skill in the art to understand the embodiments disclosed
herein.
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