U.S. patent application number 14/554068 was filed with the patent office on 2016-05-05 for metal gate structure and method of forming the same.
The applicant listed for this patent is UNITED MICROELECTRONICS CORP.. Invention is credited to Main-Gwo Chen, Sheng-Huei Dai, Nien-Ting Ho, Chi-Mao Hsu, Chi-Ju Lee, Tzung-Lin Li, Kuan-Cheng Su, Yao-Chang Wang, Hsiao-Kwang Yang, Fang-Hong Yao.
Application Number | 20160126331 14/554068 |
Document ID | / |
Family ID | 55807613 |
Filed Date | 2016-05-05 |
United States Patent
Application |
20160126331 |
Kind Code |
A1 |
Lee; Chi-Ju ; et
al. |
May 5, 2016 |
METAL GATE STRUCTURE AND METHOD OF FORMING THE SAME
Abstract
The present invention provides a metal gate structure which is
formed in a trench of a dielectric layer. The metal gate structure
includes a work function metal layer and a metal layer. The work
function metal layer is disposed in the trench and comprises a
bottom portion and a side portion, wherein a ratio between a
thickness of the bottom portion and a thickness of the side portion
is between 2 and 5. The trench is filled with the metal layer. The
present invention further provides a method of forming the metal
gate structure.
Inventors: |
Lee; Chi-Ju; (Tainan City,
TW) ; Wang; Yao-Chang; (Tainan City, TW) ; Ho;
Nien-Ting; (Tainan City, TW) ; Hsu; Chi-Mao;
(Tainan City, TW) ; Su; Kuan-Cheng; (Taipei City,
TW) ; Chen; Main-Gwo; (Hsin-Chu City, TW) ;
Yang; Hsiao-Kwang; (Hsinchu County, TW) ; Yao;
Fang-Hong; (New Taipei City, TW) ; Dai;
Sheng-Huei; (Taitung County, TW) ; Li; Tzung-Lin;
(Hsinchu City, TW) |
|
Applicant: |
Name |
City |
State |
Country |
Type |
UNITED MICROELECTRONICS CORP. |
Hsin-Chu City |
|
TW |
|
|
Family ID: |
55807613 |
Appl. No.: |
14/554068 |
Filed: |
November 26, 2014 |
Current U.S.
Class: |
257/407 ;
438/593 |
Current CPC
Class: |
H01L 21/02186 20130101;
H01L 29/518 20130101; H01L 29/513 20130101; H01L 21/28079 20130101;
H01L 29/517 20130101; H01L 29/66545 20130101; H01L 29/78 20130101;
H01L 29/4958 20130101; H01L 29/4966 20130101; H01L 21/02194
20130101; H01L 29/42376 20130101; H01L 21/02178 20130101; H01L
21/02244 20130101; H01L 21/28088 20130101; H01L 29/6659 20130101;
H01L 21/02255 20130101 |
International
Class: |
H01L 29/423 20060101
H01L029/423; H01L 21/02 20060101 H01L021/02; H01L 21/28 20060101
H01L021/28; H01L 29/49 20060101 H01L029/49; H01L 29/51 20060101
H01L029/51 |
Foreign Application Data
Date |
Code |
Application Number |
Oct 30, 2014 |
CN |
201410596532.6 |
Claims
1. A metal gate structure, which is disposed in a trench in a
dielectric layer, comprising: a work function metal (WFM) layer
disposed in the trench, wherein the WFM layer comprises a bottom
portion and a side portion, and a ratio of a thickness of the
bottom portion and a thickness of the side portion is between 2 and
5, the WFM layer comprises TiAl.sub.xCu.sub.y, and x+y=3; and a
metal layer filled in the trench.
2. The metal gate structure according to claim 1, wherein the WFM
layer further comprises a protruding portion disposed at an opening
of the trench.
3. The metal gate structure according to claim 2, wherein a ratio
of the thickness of the bottom portion and a thickness of the
protruding portion is between 2 and 6.
4. The metal gate structure according to claim 1, wherein the WFM
layer comprises titanium aluminides (TiAl), aluminum zirconium
(ZrAl), aluminum tungsten (WAl), aluminum tantalum (TaAl) or
aluminum hafnium (HfAl).
5. (canceled)
6. The metal gate structure according to claim 1, wherein the WFM
layer comprises TiAl.sub.3.
7. The metal gate structure according to claim 1, wherein the WFM
layer comprises Ni, Pd, Pt, Be, Ir, Te, Re, Ru, Rh, W, Mo, or WN,
RuN, MoN, TiN, TaN, or WC, TaC, TiC, or TiAlN, TaAlN.
8. The metal gate structure according to claim 1, further
comprising a metal oxide layer disposed between the WFM layer and
the metal layer.
9. The metal gate structure according to claim 8, wherein the metal
oxide layer comprises TiAlO.
10. The metal gate structure according to claim 1, wherein the
metal layer comprises Al or Cu.
11-20. (canceled)
Description
BACKGROUND OF THE INVENTION
[0001] 1. Field of the Invention
[0002] The present invention is related to a metal gate structure
and a method of forming the same, and more particularly, to a metal
gate structure having work function metal (WFM) layer with stable
crystal phase and a method of forming the same.
[0003] 2. Description of the Prior Art
[0004] Poly-silicon is conventionally used as a gate electrode in
semiconductor devices, such as metal-oxide-semiconductors (MOS).
However, with a trend toward scaling down the size of semiconductor
devices, the conventional poly-silicon gate faces problems like low
performances due to boron penetration, and unavoidable depletion
effect that increases the equivalent thickness of the gate
dielectric layer, reduces the gate capacitance, and worsens a
driving force of the devices. Therefore, work function metals are
used to replace the conventional poly-silicon gates as control
electrodes that are suitable as high-K gate dielectric layers.
[0005] In a complementary metal-oxide semiconductor (CMOS) device,
one of the dual work function metal gates is used in an NMOS device
and the other one is alternatively used in a PMOS device. It is
well-known that the compatibility and the process controls of the
dual metal gates are more complicated, whereas the thickness and
the composition controls of the materials used in the dual metal
gate method are more precise. The conventional dual metal gate
methods are categorized into gate first processes and gate last
processes. In a conventional dual metal gate method applied with
the gate first process, the annealing process for forming the
source/drain ultra-shallow junction and the silicide process are
performed after forming the metal gate. In the conventional gate
last process, a sacrificial gate or a replacement gate is provided
in a first step, followed by performing processes used to construct
a normal MOS transistor. Then, the sacrificial/replacement gate is
removed to form a gate trench. Consequently, the gate trench is
filled with metals according to the different electrical
requirements. However, because of the complicated steps of the gate
last processes, the manufacturers are devoted to simplifying the
manufacturing process.
[0006] In the gate first process or the gate last process, the
metal gate of the PMOS or the NMOS may include a plurality of metal
layers. The materials of the metal layers always affect the work
function of the NMOS or the PMOS, and consequently affect the
performances of the product. Thus, the manufacturers are searching
for new manufacturing method to obtain a MOS with better work
function performances.
SUMMARY OF THE INVENTION
[0007] The present invention therefore provides a metal gate
structure and a method of forming the same, thereby obtaining a
metal gate with good electrical performance.
[0008] According to one embodiment of the present invention, a
metal gate structure is provided. The metal gate structure is
formed in a trench of a dielectric layer. The metal gate structure
includes a work function metal layer and a metal layer. The work
function metal layer is disposed in the trench and comprises a
bottom portion and a side portion, wherein a ratio between a
thickness of the bottom portion and a thickness of the side portion
is between 2 and 5. The trench is filled with the metal layer.
[0009] According to another embodiment of the present invention, a
method of forming a metal gate structure is provided. First, a
dielectric layer with a trench is provided. A work function metal
(WFM) layer in the trench is formed under a temperature greater
than 200 Celsius degrees. Next, an oxidation process is performed
for the WFM layer, thereby forming a metal oxide layer, and a metal
layer is formed on the metal oxide layer, thereby filling the
trench.
[0010] The metal gate structure and the method set forth in the
present invention has a WFM layer with stable crystal phase and a
thicker bottom portion, thus solving many problems in convention
arts.
[0011] These and other objectives of the present invention will no
doubt become obvious to those of ordinary skill in the art after
reading the following detailed description of the preferred
embodiment that is illustrated in the various figures and
drawings.
BRIEF DESCRIPTION OF THE DRAWINGS
[0012] FIG. 1 to FIG. 8 show schematic diagrams of a method of
forming a metal gate structure according one embodiment of the
present invention.
[0013] FIG. 9 shows an X-ray diffusion picture of the WFM layer
with stable crystal phase in the present invention.
[0014] FIG. 10 shows a microscope picture of the WFM layer in the
present invention.
DETAILED DESCRIPTION
[0015] To provide a better understanding of the presented
invention, preferred embodiments will be made in detail. The
preferred embodiments of the present invention are illustrated in
the accompanying drawings with numbered elements.
[0016] Please refer to FIG. 1 to FIG. 8. FIG. 1 to FIG. 8 are
schematic diagrams of the method of forming an metal gate structure
according to one embodiment of the present invention. First, a
substrate 600 is provided, such as a silicon substrate, a
silicon-containing substrate, an epitaxial silicon substrate, a
silicon germanium substrate, a silicon carbide substrate or a
silicon-on-insulator (SOI) substrate, and is not limited thereto. A
plurality of shallow trench isolations (STI) 602 are disposed on
the substrate 600. A transistor 604 is formed on the substrate 600
surrounded by the STI 602. The transistor 604 can be a PMOS or an
NMOS. The following descriptions will show the transistor 604 being
an NMOS as one embodiment.
[0017] In one embodiment shown in FIG. 1, the transistor 604
includes an interface layer 606, a high-k dielectric layer 608, an
etch stop layer 610, a sacrificial gate 612, a cap layer 614, a
spacer 616, a lightly doped drain (LDD) 618 and a source/drain
region 620. In one preferred embodiment of the present invention,
the interface layer 606 can be a SiO.sub.2 layer. The high-k
dielectric layer 608 has a dielectric constant greater than 4, and
the material thereof includes rare earth metal oxides or lanthanide
oxides, such as hafnium oxide (HfO.sub.2), hafnium silicon oxide
(HfSiO.sub.4), hafnium silicon oxynitride (HfSiON), aluminum oxide
(Al.sub.2O.sub.3), lanthanum oxide (La.sub.2O.sub.3), lanthanum
aluminum oxide (LaAlO), tantalum oxide (Ta.sub.2O.sub.5), zirconium
oxide (ZrO.sub.2), zirconium silicon oxide (ZrSiO.sub.4), hafnium
zirconium oxide (HfZrO), yttrium oxide (Yb.sub.2O.sub.3), yttrium
silicon oxide (YbSiO), zirconium aluminate (ZrAlO),
hafniumaluminate (HfAlO), aluminum nitride (AlN), titanium oxide
(TiO.sub.2), zirconium oxynitride (ZrON), hafnium oxynitride
(HfON), zirconium silicon oxynitride (ZrSiON), hafnium silicon
oxynitride (HfSiON), strontium bismuth tantalite
(SrBi.sub.2Ta.sub.2O.sub.9, SBT), lead zirconate titanate
(PbZr.sub.xTi.sub.1-xO.sub.3, PZT) or barium strontium titanate
(Ba.sub.xSr.sub.1-xTiO.sub.3, BST), but is not limited thereto. The
etch stop layer 610 includes metal or metal/metal nitride, such as
TiN. The sacrificial gate 612 is a poly-silicon gate. In another
embodiment, the sacrificial gate 612 is a multi-layered gate
including a poly-silicon layer, an amorphous silicon layer or a
germanium layer. The cap layer 614 is a SiN layer for example. The
spacer 616 can be a multi-layered structure including high
temperature oxide (HTO), SiN, SiO or SiN formed by
hexachlorodisilane (Si.sub.2Cl.sub.6) (HCD-SiN). The LDD 618 and
the source/drain region 620 are formed by appropriate dopants
implantation. In one embodiment, the interface layer 606 and the
etch stop layer 610 can be omitted.
[0018] Next, a contact etch stop layer (CESL) 622 and an
inter-layer dielectric (ILD) layer 624 are formed on the substrate
600 to cover the transistor 604. In one embodiment, the CESL 622
can generate stress to form a selective strain scheme (SSS) for the
transistor 604. In one embodiment, the CESL 622 can be omitted.
[0019] As shown in FIG. 2, a planarization process, such as a
chemical mechanical polish (CMP) process or an etching-back process
or combination thereof is performed to remove a part of the ILD
layer 624, a part of the CESL 622, a part of the spacer 616, and
completely remove the cap layer 614, until a top surface of the
sacrificial gate 612 is exposed.
[0020] As shown in FIG. 3, a wet etching process and/or a dry
etching process is performed to remove the sacrificial gate 612
until exposing the etch stop layer 610. A trench 626 is therefore
formed in the transistor 626. In one embodiment, after forming the
trench 626, the etch stop layer 610 can be removed.
[0021] As shown in FIG. 4, a bottom barrier layer 628 is formed
comprehensively on the substrate 600 and along a surface of the
trench 626. The trench 626 is not completely filled with the bottom
barrier layer 628. The bottom barrier layer 628 comprises TiN,
Ti/TiN, TaN, Ta/TaN, but is not limited thereof. In one embodiment,
the bottom barrier layer 628 can comprise multi layers, for
example, comprise a first barrier layer (not shown), and a second
barrier layer (not shown) disposed thereabove, wherein the first
barrier layer is TiN and the second barrier layer is TaN.
[0022] As shown in FIG. 5, a work function metal (WFM) layer 630 is
formed conformally on the bottom barrier layer 628 wherein the
trench 626 is not completely filled with the WFM layer 630. The WFM
layer 630 serves as a work function metal required by a transistor
604. When the transistor 604 is PMOS, the WFM layer 630 includes
Ni, Pd, Pt, Be, Ir, Te, Re, Ru, Rh, W, Mo, or WN, RuN, MoN, TiN,
TaN, or WC, TaC, TiC, or TiAlN, TaAlN, and is not limited thereto.
When the transistor 604 is NMOS, the WFM layer 630 includes
titanium aluminides (TiAl), aluminum zirconium (ZrAl), aluminum
tungsten (WAl), aluminum tantalum (TaAl) or aluminum hafnium
(HfAl), but should not be limited thereto. In one embodiment, the
step of forming the WFM layer 630 includes a high temperature
deposition process. For example, said high temperature deposition
process is performed under a temperature greater than 200 Celsius
degrees, such as 200 Celsius degrees to 400 Celsius degrees, and
preferably is carried out in vacuum (.apprxeq.0 atm). In comparison
with conventional WFM layer which is formed under room temperature,
the WFM layer 630 formed by the method in the present invention can
have a relatively stable crystal phase.
[0023] Please refer to FIG. 9, which shows an X-ray diffusion
picture of the WFM layer with stable phase provided by the present
invention, wherein the x-coordinate represents the angle and the
y-coordinate represents the intensity. FIG. 9 shows one embodiment
when the WFM layer 630 is TiAl. As shown, the WFM layer formed
under high temperature in the present invention (represented by
solid line) forms a stable crystal phase, TiAl.sub.3. In contrast,
the conventional WFM layer formed under room temperature
(represented by dash line) lakes such stable crystal phase. In one
embodiment, such WFM layer 630 with stable crystal phase can be
represent as TiAl.sub.x, wherein x is 3. In another embodiment,
depending on the material of the metal layer (not shown in FIG. 5)
formed in the subsequent steps, the WFM layer 630 can be
TiAl.sub.xCu.sub.y, and x+y=3.
[0024] In addition, please refer to FIG. 10, which shows a
microscope picture of the WFM layer in the present invention. As
shown in FIG. 10, it is one salient feature in the present
invention that the formed WFM layer 630 has a thicker bottom
portion, a thinner side portion, and a smaller overhang portion.
Please again see FIG. 5, the WFM layer 630 in the trench 626 has a
bottom portion 630A, a side portion 630B and a protruding portion
630C. The bottom portion 630A is located at bottom of the trench
626 and has a bottom thickness W.sub.A; the side portion 630B is
adjacent to the sidewall of the trench 626 and has a side thickness
W.sub.B; the protruding portion 630C is located at the opening of
the trench 626, protruding from the side portion 630B to central
axis of the trench 626, wherein the protruding portion 630C has a
protruding thickness W.sub.C. The bottom thickness W.sub.A is much
greater than the side thickness W.sub.B and the protruding
thickness W.sub.C. In one embodiment, a ratio of the bottom
thickness W.sub.A and the side thickness W.sub.B is between 2 and
5, preferably 4. In another embodiment, a ratio of the bottom
thickness W.sub.A and the protruding thickness W.sub.C is between 2
and 6, preferably 3.
[0025] Next, as shown in FIG. 6, an oxidation process 632 is
performed such that a top portion of the WFM layer 630 becomes a
metal oxide layer 634. In one embodiment, when the WFM layer 630
comprises TiAl, the metal oxide layer 634 comprises TiAlO. In one
embodiment, the oxidation process 632 includes supplying a gas
containing oxygen such as O.sub.2, O.sub.3, H.sub.2O, N.sub.2O,
NO.sub.2 or their combinations. In one embodiment, the oxidation
process 632 can be carried out by exposing the WFM layer 630 to air
under a room temperature, or to oxygen gas under a high temperature
(200 degrees to 400 degrees for example). Since the WFM layer 630
has a stable crystal phase (TiAl.sub.3 for example), only a small
portion of the WFM layer 630 is oxidized, thereby forming a thin
metal oxide layer 634. Accordingly, the electrical performance of
the device can be upgraded. In the embodiment that forms the metal
oxide layer 634 in a high temperature (200 degrees to 400 degrees
for example), a faster forming rate and a better quality of the
metal oxide layer 634 can both be obtained. In addition, since the
metal oxide layer 634 is relatively thin, the ratios of the
thickness between those portions such as the bottom portion 630A,
the side portion 630B and the protruding portion 630C are not
changed and remained within a predetermined value.
[0026] After forming the oxidized WFM layer 634, as shown in FIG.
7, a top barrier layer 636 and a metal layer 638 are formed on the
metal oxide layer 634, wherein the trench 626 is completely filled
with the metal layer 638. In one embodiment, the top barrier layer
636 is comprised of Ti, TiN, TiAlN, Ta, TaN, TaAlC, TaAlN, TiCuC,
TiCuN, TaCuC or TaCuN or their combination, and is not limited
thereto. The metal layer 638 can be made of any low resistance
material such as Al, Ti, Ta, W, Nb, Mo, TiN, TiC, TaN, Ti/W or
Ti/TiN, and is not limited thereto. It is noted that, since the WFM
layer 630 has a thicker bottom portion 630A, it can avoid the metal
layer 638 protruding downwardly into the high-k dielectric layer
608 or the substrate 600 (so called "spiking phenomenon" in
conventional arts). As a result, the top barrier layer 636 can be
omitted in some embodiments. In addition, since the WFM layer 630
has a smaller protruding portion 630C, the top barrier layer 636 or
the metal layer 638 can be easily filled into the trench 638,
avoiding the void problem in conventional arts.
[0027] As shown in FIG. 8, a planarization process is performed to
remove the metal layer 638, the top barrier layer 636, the metal
oxide layer 634, the WFM layer 630 and the bottom barrier layer 628
outside the trench 626. Thus, the etch stop layer 610, the bottom
barrier layer 628, the WFM layer 630, the metal oxide layer 634,
and the metal layer 638 in the trench 626 together form a metal
gate 640 of the transistor 604. The transistor 604 with a metal
gate 640 structure is therefore obtained.
[0028] It is understood that the above embodiment shows forming the
high-k gate dielectric layer at first (namely, the "high-k first"
process). However, those skilled in the art can realize that, in
the present invention, it is also available to form the high-k gate
dielectric layer after removing the sacrifice gate (namely, the
"high-k last" process). In another embodiment, the transistor 604
can be non-planar transistors such as Fin-FET and is not limited to
the planar transistor shown above.
[0029] The transistor 604 formed by the method in the present
invention has good electrical performance and is specifically
suitable in a high-frequency integrated circuit. As shown in the
following table, under an operation voltage about 1 V, the
transistor has a maximum frequency (f.sub.max) about 275.04 GHz,
which is greater than that in conventional arts (239.18 GHz).
f max ( GHz ) The invention Conventional art 275.04 239.18
##EQU00001##
[0030] This gained advantage may be resulted from a smaller value
of capacitance (C.sub.gd) and resistance (R.sub.g) in the
transistor 604. According to the following Equation (I), a smaller
f.sub.max can therefore be obtained.
f max - f 2 R g ( g ds + 2 .pi. f T C gd Equation ( I )
##EQU00002##
[0031] In summary, the metal gate structure and the method set
forth in the present invention has a WFM layer with stable phase
and a thicker bottom portion, thus solving many problems in
convention arts.
[0032] Those skilled in the art will readily observe that numerous
modifications and alterations of the device and method may be made
while retaining the teachings of the invention. Accordingly, the
above disclosure should be construed as limited only by the metes
and bounds of the appended claims.
* * * * *