U.S. patent application number 14/952782 was filed with the patent office on 2016-03-17 for semiconductor device.
The applicant listed for this patent is Renesas Electronics Corporation. Invention is credited to Takashi HASE, Ippei KUME, Toshiharu NAGUMO, Hiroshi TAKEDA.
Application Number | 20160079426 14/952782 |
Document ID | / |
Family ID | 52581923 |
Filed Date | 2016-03-17 |
United States Patent
Application |
20160079426 |
Kind Code |
A1 |
KUME; Ippei ; et
al. |
March 17, 2016 |
SEMICONDUCTOR DEVICE
Abstract
To realize a transistor of normally-off type having a high
mobility and a high breakdown voltage. A compound semiconductor
layer is formed over a substrate, has both a concentration of
p-type impurities and a concentration of n-type impurities less
than 1.times.10.sup.16/cm.sup.3, and includes a group III nitride
compound. A well is a p-type impurity layer and formed in the
compound semiconductor layer. A source region is formed within the
well and is an n-type impurity layer. A low-concentration n-type
region is formed in the compound semiconductor layer and is linked
to the well. A drain region is formed in the compound semiconductor
layer and is located on a side opposite to the well via the
low-concentration n-type region. The drain region is an n-type
impurity layer.
Inventors: |
KUME; Ippei; (Kanagawa,
JP) ; TAKEDA; Hiroshi; (Kanagawa, JP) ;
NAGUMO; Toshiharu; (Kanagawa, JP) ; HASE;
Takashi; (Kanagawa, JP) |
|
Applicant: |
Name |
City |
State |
Country |
Type |
Renesas Electronics Corporation |
Tokyo |
|
JP |
|
|
Family ID: |
52581923 |
Appl. No.: |
14/952782 |
Filed: |
November 25, 2015 |
Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
|
|
14464912 |
Aug 21, 2014 |
9231105 |
|
|
14952782 |
|
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Current U.S.
Class: |
257/76 ;
257/190 |
Current CPC
Class: |
H01L 29/402 20130101;
H01L 29/205 20130101; H01L 29/7849 20130101; H01L 29/404 20130101;
H01L 29/1054 20130101; H01L 29/7835 20130101; H01L 29/2003
20130101; H01L 29/66659 20130101; H01L 29/66522 20130101 |
International
Class: |
H01L 29/78 20060101
H01L029/78; H01L 29/10 20060101 H01L029/10; H01L 29/205 20060101
H01L029/205; H01L 29/40 20060101 H01L029/40; H01L 29/20 20060101
H01L029/20 |
Foreign Application Data
Date |
Code |
Application Number |
Aug 27, 2013 |
JP |
2013-175991 |
Claims
1-9. (canceled)
10. A semiconductor device comprising: a substrate; a compound
semiconductor layer that is formed over the substrate and that
includes a group III nitride compound; a p-type well that is formed
in the compound semiconductor layer; a source region that is formed
in the compound semiconductor layer and that is an n-type impurity
layer; a low-concentration n-type region that is formed in the
compound semiconductor layer and that is linked to the p-type well;
a drain region that is formed in the compound semiconductor layer,
that is located on a side opposite to the p-type well via the
low-concentration n-type region, and that is an n-type impurity
layer; a gate insulating film that is formed over a portion of the
p-type well located between the source region and the
low-concentration n-type region; and a gate electrode that is
formed over the gate insulating film, wherein a p-type impurity
concentration of the compound semiconductor layer is lower than
that of the p-type well, wherein an n-type impurity concentration
of the compound semiconductor layer is less than an n-type impurity
concentration of the low-concentration n-type region, and wherein
the n-type impurity concentration of the low-concentration n-type
region is less than an n-type impurity concentration of the drain
region.
11. The semiconductor device according to claim 10, wherein a
concentration of p-type impurities in the compound semiconductor
layer and a concentration of n-type impurities in the compound
semiconductor layer are each less than
1.times.10.sup.16/cm.sup.3.
12. The semiconductor device according to claim 10, wherein the
source region is formed within the p-type well.
13. The semiconductor device according to claim 10, comprising a
high-resistance compound semiconductor layer that is located
between the substrate and the compound semiconductor layer and that
has a sheet resistance higher than that of the compound
semiconductor layer.
14. The semiconductor device according to claim 13, comprising a
buffer layer located between the high-resistance compound
semiconductor layer and the substrate.
15. The semiconductor device according to claim 10, wherein the
p-type impurity concentration of the p-type well is in a range from
1.times.10.sup.16 cm.sup.-3 to 1.times.10.sup.19 cm.sup.-3,
inclusive.
16. The semiconductor device according to claim 10, comprising: an
insulating layer formed over the low-concentration n-type region;
and a field plate electrode formed over the insulating layer.
17. The semiconductor device according to claim 10, wherein the
compound semiconductor layer is a nitride gallium layer.
18. The semiconductor device according to claim 10, wherein the
n-type impurity concentration of the low-concentration n-type
region is in a range from 1.times.10.sup.16 cm.sup.-3 to
1.times.10.sup.19 cm.sup.-3, inclusive, and wherein the n-type
impurity concentration of the drain region is in a range from
1.times.10.sup.19 cm.sup.-3 to 1.times.10.sup.22 cm.sup.-3,
inclusive.
Description
CROSS-REFERENCE TO RELATED APPLICATION
[0001] The disclosure of Japanese Patent Application No.
2013-175991 filed on Aug. 27, 2013 including the specification,
drawings and abstract is incorporated herein by reference in its
entirety.
BACKGROUND
[0002] The present invention relates to a semiconductor device, and
for example, to a technology applicable to a semiconductor device
having a transistor using a compound semiconductor layer.
[0003] In the field of power semiconductor, the demand for an
increase in breakdown voltage and a reduction in resistance is
rising. The degree of difficulty in device design of an element
using a silicon substrate is increasing because of the adoption or
the like of a complicated structure called super junction in order
to achieve performance exceeding the physical limit.
[0004] In contrast to this, in recent years, development of the
field effect transistor using a group III nitride semiconductor has
been in progress. Such a transistor includes the HEMT (High
Electron Mobility Transistor) using the AlGaN/GaN-based material
and the MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor)
using the Ga-based material. For example, in the transistor having
the AlGaN/GaN heterojunction structure, two-dimensional electron
gas is generated at the interface due to polarization by the piezo
effect. The two-dimensional electron gas has high electron mobility
and a high-carrier density and is capable of giving a low-on
resistance and high-speed switching characteristics to the
transistor.
[0005] In the case where a transistor is used as an element for
power control, the transistor is required to have a low resistance
and a high breakdown voltage between drain and gate. Furthermore,
the transistor using the two-dimensional electron gas is commonly a
transistor of normally-on type. In order to reduce power
consumption of the transistor, it is preferable to form the
transistor into a normally-off type.
[0006] In contrast to this, Japanese Patent Laid-Open No.
2009-246292 (Patent Literature 1) describes that it is possible to
give both a high mobility and a high breakdown voltage to the
GaN-FET by using the electron transit layer using the
two-dimensional electron gas as an electric field relaxation layer.
Furthermore, Patent Literature 1 describes that the transistor is
formed into the normally-off type by separating the electron
transit layer by the recess formed so as to reach the electron
transit layer. However, in the structure of Patent Literature 1,
the threshold voltage and the channel resistance vary considerably
depending on the depth of the recess. Furthermore, due to the
damage caused by the recess processing, the mobility in the channel
part reduces and the channel resistance increases. Because of this,
it is difficult to simultaneously achieve a normally-off type, a
high mobility, and a high breakdown voltage in the GaN-FET as a
whole.
[0007] Japanese Patent Laid-Open No. 2011-187623 (Patent Literature
2) describes formation of the electric field relaxation layer by
introducing n-type impurities into the p-type GaN substrate without
using the two-dimensional electron gas. In detail, Patent
Literature 2 describes that the electric field relaxation layer
having high mobility and a high breakdown voltage is obtained by
setting the sheet carrier concentration of the electric field
relaxation layer to 1.times.10.sup.13 cm.sup.-3 or more and
5.times.10.sup.17 cm.sup.-3 or less.
SUMMARY
[0008] As described above, the transistor used for power control is
required to be of normally-off type and to have a high mobility and
a high breakdown voltage. The inventors of the present invention
have examined the transistor having these three characteristics.
The other tasks and the new feature will become clear from the
description of the present specification and the accompanying
drawings.
[0009] According to the present invention, the semiconductor device
includes a substrate, a compound semiconductor layer, a source
region, a low-concentration n-type region, a drain, a gate
insulating film, and a gate electrode. The compound semiconductor
layer is formed over the substrate, of which both the concentration
of p-type impurities and the concentration of n-type impurities are
less than 1.times.10.sup.16/cm.sup.3, and which includes a group
III nitride compound. The source region is formed in the compound
semiconductor layer and is an n-type impurity layer. The
low-concentration n-type region is formed in the compound
semiconductor layer and linked to a well. The drain region is
formed in the compound semiconductor layer and located on the
opposite side of the well via the low-concentration n-type region.
Furthermore, the drain region is an n-type impurity layer. The gate
insulating film is formed over the portion of the well located
between the source region and the low-concentration n-type region.
The gate electrode is formed over the gate insulating film.
[0010] According to the present invention, it is possible to
realize a transistor of normally-off type and having a high
mobility and a high breakdown voltage.
BRIEF DESCRIPTION OF THE DRAWINGS
[0011] FIG. 1 is a cross-sectional view schematically illustrating
a semiconductor device in a First Embodiment;
[0012] FIG. 2 is a graph illustrating a distribution of impurities
in an A-A section in FIG. 1;
[0013] FIG. 3 is a diagram illustrating a manufacturing method of
the semiconductor device of the First Embodiment;
[0014] FIG. 4 is a diagram illustrating the manufacturing method of
the semiconductor device of the First Embodiment;
[0015] FIG. 5 is a diagram illustrating the manufacturing method of
the semiconductor device of the First Embodiment;
[0016] FIG. 6 is a diagram illustrating the manufacturing method of
the semiconductor device of the First Embodiment;
[0017] FIG. 7 is a diagram illustrating the manufacturing method of
the semiconductor device of the First Embodiment;
[0018] FIG. 8 is a diagram illustrating the manufacturing method of
the semiconductor device of the First Embodiment;
[0019] FIG. 9 is a cross-sectional view illustrating a structure of
a semiconductor device of a Second Embodiment;
[0020] FIG. 10 is a graph illustrating a concentration profile of
impurities;
[0021] FIG. 11 is a cross-sectional view illustrating a structure
of a semiconductor device of a Third Embodiment;
[0022] FIG. 12 is a diagram illustrating a manufacturing method of
the semiconductor device of the Third Embodiment;
[0023] FIG. 13 is a diagram illustrating the manufacturing method
of the semiconductor device of the Third Embodiment;
[0024] FIG. 14 is a diagram illustrating the manufacturing method
of the semiconductor device of the Third Embodiment;
[0025] FIG. 15 is a cross-sectional view illustrating a structure
of a semiconductor device of a Fourth Embodiment;
[0026] FIG. 16 is a cross-sectional view illustrating a structure
of a semiconductor device of a Fifth Embodiment;
[0027] FIG. 17 is a graph for explaining a relationship between the
channel length and the threshold;
[0028] FIG. 18 is a graph for explaining a relationship of the
on-current per unit gate length;
[0029] FIG. 19 is a graph for explaining a relationship between the
sheet resistance and the breakdown voltage of a low-concentration
n-type region LDD;
[0030] FIG. 20 is a graph for explaining a relationship between the
sheet resistance and the amount of implanted Si of an n-type GaN
layer;
[0031] FIG. 21 is a graph for explaining changes in the breakdown
voltage depending on the presence or absence of a field plate;
[0032] FIG. 22 is a graph for explaining a relationship between the
operating temperature and the amount of change in threshold;
[0033] FIG. 23 is a graph for explaining a relationship between the
operating temperature and the device resistance;
[0034] FIG. 24 is a graph for explaining a relationship between a
breakdown voltage VBD and the gate capacitance per resistance;
[0035] FIGS. 25A to 25C illustrate comparisons of the gate
capacitance between Si-MOS and GaN LDD-MISFET, both having a chip
resistance of 0.1 .OMEGA.;
[0036] FIG. 26 illustrates circuit diagrams for evaluating the
high-frequency operations of Si-MOS and GaN LDD-MISFET both having
a chip resistance of 0.1 .OMEGA.;
[0037] FIG. 27 is a diagram for explaining output waveforms when
Si-MOS and LDD-MISFET are caused to operate, respectively, in the
circuits in FIG. 26;
[0038] FIGS. 28A and 28B are graphs illustrating simulation results
of the high-frequency operations of Si-MOS and LDD-MISFET; and
[0039] FIG. 29 is a graph for explaining a relationship between the
operating frequency and the efficiency of each of Si-MOS and GaN
LDD-MISFET.
DETAILED DESCRIPTION
[0040] Hereinafter, embodiments of the present invention will be
explained by using drawings. In all the drawings, the same symbols
are attached to the same components and explanation is omitted
appropriately.
First Embodiment
[0041] FIG. 1 is a cross-sectional view schematically illustrating
a semiconductor device in a First Embodiment. The semiconductor
device of the present embodiment includes a substrate SUB, a
compound semiconductor layer ISM, a source region SOU, a
low-concentration n-type region LDD, a drain region DRN, a gate
insulating film GINS, and a gate electrode GE. The compound
semiconductor layer ISM is formed over the substrate SUB, of which
both the concentration of p-type impurities and the concentration
of n-type impurities are less than 1.times.10.sup.16/cm.sup.3, and
which includes a group III nitride compound. The source region SOU
is formed within the compound semiconductor layer ISM and is an
n-type impurity layer. The low-concentration n-type region LDD is
formed in the compound semiconductor layer ISM and linked to a well
WEL. The drain region DRN is formed in the compound semiconductor
layer ISM and located on the opposite side of the well WEL via the
low-concentration n-type region LDD. The drain region DRN is an
n-type impurity layer. The gate insulating film GINS is formed over
the portion of the well WEL, located between the source region SOU
and the low-concentration n-type region LDD. In addition, the gate
electrode GE is formed over the gate insulating film GINS.
[0042] In the group III nitride compound, the activation rate of
the p-type impurity is low, and thus the p-type layer of the group
III nitride compound includes many p-type impurities not activated.
Because of this, even if the n-type impurity region is formed by
implanting n-type impurities into the p-type group III nitride
compound layer, the mobility of carriers in this impurity region
reduces due to the presence of p-type impurities.
[0043] In contrast to this, the compound semiconductor layer ISM is
a layer intentionally without impurities doped and both the
concentration of p-type impurities and the concentration of n-type
impurities are less than 1.times.10.sup.16/cm.sup.3. Because of
this, by forming the low-concentration n-type region LDD in the
compound semiconductor layer ISM, it is possible to keep high the
mobility of carriers in the low-concentration n-type region LDD.
Furthermore, the low-concentration n-type region LDD is formed, and
thus it is possible to increase the breakdown voltage between the
drain region DRN and the gate electrode GE. Moreover, the portion
of the well WEL, located between the source region SOU and the
low-concentration n-type region LDD serves as a channel region CNL,
and thus it is possible to form the transistor into the
normally-off type. Detailed explanation will be given below.
[0044] Meanwhile, the constituent components in each embodiment
below only selectively illustrate a part of devices constituting
each circuit and the scope of right of the present invention is not
limited by active devices not related directly to the embodiments
according to the present invention, coupling methods of multilayer
wirings, and the like.
[0045] The semiconductor device illustrated in FIG. 1 has a
compound semiconductor layer EPI over the substrate SUB. The
compound semiconductor layer EPI has a configuration in which a
buffer layer BUF, a high-resistance compound semiconductor layer
HRL, and the compound semiconductor layer ISM are stacked over the
substrate SUB.
[0046] The substrate SUB is, for example, a silicon substrate or a
sapphire substrate. The buffer layer BUF is, for example, AlN,
AlGaN, a stacked structure thereof, or a stacked structure of
AlN/GaN. As these layers, a layer may be used, which is formed by
the manufacturing method of a semiconductor substrate or a
semiconductor device used commonly and the scope of right of the
present invention is not limited by these structures and
materials.
[0047] The buffer layer BUF is provided in order to absorb lattice
mismatch between the substrate SUB and the high-resistance compound
semiconductor layer HRL and to suppress an internal stress.
[0048] The high-resistance compound semiconductor layer HRL is
formed of a material having a sheet resistance higher than that of
the compound semiconductor layer ISM, and thus has a breakdown
voltage higher than that of the compound semiconductor layer ISM.
The high-resistance compound semiconductor layer HRL is formed by,
for example, doping impurities for improving insulating properties
into the compound semiconductor made of the same material as that
of the compound semiconductor layer ISM.
[0049] The thickness of the compound semiconductor layer ISM is,
for example, 100 nm or more and 2,000 nm or less. Impurities are
not added to the compound semiconductor layer ISM intentionally.
Because of this, both the concentration of n-type impurities and
the concentration of p-type impurities in the compound
semiconductor layer ISM are less than 1.times.10.sup.16/cm.sup.3,
for example, less than 1.times.10.sup.15/cm.sup.3. The compound
semiconductor layer ISM is, for example, GaN, AlN, AlGaN, and
AlGaInN.
[0050] Meanwhile, in the case where the high-resistance compound
semiconductor layer HRL and the compound semiconductor layer ISM
are nitride gallium (GaN) layers, the p-type impurity is, for
example, Mg and the n-type impurity is, for example, Si. In
addition, the high-resistance compound semiconductor layer HRL is
formed by introducing impurities, such as C, into GaN.
[0051] In the compound semiconductor layer ISM, a MOSFET is formed.
The MOSFET has the well WEL, the source region SOU, the drain
region DRN, the low-concentration n-type region LDD, the gate
insulating film GINS, and the gate electrode GE.
[0052] The well WEL is a p-type impurity region and formed by
implanting impurities such as Mg, into the compound semiconductor
layer ISM. The source region SOU is formed in the well WEL. In
addition, the region of the well WEL located between the source
region SOU and the low-concentration n-type region LDD serves as
the channel region CNL.
[0053] The source region SOU, the drain region DRN, and the
low-concentration n-type region LDD are formed by implanting
impurities such as, for example, silicon (Si), into the compound
semiconductor layer ISM. The low-concentration n-type region LDD
functions as an electric field relaxation layer (LDD: Lightly Doped
Drain). The source region SOU and the drain region DRN have an
n-type impurity concentration higher than that of the
low-concentration n-type region LDD.
[0054] The gate insulating film GINS and the gate electrode GE are
formed over the channel region CNL.
[0055] The gate insulating film GINS is an insulating film formed
by an insulating material including, for example, one selected from
SiO.sub.2, SiN, and Al.sub.2O.sub.3 or an insulating film formed by
combining a plurality of layers formed by these insulating
materials (for example, silicon nitride film/aluminum oxide film),
or a stacked film made of the same material. For example, from the
viewpoint of chemical stability of GaN that is a compound
semiconductor, it is preferable for the gate insulating film GINS
to be formed by the insulating material containing Al.sub.2O.sub.3
as a main component. In the example illustrated in FIG. 1, although
the gate insulating film GINS is formed also in a region other than
the channel region CNL, the insulating film located in a region
other than the channel region CNL, for example, the insulating film
over the low-concentration n-type region LDD may be formed by a
material different from that of the gate insulating film GINS.
[0056] Although not limited in particular, it is preferable that
the film thickness of the gate insulating film GINS is a thickness
of having, for example, a breakdown voltage of 10 V or more. The
gate insulating film GINS forms an inversion layer in the channel
region CNL, and therefore, a voltage is applied thereto.
Preferably, an example of the film thickness of the gate insulating
film GINS is, for example, 30 nm or more and 200 nm or less. By
setting the film thickness of the gate insulating film GINS to the
lower limit value or more, it is possible to apply a voltage of 10
V or more to the gate electrode GE.
[0057] It is possible to select the gate electrode GE from a metal
material including one selected from, for example, TiN, W, Pt, Hf
and the like, or an alloy containing those as main components (for
example, 95 mass % or more are contained), or a metal material
including those. In addition, a voltage of 10 V or more is applied
to the gate electrode GE.
[0058] A source electrode SOE is formed over the source region SOU
and a drain electrode DRE is formed over the drain region DRN. It
is possible to select the material of the source electrode SOE and
the drain electrode DRE from the metal material selected from Al,
Cu, W, and the like, or the alloy containing these as main
components (for example, 95 mass % or more are contained).
Meanwhile, it is desirable that the material of the source
electrode SOE and the drain electrode DRE is a material that can be
ohmic-coupled to the source region SOU and the drain region DRN and
that has a low work function. Note that a barrier metal may be
present around the source electrode SOE and the drain electrode
DRE. It is preferable that the material of the barrier metal is a
material that has barrier properties against diffusion of metal,
such as Ti, TiN, Ta, and TaN, that has high adhesion to GaN, an
insulating film, or the like, that can be ohmic-coupled to an
n-type GaN, and that has a low work function.
[0059] Meanwhile, the transistor formed over the compound
semiconductor layer EPI is electrically floating in its original
state, and thus it needs to be grounded. In the semiconductor
device of the present embodiment, the electrode for grounding the
well WEL is also formed in the same manner as that of the source
electrode SOE and the drain electrode DRE. It is preferable that
the material of the electrode for grounding the well WEL is a
material having a high work function, such as TiN, W, WN, Pt, and
Ni.
[0060] In addition, over the gate electrode GE and over the gate
insulating film GINS, a wiring layer insulating film INSL1 is
formed. The wiring layer insulating film INSL1 is, for example, a
SiO.sub.2 film or a SiN film. It may also be possible to further
form a wiring layer constituted by a wiring and an interlayer
insulating layer at the upper part of the gate electrode GE, the
source electrode SOE, and the drain electrode DRE. Due to this, it
is possible to form a semiconductor device having a multilayer
wiring structure of the semiconductor device commonly used. It is
obvious to a person skilled in the art that such a configuration of
the semiconductor device is possible, and thus, in the present
embodiment, there is not illustrated, in particular, the structure
diagram of the wiring located in the layer further higher than the
wiring layer in which the gate electrode GE, the source electrode
SOE, and the drain electrode DRE which operate the transistor are
formed.
[0061] In addition, in the actual semiconductor device, the source
region SOU, the gate electrode GE, and the drain region DRN are
provided repeatedly. Although the wiring layer has a multilayer
structure, in FIG. 1, a single-layer wiring is illustrated for the
sake of simplification of the drawing.
[0062] FIG. 2 is a graph illustrating a distribution of impurities
in an A-A section in FIG. 1. As described above, the source region
SOU, the channel region CNL, the low-concentration n-type region
LDD, and the drain region DRN are formed by using the compound
semiconductor layer ISM. N-type impurities or p-type impurities are
not introduced intentionally into the compound semiconductor layer
ISM. Therefore, in the drain region DRN and in the
low-concentration n-type region LDD, Mg serving as the p-type
impurities is not included. Meanwhile, the source region SOU is
formed in the channel region CNL, and thus includes Mg.
[0063] FIG. 3 to FIG. 8 are diagrams illustrating a manufacturing
method of the semiconductor device of the First Embodiment. The
manufacturing method of the semiconductor device of the present
embodiment includes the following processes. First, the compound
semiconductor layer EPI is formed over the substrate SUB. Here, it
may also be possible to prepare a substrate in which the compound
semiconductor layer EPI is formed over the semiconductor substrate
SUB. Next, impurities are implanted into the compound semiconductor
layer ISM in order to form the low-concentration n-type region LDD,
the source region SOU, the drain region DRN, and the well WEL.
Subsequently, a cap film is formed over the compound semiconductor
layer EPI and activation annealing for activating impurities is
performed. After the activation annealing is performed, the cap
film is removed. Next, the gate insulating film GINS is formed over
the compound semiconductor layer EPI. After that, the gate
electrode GE and the wiring layer insulating film INSL1 are formed.
Next, the gate insulating film GINS over the source region SOU and
the drain region DRN is removed and the source electrode SOE and
the drain electrode DRE are formed. In this manner, a transistor is
formed over the semiconductor substrate SUB. Hereinafter, the
processes of the present embodiment will be described in
detail.
[0064] First, as illustrated in FIG. 3, the buffer layer BUF, the
high-resistance compound semiconductor layer HRL, and the compound
semiconductor layer ISM are formed sequentially over the substrate
SUB by a method commonly used (e.g., epitaxial growth method). The
buffer layer BUF is, for example, AlN and the thickness is, for
example, 300 to 1,000 nm. The high-resistance compound
semiconductor layer HRL is formed so as to have a thickness of, for
example, 100 to 1,000 nm. The high-resistance compound
semiconductor layer HRL is formed by the doping of impurities for
increasing resistance such as, for example, C (carbon), in the
range of 1.times.10.sup.16 cm.sup.-3 to 1.times.10.sup.19 cm.sup.-3
while forming a film of the compound semiconductor. Then, the
compound semiconductor layer ISM is formed so as to have a
thickness of 100 to 1,000 nm. During the formation of the compound
semiconductor layer ISM, gases serving as raw materials of
impurities are not introduced into a film formation chamber.
[0065] Next, as illustrated in FIG. 4, impurities are implanted
into the compound semiconductor layer ISM. Due to this, the well
WEL, the source region SOU and the drain region DRN, and the
low-concentration n-type region LDD are formed. The order of
formation of these regions is the order of greater depth of
implantation of impurities. Specifically, the well WEL, the source
region SOU and the drain region DRN, and the low-concentration
n-type region LDD are formed in this order. The depth of
implantation of impurities in forming the well WEL is 100 to 500
nm, the depth of implantation of impurities in forming the source
region SOU and the drain region DRN is 50 to 300 nm, and the depth
of implantation of impurities in forming the low-concentration
n-type region LDD is 10 to 50 nm. Furthermore, in forming the well
WEL, Mg is implanted in the range of 1.times.10.sup.16 to
1.times.10.sup.19 cm.sup.-3, in forming the source region SOU and
the drain region DRN, Si is implanted in the range of
1.times.10.sup.18 to 1.times.10.sup.22 cm.sup.-3, and in forming
the low-concentration n-type region LDD, Si is implanted in the
range of 1.times.10.sup.16 to 1.times.10.sup.19 cm.sup.-3.
[0066] Next, although not illustrated, a cap film is formed over
the compound semiconductor layer EPI and then impurities are
activated by activation annealing.
[0067] Next, as illustrated in FIG. 5, the gate insulating film
GINS is formed over the compound semiconductor layer EPI. As the
film forming method, it is desirable to use CVD, ALD, and the like.
Furthermore, as illustrated in FIG. 6, it is sufficient that the
gate insulating film GINS only exists over the channel region CNL,
and an insulating film INSL3 made of an insulating material
different from that of the gate insulating film GINS may be formed
over the source region SOU and the drain region DRN.
[0068] Next, as illustrated in FIG. 7, the gate electrode GE is
formed over the gate insulating film GINS. Specifically, first, an
electrically conductive film serving as the gate electrode GE is
formed over the entire surface of the gate insulating film GINS by,
for example, the sputter method or the CVD method. Then, the
insulating film is processed into a shape of the gate electrode GE
by patterning using a photoresist. Meanwhile, although not
illustrated, depending on the material of the gate electrode GE,
there is a case where the film thickness of the gate insulating
film GINS is reduced at the time of processing the gate electrode
GE. After the gate electrode GE is formed, the wiring layer
insulating film INSL1 is formed. The wiring layer insulating film
INSL1 is formed by the CVD method or the ALD method.
[0069] Next, as illustrated in FIG. 8, the source electrode SOE and
the drain electrode DRE are formed. Specifically, the wiring layer
insulating film INSL1 over the source region SOU and the drain
region DRN is removed by dry etching or wet etching through the use
of a photoresist or a hard mask process. Next, an electrically
conductive film (for example, metal film) is formed by a sputter
method or the CVD method and the electrically conductive film is
patterned into a shape of electrode by the photoresist.
[0070] Next, the working effect of the First Embodiment will be
explained. According to the present embodiment, the
low-concentration n-type region LDD is formed in the compound
semiconductor layer ISM. Impurities are not doped into the compound
semiconductor layer ISM intentionally at the time of film
formation. Because of this, the low-concentration n-type region LDD
serves as an electric field relaxation layer excellent in mobility.
Furthermore, the well WEL is formed limitedly to the region serving
as the source region SOU and the channel region CNL. Therefore, it
is possible to form hole carriers in the channel region CNL without
reducing the mobility of the low-concentration n-type region LDD
and to work the transistor as the normally-off type. Moreover, by
implanting high-concentration impurities into the source region SOU
and the drain region DRN, it is possible to considerably reduce the
coupling resistance of the source electrode SOE and the drain
electrode DRE. Due to this, it is possible to reduce all of the
channel resistance, the LDD resistance, and the contact resistance,
which account for the resistance of the LDD-MISFET device.
Consequently, a semiconductor device of the normally-off type,
having a low resistance and a high breakdown voltage is
realized.
[0071] In addition, since the transistor is formed in the compound
semiconductor layer ISM, the layer structure of the compound
semiconductor layer EPI is simplified and the manufacturing thereof
becomes easy. Due to this, the enhancement of the manufacturing
yield of the compound semiconductor layer EPI is realized, and as a
result, it is possible to reduce the manufacturing cost of the
semiconductor device.
[0072] Furthermore, between the compound semiconductor layer ISM
and the substrate SUB, the high-resistance compound semiconductor
layer HRL is formed. Therefore, it is possible to increase the
breakdown voltage between the substrate SUB and the drain region
DRN. In addition, it is possible to reduce the leak current that
flows from the drain region DRN to the substrate SUB.
Second Embodiment
[0073] FIG. 9 is a cross-sectional view illustrating a structure of
a semiconductor device of a Second Embodiment. The semiconductor
device according to the present embodiment has the same
configuration as that of the semiconductor device according to the
First Embodiment except in that the compound semiconductor layer
EPI has a p-type compound semiconductor layer PSM. The p-type
compound semiconductor layer PSM is located between the
high-resistance compound semiconductor layer HRL and the compound
semiconductor layer ISM.
[0074] The p-type compound semiconductor layer PSM is formed by
introducing p-type impurities (for example, Mg) into the raw
material while, for example, forming a film of a compound
semiconductor layer. The film thickness of the p-type compound
semiconductor layer PSM is, for example, 100 to 1,000 nm and the
film thickness of the compound semiconductor layer ISM is in the
range of, for example, 10 to 100 nm. In addition, the impurity
concentration of the p-type compound semiconductor layer PSM is in
the range of, for example, 1.times.10.sup.16 to 1.times.10.sup.19
cm.sup.-3.
[0075] In the present embodiment, the low-concentration n-type
region LDD is formed only in the compound semiconductor layer ISM.
On the other hand, the lower parts of the source region SOU and the
drain region DRN may intrude into the p-type compound semiconductor
layer PSM. However, in forming the compound semiconductor layer ISM
over the p-type compound semiconductor layer PSM, the impurities
(for example, Mg) of the p-type compound semiconductor layer PSM
diffuse to the compound semiconductor layer ISM. Therefore, there
exists a mixing layer at the interface between the p-type compound
semiconductor layer PSM and the compound semiconductor layer ISM.
Because of this, in the present embodiment, as illustrated in FIG.
10, the concentration profile of the p-type impurities (for
example, Mg) is discontinuous and the portion where the impurity
concentration is reduced 50% or more compared with that of the
p-type compound semiconductor layer PSM is defined as the interface
between the compound semiconductor layer ISM and the p-type
compound semiconductor layer PSM.
[0076] In the present embodiment also, by not forming the
low-concentration n-type region LDD in the p-type GaN layer where
the impurity concentration is high, it is possible to maintain the
high mobility of the low-concentration n-type region LDD. Because
of this, the same effect as that of the First Embodiment is
obtained. Furthermore, because the p-type compound semiconductor
layer PSM is located in the lower layer of the low-concentration
n-type region LDD, hole carriers are supplied from the p-type
compound semiconductor layer PSM when the gate voltage is off.
Because of this, by the RESURF (Reduced Surface Field) effect, the
depletion layer extends and the breakdown voltage of the
semiconductor device is increased compared to that of the First
Embodiment.
Third Embodiment
[0077] FIG. 11 is a cross-sectional view illustrating a structure
of a semiconductor device of a Third Embodiment. The semiconductor
device of the present embodiment is the same as that of the First
Embodiment except in that a source field plate electrode SFP and a
gate field plate electrode GFP are constituted in the upper layer
of the low-concentration n-type region LDD. In the present
embodiment, the semiconductor device may have only one of the
source field plate electrode SFP and the gate field plate electrode
GFP.
[0078] The source field plate electrode SFP is installed above the
low-concentration n-type region LDD and with a sufficient space
from the drain electrode DRE, in a plan view. Although not
illustrated in particular, the source field plate electrode SFP is
electrically coupled to the source electrode SOE. The wiring for
coupling may stride over the gate electrode GE or may be formed in
the same layer as that of the source field plate electrode SFP and
the source electrode SOE in the form of a ladder. Similarly, the
gate field plate electrode GFP is also installed above the
low-concentration n-type region LDD and with a sufficient space
from the source electrode SOE and the drain electrode DRE in a plan
view.
[0079] In the example illustrated in FIG. 11, the gate field plate
electrode GFP is formed over the wiring layer insulating film
INSL1. In addition, a wiring layer insulating film INSL2 is formed
over the wiring layer insulating film INSL1 and the source field
plate electrode SFP is formed over the wiring layer insulating film
INSL2. Furthermore, in a plan view, the source field plate
electrode SFP is located close to the drain electrode DRE than the
gate field plate electrode GFP. The wiring layer insulating film
INSL2 is, for example, a SiO.sub.2 film or a SiN film.
[0080] FIG. 12 to FIG. 14 are diagrams illustrating a manufacturing
method of the semiconductor device of the Third Embodiment. First,
in the same manner as that of the First Embodiment, a structure
illustrated in FIG. 12 is fabricated (that is, fabrication of up to
the wiring layer insulating film INSL1 is completed). Namely, after
forming the gate electrode GE over the gate insulating film GINS,
the wiring layer insulating film INSL1 is formed.
[0081] Next, as illustrated in FIG. 13, in the wiring layer
insulating film INSL1, a coupling hole OP1 located over the gate
electrode GE is opened. Next, an electrically conductive film is
formed over the wiring layer insulating film INSL1 and within the
coupling hole OP1, and the electrically conductive film is removed
selectively. Due to this, the gate field plate electrode GFP is
formed.
[0082] Next, over the gate field plate electrode GFP and over the
wiring layer insulating film INSL1, the wiring layer insulating
film INSL2 is formed. The insulating materials of the wiring layer
insulating film INSL1 and the wiring layer insulating film INSL2
may be the same or different. For example, both the wiring layer
insulating films INSL1 and INSL2 may be SiO.sub.2 films or one of
them may be a SiO.sub.2 film and the other may be a SiN film.
[0083] Next, as illustrated in FIG. 14, by the same manufacturing
method as that of the First Embodiment, the source electrode SOE
and the drain electrode DRE are formed. At this time, the source
field plate electrode SFP is formed at the same time as each
electrode.
[0084] By the present embodiment also, the same effect as that of
the First Embodiment is obtained. Furthermore, by providing at
least one of the source field plate electrode SFP and the gate
field plate electrode GFP, the depletion layer in the
low-concentration n-type region LDD extends when the transistor is
off. When the impurity concentration of the low-concentration
n-type region LDD becomes a fixed level or more, the depletion
layer no longer extends through the entire low-concentration n-type
region LDD, and therefore, the breakdown voltage reduces, but by
the installation of the field plate, it becomes possible to extend
the depletion layer through the entire low-concentration n-type
region LDD. Because of this, with maintenance of a high breakdown
voltage, the increase in the concentration of the low-concentration
n-type region LDD, namely, the reduction in resistance becomes
possible.
Fourth Embodiment
[0085] FIG. 15 is a cross-sectional view illustrating a structure
of a semiconductor device of a Fourth Embodiment. The semiconductor
device according to the present embodiment is the same as the
semiconductor device according to the Third Embodiment except in
that the compound semiconductor layer EPI has the p-type compound
semiconductor layer PSM illustrated in the Second Embodiment.
[0086] According to the present embodiment, both the effect shown
in the Second Embodiment and the effect shown in the Third
Embodiment can be obtained.
Fifth Embodiment
[0087] FIG. 16 is a cross-sectional view illustrating a structure
of a semiconductor device of a Fifth Embodiment. The semiconductor
device according to the present embodiment is the same as the
semiconductor device according to the Fourth Embodiment except
having no well WEL.
[0088] According to the present embodiment, the hole carriers
formed in the p-type compound semiconductor layer PSM can move into
the compound semiconductor layer ISM. Because of this, it is
possible to realize the normally-off type transistor without
forming the well WEL. Consequently, the same effect as that of the
Fourth Embodiment is obtained. Furthermore, when the impurity
concentration of the channel part is lowered, the channel
resistance is also reduced, and thus it becomes possible to realize
a semiconductor device having a lower resistance.
[0089] Next, the effect of the semiconductor device of each
embodiment described above will be explained in comparison with a
comparative example. FIG. 17 is a graph for explaining a
relationship between the channel length and the threshold in the
semiconductor device according to the First Embodiment. It is known
that the threshold of the transistor does not depend on the channel
length and indicates a positive fixed value in the case where the
impurity concentration of the well WEL is 1.times.10.sup.16
cm.sup.-3 or more. From this, it is known that the normally-off
transistor can be formed by forming the well WEL.
[0090] FIG. 18 is a graph for explaining a relationship of the
on-current per unit gate length at each gate voltage in the
semiconductor device according to the First Embodiment. It is known
that the on-threshold is about 1 V in the case where 10 uA/mm is
set to be the boundary between on and off.
[0091] FIG. 19 is a graph for explaining a relationship between the
sheet resistance and the breakdown voltage of the low-concentration
n-type region LDD having the same impurity concentration. The case
where the well WEL is formed on the entire surface of the region
serving as the transistor (that is, the case where the
low-concentration n-type region LDD is formed within the well WEL)
and the case where the well WEL is formed only in the region
serving as the channel region CNL and the source region SOU are
compared. It is indicated that the presence of the well WEL
increases the resistance of the low-concentration n-type region LDD
in the case where the breakdown voltage is maintained. Conversely,
FIG. 19 indicates that if there is no P well overlapping with the
LDD layer, it is possible to realize the low-concentration n-type
region LDD as an LDD having a low resistance.
[0092] FIG. 20 is a graph for explaining a relationship between the
sheet resistance of an n-type GaN layer and the amount of implanted
Si. In the range of application to the source region SOU, it is
possible to realize a sheet resistance lower than that in the case
where the 2DEG (two-dimensional electron gas) is utilized. This
indicates that the contact resistance between the source region SOU
and the source electrode SOE and the contact resistance between the
drain region DRN and the drain electrode DRE become lower than
those in the case where impurity implantation is not used.
[0093] FIG. 21 is a graph for explaining a change in breakdown
voltage depending on the presence or absence of a field plate (for
example, the gate field plate electrode GFP or the source field
plate electrode SFP). In the case where a field plate is present,
the breakdown voltage is enhanced by a factor of about 2 while
maintaining the same area resistivity (RonA). This indicates that
it is possible to enhance the breakdown voltage by a field plate
due to the effect of extended depletion layer.
[0094] FIG. 22 is a graph for explaining a relationship between the
operating temperature and the amount of change in threshold. It is
indicated that in the Si-MOS, the higher the operating temperature
becomes, the lower the threshold becomes, but in the LDD-MISFET of
GaN, the temperature dependence is low.
[0095] FIG. 23 is a graph for explaining a relationship between the
operating temperature and the device resistance. It is indicated
that while the Si-MOS depends on the operating temperature and the
resistance of the device increases, the resistance of the device is
constant in the LDD-MISFET of GaN. From FIG. 22 and FIG. 23, it is
indicated that the LDD-MISFET of GaN is superior to the Si-MOS in
terms of the high-temperature operation.
[0096] FIG. 24 is a graph for explaining a relationship between the
breakdown voltage VBD and the gate capacitance per resistance. By
comparison with a general Si-MOS for high frequencies, it is known
that the performance of the LDD-MISFET of GaN is superior (lower
capacitance) by about one digit.
[0097] FIGS. 25A to 25C illustrate comparisons between gate
capacitances of the Si-MOS and the LDD-MISFET of GaN, both having a
chip resistance of 0.1.OMEGA.. The capacitance between gate and
source (GS), the capacitance between gate and drain (GD), and the
capacitance between drain and source (DS) are measured,
respectively. It is known that all the capacitances of the
LDD-MISFET are one-tenth or less of the capacitances of the
Si-MOS.
[0098] FIG. 26 illustrates circuit diagrams for evaluating the
high-frequency operations of the Si-MOS and the LDD-MISFET of GaN,
both having a chip resistance of 0.1.OMEGA.. The transistors
corresponding to HO and LO portions are replaced with the Si-MOS
and the LDD-MISFET of GaN and then performance is evaluated. FIG.
27 is a diagram for explaining respective output waveforms when the
Si-MOS and the LDD-MISFET are operated respectively in the circuits
in FIG. 26. In the evaluation of the operation at an operating
frequency of 300 kHz, as seen remarkably in the waveform of the LO,
the rise at power ON of the Si-MOS becomes dull. From the
comparison of output waveforms, it is known that the loss of the
LDD-MISFET of GaN is low for the high-frequency operation.
[0099] Furthermore, it is possible to use the circuits illustrated
in FIG. 26 also in the SPICE simulation. It is possible to evaluate
the high-frequency operation by inputting the device parameters of
the Si-MOS and the LDD-MISFET of GaN used for the performance
evaluation explained in FIG. 27 to the HO and the LO. FIGS. 28A and
28B are graphs for explaining examples of the calculation results.
It is indicated that while in the operation at 1 MHz of the Si-MOS,
switching becomes difficult, the LDD-MISFET of GaN is sufficiently
operable even at 10 MHz. FIG. 29 is a graph for explaining a
relationship between the operating frequency of each of the Si-MOS
and the LDD-MISFET of GaN and the efficiency. The comparison
between the Si-MOS and the LDD-MISFET of GaN indicates that the
LDD-MISFET of GaN is much superior to the conventional device in
the high frequency region.
[0100] As above, although specific explanation is given on the
basis of the embodiments of the invention made by the inventors of
the present invention, it is needless to say that the present
invention is not limited to the above-described embodiments and
there can be various modifications within the scope not deviating
from its gist.
* * * * *