U.S. patent application number 14/791412 was filed with the patent office on 2016-02-11 for programmable resistance memory elements with electrode interface layer and memory devices including the same.
The applicant listed for this patent is Adesto Technologies Corporation. Invention is credited to Chakravarthy Gopalan, Wei Ti Lee, Yi Ma, Jeffrey Allan Shields.
Application Number | 20160043310 14/791412 |
Document ID | / |
Family ID | 49261183 |
Filed Date | 2016-02-11 |
United States Patent
Application |
20160043310 |
Kind Code |
A1 |
Gopalan; Chakravarthy ; et
al. |
February 11, 2016 |
PROGRAMMABLE RESISTANCE MEMORY ELEMENTS WITH ELECTRODE INTERFACE
LAYER AND MEMORY DEVICES INCLUDING THE SAME
Abstract
A memory element can include a first electrode comprising at
least a first element; a second electrode formed of a conductive
material; and a memory layer comprising a memory material
programmable between different resistance states. The first element
can be ion conductible within the memory material. A second
electrode can include an interface layer in contact with the memory
layer. The interface layer being formed by inclusion of at least
one modifier element not present in a remainder of the second
electrode and not ion conductible within the memory material.
Inventors: |
Gopalan; Chakravarthy;
(Santa Clara, CA) ; Lee; Wei Ti; (San Jose,
CA) ; Ma; Yi; (Santa Clara, CA) ; Shields;
Jeffrey Allan; (Sunnyvale, CA) |
|
Applicant: |
Name |
City |
State |
Country |
Type |
Adesto Technologies Corporation |
Sunnyvale |
CA |
US |
|
|
Family ID: |
49261183 |
Appl. No.: |
14/791412 |
Filed: |
July 4, 2015 |
Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
|
|
13850267 |
Mar 25, 2013 |
9099633 |
|
|
14791412 |
|
|
|
|
61615837 |
Mar 26, 2012 |
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Current U.S.
Class: |
257/4 ;
438/382 |
Current CPC
Class: |
H01L 45/04 20130101;
H01L 45/1266 20130101; H01L 45/16 20130101; H01L 45/142 20130101;
H01L 45/1625 20130101; H01L 45/085 20130101; H01L 45/143 20130101;
H01L 45/1233 20130101; H01L 45/1253 20130101; H01L 45/1608
20130101 |
International
Class: |
H01L 45/00 20060101
H01L045/00 |
Claims
1. A memory element, comprising: a first electrode comprising at
least a first element; a second electrode formed of a conductive
material; and a memory layer disposed between the first electrode
and a second electrode, the memory layer comprising a memory
material programmable between different resistance states, the
first element being ion conductible within the memory material;
wherein the second electrode includes an interface layer on a
surface of the second electrode in contact with the memory layer,
the interface layer formed by inclusion of at least one modifier
element not present in a remainder of the second electrode, the
modifier element not being ion conductible within the memory
material.
2. The memory element of claim 1, wherein: the modifier element is
a non-metal.
3. The memory element of claim 2, wherein: the modifier element is
nitrogen.
4. The memory element of claim 2, wherein: the modifier element is
oxygen.
5. The memory element of claim 4, wherein: the second electrode
comprises a metal; and the interface layer comprises an oxide of
the metal.
6. The memory element of claim 2, wherein: the modifier element is
a semiconductor that is not included in the memory material.
7. The memory element of claim 1, wherein: the interface layer has
a thickness less than one half the thickness of the memory
layer.
8. A memory element, comprising: a first electrode comprising at
least a first element; a second electrode comprising at least
second element; a memory layer disposed between the first electrode
and a second electrode, the memory layer comprising a memory
material programmable between different resistance states, the
first element being ion conductible within the memory material; and
an interface layer on a surface of the second electrode in contact
with the memory layer, the interface layer formed by inclusion of
at least one modifier element not present in a remainder of the
second electrode, the modifier element being a non-metal.
9. The memory element of claim 8, wherein: the modifier element is
selected from the group of: oxygen and nitrogen.
10. The memory element of claim 9, wherein: the interface layer
comprises an oxide of the second element.
11. The memory element of claim 9, wherein: the interface layer
comprises a nitride of the second element.
12. The memory element of claim 8, wherein: the modifier element is
a semiconductor.
13. The memory element of claim 8, wherein: the first electrode,
second electrode and memory layer are vertically stacked, the first
electrode being a top electrode and the second electrode being a
bottom electrode.
14. A method, comprising: forming a first electrode; forming an
interface layer that extends into the first electrode by inclusion
of at least one modifier element not present in a remainder of the
second electrode; forming a memory layer in contact with the
interface layer, the memory layer comprising a memory material
programmable between different resistance states; and forming a
second electrode comprising a first element that is ion conductible
within the memory material; wherein the modifier element is not ion
conductible within the memory material.
15. The method of claim 14, wherein: forming the interface layer
includes treating an exposed surface of the first electrode.
16. The method of claim 15, wherein: treating the exposed surface
of the first electrode includes subjecting the surface to a
temperature cycle.
17. The method of claim 15, wherein: treating the exposed surface
of the first electrode includes oxidizing the surface.
18. The method of claim 15, wherein: treating the exposed surface
of the first electrode includes implanting atoms of the modifier
element into the surface.
19. The method of claim 15, wherein: treating the exposed surface
of the first electrode includes exposing the surface to a plasma
that includes a gas comprising the modifier element.
20. The method of claim 14, wherein: forming the interface layer
includes adding the modifier element in situ as the first electrode
is formed.
Description
[0001] This application is a continuation of U.S. patent
application Ser. No. 13/850,267 filed on Mar. 25, 2013, which
claims the benefit of U.S. provisional patent application Ser. No.
61/615,837, filed on Mar. 26, 2012, the contents all of which are
incorporated by reference herein.
TECHNICAL FIELD
[0002] The present disclosure relates generally to memory devices
with programmable impedance elements, and more particularly to
memory elements that can program a solid electrolyte layer between
different resistance states.
BACKGROUND
[0003] Conventional conductive bridging random access memory
(CBRAM) devices can include CBRAM type elements that can be placed
into a low resistance state with a programming operation, and a
high resistance state with an erase operation. Conventionally,
after a CBRAM device has been fabricated, but before it is
programmed or erased to store data for the very first time (i.e.,
the CBRAM elements are "fresh" elements), the CBRAM device is
subject to a "forming" step. It is believed that the forming step
can create an initial conductive path (i.e., filament) through a
solid electrolyte material, which can be recreated, in some
fashion, in subsequent programming operations (and dissolved in
erase operations).
[0004] A forming step can take a relatively large amount of time in
an integrated circuit manufacturing flow, and thus can present a
production bottleneck. The amount of time consumed in a forming
step can be exacerbated by the presence of "reverse programming".
Reverse programming can occur when erase conditions are applied to
a CBRAM type element, but the element enters a low resistance
state, instead of a desired high resistance state. If reverse
programming occurs, it can take a substantial amount of time to
bring the CBRAM elements from the reverse programmed state to a
proper erased state.
[0005] In some conventional CBRAM devices, the effects of a forming
step can be reversed or reduced if a device is subject to a heat
cycle (such as a solder reflow on a packaged device).
BRIEF DESCRIPTION OF THE DRAWINGS
[0006] FIG. 1 is a side cross sectional view of a memory element
according to one embodiment.
[0007] FIG. 2 is a side cross sectional view of a memory element
according to another embodiment.
[0008] FIG. 3 is a side cross sectional view of a memory element
according to a further embodiment.
[0009] FIGS. 4A to 4D are a series of side cross sectional views
showing a method of making a memory element like that of FIG. 1,
according to one very particular embodiment.
[0010] FIGS. 5A to 5D are a series of side cross sectional views
showing a method of making a memory element like that of FIG. 2,
according to one very particular embodiment.
[0011] FIGS. 6A to 6D are a series of side cross sectional views
showing a method of making a memory element like that of FIG. 3,
according to one very particular embodiment.
[0012] FIG. 7 is a side cross sectional view of a memory element
according to another embodiment.
[0013] FIG. 8 is a side cross sectional view of a memory element
according to another embodiment.
[0014] FIGS. 9A to 9C are a series of side cross sectional views
showing a method of making a memory element like that of FIG. 7,
according to one very particular embodiment.
[0015] FIGS. 10A to 10C are a series of side cross sectional views
showing a method of making a memory element like that of FIG. 8,
according to one very particular embodiment.
[0016] FIGS. 11A-0 to 11A-3 are graphs showing program experimental
results for memory elements according to some embodiments.
[0017] FIGS. 11B-0 to 11 B-3 are graphs showing erase experimental
results for memory elements according to some embodiments.
[0018] FIGS. 11C-0 to 11C-3 are graphs showing reverse program
experimental results for memory elements according to some
embodiments
[0019] FIG. 12 is a table showing experimental results for memory
elements according to particular embodiments.
[0020] FIGS. 13-0 to 13-2 are graphs showing experimental results
for memory elements according to additional embodiments
[0021] FIG. 14 is a table showing experimental results for memory
elements according to particular embodiments.
DETAILED DESCRIPTION
[0022] Embodiments described herein show memory elements and
manufacturing methods that include a memory layer between an anode
electrode and a cathode electrode. A memory layer of a memory
element can have a modifier material formed therein, which can
result in the memory element having a suitable programming response
without the need for a conventional forming step.
[0023] In very particular embodiments, memory elements can be
conductive bridging random access memory (CBRAM) type cells,
programmable between two or more resistance states.
[0024] In the various embodiments, like features may be referred to
by the same reference character but with a first characters
corresponding to the figure number.
[0025] FIG. 1 is a side cross sectional view of a memory element
100 according to an embodiment. A memory element 100 can include a
cathode electrode 102, an interface layer 104, a memory layer 106
and an anode electrode 108. A memory element 100 can be
programmable between two or more different states by altering an
impedance between the cathode and anode electrodes (102 and
108).
[0026] A cathode electrode 102 can be formed from one or more
conductive materials. A cathode electrode 102 can include any
suitable material used to form interconnections, contacts, or vias
in an integrated circuit device. In very particular embodiments, a
cathode electrode 102 can be formed from and of: tungsten,
titanium, titanium nitride, aluminum, tantalum, or tantalum
nitride.
[0027] An interface layer 104 can be formed from a solid
electrolyte with one or more modifier materials. In some
embodiments, a memory element 100 can be a CBRAM element, and
creating an interface layer 104 with modifier materials can alter
the cathode-memory layer interface, enabling CBRAM elements to
function without a conventional forming step.
[0028] In some embodiments, an interface layer 104 can include a
chalcogen based solid electrolyte (e.g., a chalcogenide), a metal
oxide, or a combination thereof. In a particular embodiment, a
solid electrolyte can include germanium sulfide (GeS.sub.2),
germanium--sulfur compounds of different stoichiometries (GeSx)
and/or germanium selenium compounds (e.g., GeSe).
[0029] In some embodiments a modifier material added to a solid
electrolyte can include a metal. A modifier metal can be a
transition metal, including but not limited to copper (Cu),
tantalum (Ta) or ruthenium (Ru),as well as the rare earth elements.
A modifier can also include a post-transition metal such as
aluminum (Al), as but one example. Post-transition metals are
metals from those periodic table groups that occur after the
transition metal groups (i.e., groups IIIA, IVA and VA), and
include alumimun (Al), gallium (Ga), indium (In), thallium (TI),
tin (Sn), lead (Pb) and bismuth (Bi).
[0030] In one very particular embodiment, an interface layer can
include GeSx with Cu as a modifier metal, at 0.1% to 50% (atomic
percent).
[0031] As understood from above, other embodiments can include a
metal oxide with a modifier metal formed therein.
[0032] As will be shown below, inclusion of a modifier metal in an
interface layer may make it possible to program and erase the
memory element without a conventional forming step.
[0033] While modifier materials can include metals incorporated
into a solid electrolyte, in other embodiments, a modifier material
can be a non-metal. In very particular embodiments, a modifier
non-metal can include oxygen (O) or nitrogen (N), as but two
possible examples. In other embodiments, a modifier non-metal can
include a semiconductor or metalloid, such as silicon (Si) or Ge
(where Ge is not part of the solid electrolyte material),
[0034] In one very particular embodiment, an interface layer can
include GeSx with N as a modifier metal, at 0.1% to 40% (atomic
percent).
[0035] Referring still to FIG. 1, in some embodiments, a memory
layer 106 can be formed from the same material as interface layer
104. That is, memory layer 106 and interface layer 104 can form a
single layer of the same material. However, as will be shown below,
in other embodiments such layers are different.
[0036] In some embodiments, a total thickness of memory layer 106
and interface layer 104 can be in the range of 3 to 1000 angstroms
(.ANG.).
[0037] An anode electrode 108 can be formed from one or more metals
that ion conduct within memory layer 106 and interface layer 104.
However, when a modifier metal is included in interface layer 104,
such a metal can be different than the anode metal. In one very
particular embodiment, an anode electrode 108 can be formed of
silver (Ag), while an interface layer 104 can be formed of GeSx
with Cu as a modifier metal.
[0038] FIG. 2 is a side cross sectional view of a memory element
200 according to another embodiment. A memory element 200 can
include structures like those of FIG. 1.
[0039] However, unlike FIG. 1, in FIG. 2, a memory layer 206 can be
different than an interface layer 204. In one embodiment, a memory
layer 206 can be formed from a same solid electrolyte as interface
layer 204, but not include the modifier material(s) present in the
interface layer 204. In very particular embodiments, a memory layer
206 and interface layer 204 can be formed from the same solid
electrolyte, but with the memory layer 206 not including the
modifier material(s). An interface layer 204 can be formed from the
same materials, and subject to the same variation as noted for
interface layer 104 shown in FIG. 1.
[0040] In some embodiments, a total thickness of memory layer 206
and interface layer 204 can be in the range of 3 to 1000 angstroms
(.ANG.). An interface layer 204 can have a thickness less than that
of memory layer 206. In particular embodiments, an interface layer
204 have less than 1/2 the thickness of memory layer 206,
preferably less than 1/4 the thickness of memory layer 206.
[0041] While the embodiments above have shown modifications of a
cathode-memory layer interface with a layer formed on a cathode
electrode, other embodiments can modify a cathode electrode
material to form an interface layer. One such embodiment is shown
in FIG. 3.
[0042] FIG. 3 shows a memory element 300 according to another
embodiment in a side cross sectional view. A memory element 300 can
include structures like those of FIG. 1.
[0043] Unlike FIG. 1 or 2, an interface layer 304 can be formed as
part of a surface of cathode electrode 302. An interface layer 304
can be formed from the same conductive materials as cathode
electrode 302, but in addition, can also include one or more
modifier materials. Such modifier materials an include any of those
noted herein, or equivalents, including non-metals and/or
metals.
[0044] In some embodiments, an interface layer 304 can extend into
a cathode electrode 302 to a depth in the range of 3 to 1000
angstroms (.ANG.).
[0045] A memory layer 306 can include one or more solid
electrolytes. In some embodiments, a solid electrolyte of interface
layer 304 can include a chalcogenide, a metal oxide, or
combinations thereof. In a particular embodiment, a solid
electrolyte can include GeS.sub.2, GeSx and/or GeSe.
[0046] While the embodiments of FIGS. 1 to 3 show memory elements
with anode electrodes formed over cathode electrodes, other
embodiments can have different orientations. As but one example,
the structures shown in FIGS. 1-3 can have a reverse vertical
order, with a cathode being formed over an anode, and the interface
layers being formed over the memory layers.
[0047] FIGS. 4A to 4D are a sequence of side cross sectional views
showing one particular method of forming a memory element like that
of FIG. 1, in which an interface layer and memory layer can have
the same structure.
[0048] FIG. 4A shows a cathode electrode 402 formed in an
insulating material 410. A cathode electrode 402 can have a surface
(in this embodiment a top surface) exposed.
[0049] FIG. 4B shows the formation of interface layer 404 in
contact with the exposed surface of cathode electrode 402. In
particular embodiments, an interface layer 404 can be deposited
with sputtering methods. In one embodiment, such sputtering can
include co-sputtering one target formed from one or more solid
electrolyte materials, and another target that includes a modifier
material. In another embodiment, such sputtering can sputter one
target that includes both a solid electrolyte material and a
modifier material. In particular embodiments, sputtering can
include physical vapor deposition (PVD). Sputtering can be a
suitable method for modifier materials that are metals (e.g., Cu,
Ta, Ru, Al).
[0050] In addition or alternatively, an interface layer 404 can be
deposited with reactive sputtering. More particularly, one or more
gases containing the modifier materials can be introduced into the
plasma. Reactive sputtering can be a suitable method for modifier
materials that are non-metals (e.g., O, N). In a particular
embodiment, a reactive sputtering process can sputter GeSx and/or
GeS.sub.2 in a plasma formed by argon gas (Ar) together with
nitrogen gas (N.sub.2) providing non-metal modifier N. A flow ratio
between N.sub.2:Ar can be in the range of 0.05 to 2.
[0051] It is understood that an interface layer 404 can be formed
form any other suitable method. Such alternate methods can include,
but are not limited to: evaporative methods, chemical vapor
deposition (CVD), including plasma enhanced CVD, atomic layer
deposition, or electroplating, as but a few examples.
[0052] FIG. 4C shows the formation of memory layer 406. In one
embodiment, a memory layer 406 can be formed in the same manner as
interface layer 404. That is, interface layer 404 and memory layer
406 can be formed in a continuous deposition step. However, in some
embodiments, an interface layer 404 can be formed as a separate
layer than memory layer 406.
[0053] FIG. 4D shows the formation of anode electrode 408 over and
in contact with memory layer 406.
[0054] FIGS. 5A to 5D are a sequence of side cross sectional views
showing one particular method of forming a memory element like that
of FIG. 2, in which an interface layer can be different from a
memory layer.
[0055] FIGS. 5A and 5B show steps like that of FIGS. 4A and 4B,
respectively, and equivalents. Such steps can be subject to the
same variations.
[0056] FIG. 5C shows the formation of memory layer 506. In one
embodiment, a memory layer 506 can be formed in the same manner as
interface layer 504, but not include modifier material(s), or have
a different concentration of modifier material(s). Thus, in some
embodiments an interface layer 504 and memory layer 506 can be
formed with a same deposition type, but turning off, or otherwise
altering a source of modifying materials while forming the memory
layer.
[0057] In other embodiments, an interface layer 504 can be formed
as a separate layer than memory layer 506. Further, a solid
electrolyte material of memory layer 506 can be different than that
of interface layer 504.
[0058] FIG. 5D shows a step like that of FIG. 5D, and can be
subject to the same variations.
[0059] FIGS. 6A to 6D are a sequence of side cross sectional views
showing one particular method of forming a memory element like that
of FIG. 3, in which a bottom electrode can include an interface
layer.
[0060] FIG. 6A shows a step like that of FIG. 5A, and can be
subject to the same variations.
[0061] FIG. 6B shows the forming of interface layer 604 as part of
a surface of cathode electrode 602. In some embodiments, an
interface layer 604 can be created by treating of a surface of
cathode electrode 602. A treating of the surface can incorporate
modifier materials into a top portion of cathode electrode 602 to
thereby form interface layer 604. A surface treatment can include
any suitable method that can form a modifier material(s) to a
desired depth. In particular embodiments, a surface treatment can
include any of: subjecting the surface to a temperature cycle in an
environment that includes the modifier material; oxidizing the
surface; ion implanting into the surface; and/or exposing the
surface to a plasma having a gas that includes the modifier
material.
[0062] In alternate embodiments, an interface layer can be created
with methods noted in FIGS. 4A to 4D. In particular, as a cathode
electrode is being formed, modifier material(s) can be
introduced.
[0063] FIG. 6C shows steps like that of FIG. 5C, or
equivalents.
[0064] FIG. 6D shows steps like that of FIG. 5D, or
equivalents.
[0065] While the embodiments of FIGS. 1 to 6D show a memory element
having an interface layer formed between a cathode and a memory
material, other embodiments can include an interface layer between
an anode and a memory material. Examples of such embodiments are
shown in FIGS. 7 to 100.
[0066] FIG. 7 is a side cross sectional view showing a memory
element 700 according to another embodiment. A memory element 700
can include structures like those of FIG. 2.
[0067] Like FIG. 2, in FIG. 7 a memory layer 706 can be different
than an interface layer 704. However, unlike FIG. 2, an interface
layer 704 can be formed between anode electrode 708 and memory
layer 706. In one embodiment, a memory layer 706 can be formed from
a solid electrolyte, and an interface layer 704 can be formed from
the same solid electrolyte, but also include one or more modifier
material(s) not present in the memory layer 706.
[0068] An interface layer 704 can be formed from the same
materials, and subject to the same variation as noted for interface
layer 204 shown in FIG. 2.
[0069] FIG. 8 is a side cross sectional view showing a memory
element 800 according to another embodiment. A memory element 800
can include structures like those of FIG. 7.
[0070] Unlike FIG. 7, an interface layer 804 can be formed as part
of anode electrode 808. An interface layer 804 can be formed from
the same conductive materials as anode electrode 808, but in
addition, can also include one or more modifier materials. Such
modifier materials can include any of those noted herein, or
equivalents, including non-metals and/or metals.
[0071] In one very particular embodiment, an anode electrode 808
can be formed of silver, and an interface layer 804 can be formed
of copper.
[0072] In some embodiments, an interface layer 804 can occupy an
initial thickness of anode electrode 808 in the range of 3 to 1000
angstroms (.ANG.).
[0073] A memory layer 806 can include one or more solid
electrolytes. In some embodiments, a solid electrolyte of interface
layer 804 can include a chalcogenide, a metal oxide, or
combinations thereof. In a particular embodiment, a solid
electrolyte can include GeS.sub.2, GeSx and/or GeSe.
[0074] FIGS. 9A to 9C are a sequence of side cross sectional views
showing one particular method of forming a memory element like that
of FIG. 7, in which an interface layer can be formed between an
anode and a memory layer.
[0075] FIG. 9A can shows a step like that of FIG. 5C (the formation
of a memory layer 906). However, unlike FIG. 5C, such a memory
layer is formed on a cathode 902, and not an interface layer.
[0076] FIG. 9B shows a step like that of FIG. 5B (the formation of
an interface layer 904). However, unlike FIG. 5B, such an interface
layer is formed on a top portion of memory layer 906 and not a
cathode.
[0077] FIG. 9C shows a step like that of FIG. 5D. An anode 908 can
be formed over and in contact with interface layer 904.
[0078] FIGS. 10A to 100 are side cross sectional views showing one
particular method of forming a memory element like that of FIG. 8,
in which an interface layer can occupy a portion of an anode that
interfaces with a memory layer.
[0079] FIG. 10A shows the forming of interface layer 1004 as part
of an initial portion of anode electrode 1008. In some embodiments,
an interface layer 1004 can be created by treating an initial
portion of an anode electrode 1008. A treating of the anode
electrode can incorporate modifier materials into an initial
portion of anode electrode 1008 to thereby form interface layer
1004. A surface treatment can include any suitable method that can
form a modifier material(s) to a desired depth.
[0080] In particular embodiments, an interface layer can be created
with methods noted in FIGS. 4A to 4D, or equivalents. In
particular, as an anode electrode is being formed, modifier
material(s) can be introduced.
[0081] In alternate embodiments, a surface treatment can include
any of: depositing a modifier material; subjecting the surface to a
temperature cycle in an environment that includes the modifier
material; oxidizing the surface; ion implanting into the surface;
and exposing the surface to a plasma having a gas that includes the
modifier material.
[0082] FIG. 10B shows a step like that of FIG. 5C (formation of the
rest of an anode electrode). In one embodiment, an anode electrode
1008 can be formed in the same manner as interface layer 1004, but
not include modifier material(s), or have a different concentration
of modifier material(s). Thus, in some embodiments an interface
layer 1004 and anode electrode 1008 can be formed with same
formation methods, but turning off, or otherwise altering a source
of modifying materials while forming the anode electrode.
[0083] FIG. 10C shows a step like that of FIG. 5D (formation of the
rest of an anode electrode).
[0084] FIGS. 11A-0 to 11A-3 are graphs illustrating experimental
results for memory elements according to particular embodiments.
FIGS. 11A-0 to 11A-3 show CBRAM type elements having an anode
formed from Ag, a memory material formed form GeSx, with Cu as a
modifier material. FIG. 11A-0 shows results for conventional CBRAM
elements, having GeSx as a memory layer, and no Cu modifiers. FIG.
11A-1 shows CBRAM elements having 10% (atomic percent) Cu in GeSx.
FIG. 11A-2 shows CBRAM elements having 15% (atomic percent) Cu in
GeSx. FIG. 11A-3 shows CBRAM elements that include a 20 angstrom Cu
interfacial layer formed over the memory material and below an
anode electrode of silver. The results of FIGS. 11A-0 to 11A-3 are
for "fresh" elements.
[0085] FIGS. 11A-0 to 11A-3 show first time program yields versus
pulse width (in microseconds (.mu.s)), for various programming
voltages (0.4V, 0.8V, 1.2V, 1.6V). FIGS. 11B-0 to 11B-3 are graphs
illustrating additional experimental results for memory elements
according to particular embodiments. FIGS. 11B-0 to 11B-3 show
results for elements like those of FIGS. 11A-0 to 11A-3,
respectively, but for first time erase yields for the various erase
voltages. The results of FIGS. 11B-0 to 11B-3 are also for fresh
elements.
[0086] FIGS. 11C-0 to 11C-3 are graphs illustrating further
experimental results for memory elements according to particular
embodiments. FIGS. 11C-0 to 11C-3 show the occurrence of reverse
programming for elements like those of FIGS. 11A-0 to 11A-3,
respectively.
[0087] As shown in FIGS. 11A-0 to 11C-3, a smaller concentration of
Cu (10%), and the Cu interface, can provide relatively fast program
and erase speed, while reducing RPG. Higher concentrations of Cu
(15%) can provide slower program/erase speeds, while essentially
eliminating RPG in the samples.
[0088] FIG. 12 is a table showing program yields (PG Yield), erase
yields (ER Yield) and a page program times (PAGE time) (in
milliseconds) for memory elements according to embodiments having
10% Cu in a GeSx memory layer. Such yields and program times are
for fresh elements.
[0089] As shown, page program times can be as short as 2 ms. This
is comparable to conventional elements that have been subject to a
forming step.
[0090] FIGS. 13-0 to 13-2 are graphs illustrating experimental
results for memory elements according to additional embodiments.
For FIGS. 13-0 to 13-2, CBRAM elements have a GeSx memory layer
with a nitrided bottom layer (i.e., N as a non-metal modifier).
FIG. 13-0 shows first time program yields versus pulse width for
various programming voltages (0.4V, 0.8V, 1.2V, 1.6V). FIG. 13-1
shows first time erase yields for the various erase voltages. FIG.
13-2 shows the occurrence of reverse programming for such elements.
The CBRAM elements are fresh elements.
[0091] As shown, the introduction of a nitride GeSx interface layer
can provide program/erase times comparable to conventional elements
subject to a forming step, with very little RPG.
[0092] FIG. 14 is a table showing experimental results for CBRAM
elements like that of FIGS. 13-0 to 13-2 (i.e., CBRAM elements
having a bottom nitride GeSx layer). Rows "NO PC" shows
program/erase yields (PG Yield/ER Yield) and page program times (PG
Page Time/ER Page Time) for elements that have not been subject to
a forming step. Elements subject to a forming step are shown by
rows "3 PC". As shown, yields are satisfactory with no forming
step. Further, page program times can be significantly faster than
"fresh" conventional elements.
[0093] It is understood that the results shown in FIGS. 11 to 14
are but experimental results, and other embodiments may have
different result, including better results, with variations in
materials, dimensions, or fabrication process.
[0094] Embodiments of the invention can improve erase times for
fresh elements by reducing and/or eliminating reverse programming.
Embodiments may also enable memory elements with solid electrolyte
memory layers to be fabricated for use without a forming step, or
with a forming step that is shorter than conventional
approaches.
[0095] It should be appreciated that in the foregoing description
of exemplary embodiments, various features are sometimes grouped
together in a single embodiment, figure, or description thereof for
the purpose of streamlining the disclosure aiding in the
understanding of one or more of the various inventive aspects. This
method of disclosure, however, is not to be interpreted as
reflecting an intention that the claimed invention requires more
features than are expressly recited in each claim. Rather, as the
following claims reflect, inventive aspects lie in less than all
features of a single foregoing disclosed embodiment. Thus, the
claims following the detailed description are hereby expressly
incorporated into this detailed description, with each claim
standing on its own as a separate embodiment of this invention.
[0096] It is also understood that the embodiments of the invention
may be practiced in the absence of an element and/or step not
specifically disclosed. That is, an inventive feature of the
invention can be elimination of an element.
[0097] Accordingly, while the various aspects of the particular
embodiments set forth herein have been described in detail, the
present invention could be subject to various changes,
substitutions, and alterations without departing from the spirit
and scope of the invention.
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