U.S. patent application number 14/733153 was filed with the patent office on 2015-09-24 for semiconductor device having plural selection lines.
This patent application is currently assigned to PS4 Luxco S.a.r.l.. The applicant listed for this patent is PS4 Luxco S.a.r.l.. Invention is credited to Hidekazu Noguchi.
Application Number | 20150269988 14/733153 |
Document ID | / |
Family ID | 48466781 |
Filed Date | 2015-09-24 |
United States Patent
Application |
20150269988 |
Kind Code |
A1 |
Noguchi; Hidekazu |
September 24, 2015 |
Semiconductor Device Having Plural Selection Lines
Abstract
The semiconductor device includes a plurality of word lines
classified into a plurality of groups and a selection circuit for
selecting a word line according to an address. The selection
circuit has a level shifter arranged for each of the groups. The
address includes a first address for selecting any of the groups
and a second address for selecting a word line in the selected
group. The selection circuit selects a word line by allowing supply
of active potential for word line by the level shifter of a group
selected by the first address and further allowing supply of the
active potential to the word line selected by the second address
out of a plurality of word lines belonging to the selected
group.
Inventors: |
Noguchi; Hidekazu; (Tokyo,
JP) |
|
Applicant: |
Name |
City |
State |
Country |
Type |
PS4 Luxco S.a.r.l. |
Luxembourg |
|
LU |
|
|
Assignee: |
PS4 Luxco S.a.r.l.
Luxembourg
LU
|
Family ID: |
48466781 |
Appl. No.: |
14/733153 |
Filed: |
June 8, 2015 |
Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
|
|
13683538 |
Nov 21, 2012 |
9053759 |
|
|
14733153 |
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Current U.S.
Class: |
365/191 |
Current CPC
Class: |
G11C 11/4097 20130101;
G11C 8/08 20130101; G11C 11/4087 20130101; G11C 11/4085 20130101;
G11C 8/14 20130101; G11C 11/4094 20130101; G11C 7/00 20130101; G11C
8/06 20130101 |
International
Class: |
G11C 11/4094 20060101
G11C011/4094; G11C 11/408 20060101 G11C011/408 |
Foreign Application Data
Date |
Code |
Application Number |
Nov 25, 2011 |
JP |
2011-257175 |
Claims
1. A semiconductor device comprising: a plurality of circuit sets
each including a plurality of drive circuits; a plurality of
selection circuits each assigned to an associated one of the
circuit sets such that each of the selection circuits are coupled
in common to the driver circuits included in the associated one of
the circuit sets; and a plurality of selection lines, wherein one
of the selection circuits selected by a first signal supplies an
active potential to a first output node thereof, and each of the
drive circuits includes a first transistor coupled between an
associated one of the selection lines and the first output node of
the associated one of the selection circuits, the first transistor
having a control electrode supplied with a second signal that is
different from the first signal.
Description
CONTINUING DATA
[0001] This application is a continuation of U.S. patent
application Ser. No. 13/683,538, filed on Nov. 21, 2012, now U.S.
Pat. No. 9,053,759, issued on Jun. 9, 2015, which claims the
benefit of priority from Japanese patent application No.
2011-257175, filed on Nov. 25, 2011, the disclosures of which are
incorporated herein by reference in their entireties.
BACKGROUND OF THE INVENTION
[0002] 1. Field of the Invention
[0003] The present invention relates to a semiconductor device and
particularly relates to a semiconductor device having a plurality
of word lines selectively activated.
[0004] 2. Description of Related Art
[0005] In recent years, many electronic apparatuses employ
semiconductor device such as a DRAM (Dynamic Random Access Memory)
as a memory device. A DRAM stores data by holding electric charges
in memory cells arranged at intersection points of a plurality of
word lines and a plurality of bit lines. Accordingly, access to a
desired memory cell is made by selecting a word line and a bit line
based on address information.
[0006] Word lines are connected to word drivers. Word drivers drive
a selected word line based on address information supplied thereto.
Note that techniques related to the memory cell and the word driver
are described in Japanese Patent Application Laid-open No.
H11-111944, Japanese Patent Application Laid-open No. H11-68063 and
Japanese Patent Application Laid-open No. 2008-135099.
[0007] In accordance with higher integration of memory cells, the
increasing number of word lines leads to place a larger load on
word drivers that drive word lines. The increasing number of word
lines leads to expand a circuit scale in the semiconductor device.
In addition, the size in a direction to repeat word drivers is
restricted by the size of memory cells and therefore the size that
can be ensured for word drivers is reduced due to higher
integration of memory cells. As a result, under a limited repeating
pitch and limited wiring layers, it is difficult to pull out word
lines from both sides of one word driver. Therefore, such a problem
is often dealt with by juxtaposing two word drivers to simply pull
out word lines only from one side of each driver. However, if a
repeating pitch is further reduced with a larger reduction rate to
process memory cells than drivers, the method of putting two word
drivers side by side imposes restrictions on further reduction of a
circuit scale in the semiconductor device.
[0008] Note that in a hierarchical word line structure, word lines
are composed of MWL (Main Word Line) and SWL (Sub-Word Line). A
plurality of SWLs is related to one of MWLs. Based on address
information, MWL is selected and one SWL is selected out of a
plurality of SWL related to the selected MWL. Even in a memory with
such a hierarchical word line structure, a similar problem arises
with MWL and main word drivers.
SUMMARY
[0009] In one embodiment, there is provided a semiconductor device
that includes: a plurality of circuit sets each including a
plurality of drive circuits; a plurality of selection circuits each
assigned to an associated one of the circuit sets such that each of
the selection circuits are coupled in common to the driver circuits
included in the associated one of the circuit sets; and a plurality
of selection lines. One of the selection circuits selected by a
first signal supplies an active potential to a first output node
thereof. Each of the drive circuits includes a first transistor
coupled between an associated one of the selection lines and the
first output node of the associated one of the selection circuits,
the first transistor having a control electrode supplied with a
second signal that id different from the first signal.
[0010] In another embodiment, there is provide a semiconductor
device that includes: a plurality of word lines classified into a
plurality of groups; and a selection circuit selecting one of the
word lines according to an address signal. The selection circuit
includes a plurality of level shifters each assigned to an
associated one of the groups. The address signal includes a first
signal that selects one of the groups and a second signal that
selects one of the word lines in the selected group. One of the
level shifters assigned to the selected group selected by the first
signal supplies an active potential to one of the word lines
selected by the second signal.
[0011] The present invention makes it easier to reduce the size of
a semiconductor device by reducing in the size of word line
selection circuits.
BRIEF DESCRIPTION OF THE DRAWINGS
[0012] FIG. 1 is a schematic diagram showing a layout of memory
banks in a semiconductor device according to an embodiment of the
present invention;
[0013] FIG. 2 is an enlarged view of an area surrounded by a broken
line in FIG. 1;
[0014] FIG. 3 is a schematic circuit diagram showing a memory mat
and the periphery thereof;
[0015] FIG. 4 is a circuit diagram of main word drivers that the
inventor has conceived as a prototype in the course of making the
present invention;
[0016] FIG. 5 is a circuit diagram of the first group selection
circuit shown in FIG. 5;
[0017] FIG. 6 is a layout diagram of the memory cell arrays and the
main word drivers that the inventor has conceived as a prototype in
the course of making the present invention;
[0018] FIG. 7 is a circuit diagram of the main word drivers MWD
according to the embodiment of the present invention.
[0019] FIG. 8 is a circuit diagram of the first group selection
circuit shown in FIG. 7;
[0020] FIG. 9 is a circuit diagram of the second group selection
circuit shown in FIG. 8;
[0021] FIG. 10 is a layout diagram of the memory cell arrays 108
and the main drivers MWD according to the embodiment of the present
invention;
[0022] FIG. 11 is a layout diagram showing a relationship between
the adjacent second group selection circuits and the main word
lines;
[0023] FIG. 12 is a wiring diagram showing more details of the
relationship between the second group selection circuits and the
main word lines;
[0024] FIG. 13 is a conceptual diagram of the first group selection
circuit of the prototype example shown in FIG. 5; and
[0025] FIG. 14 is a conceptual diagram of the second group
selection circuit shown in FIG. 9.
DETAILED DESCRIPTION OF THE EMBODIMENTS
[0026] In the embodiment of the present invention, a DRAM as one of
the semiconductor devices is assumed, but the present invention is
not limited to DRAM. Also, selection of a main word line will be
mainly described in the present embodiment but the present
invention is applicable to selection of a signal line other than a
main word line.
[0027] Referring now to FIGS. 1 and 2, the memory cell array 108
has a plurality of memory banks 106. Each of the memory banks 106
serves as an independently accessible storage area and contains a
plurality of memory mats (to be described later).
[0028] In the memory banks 106, a plurality of word lines WL
(including main word lines and sub-word lines) and bit lines BL are
arranged vertically and horizontally and memory cells MC are
arranged at intersection points of these lines. Owing to an
electric charge held by each of the memory cells MC, information of
one bit is stored therein. In the periphery of the memory banks
106, peripheral circuits such as row decoders 102 and column
decoders 104 are arranged. The row decoders 102 select any of the
word lines WL and the column decoders 104 select any of the bit
lines BL. The memory cell MC positioned at an intersection point of
the word line WL and the bit line BL to be selected becomes target
to be accessed.
[0029] Turning to FIG. 3, each of the memory banks 106 has a
plurality of the memory mats 110. In each of the memory mats 110,
the word lines WL (including main word lines and sub-word lines)
and the bit lines BL are arranged. In the periphery of the memory
mats 110, sense amplifier circuits SA and sub-word drivers SWD are
arranged. Each of the row decoders 102 includes a row control
circuit 112 and a main word driver MWD.
[0030] The main word driver MWD selects a main word line according
to a part of address information. Address information is also
supplied to the row control circuit 112. In accordance with address
information decoded by the row control circuit 112, the sub-word
drivers SWD select sub-word lines. A plurality of sub-word lines is
related to one main word line and a plurality of main word lines is
related to one memory mat 110. The memory bank 106, a main word
line and a sub-word line are specified sequentially by a part of
address information.
[0031] Address information is also supplied to the column decoders
104 and the column decoders 104 select any of the bit lines BL. Any
of the bit lines BL to be selected is connected to a local I/O line
via the sense amplifier circuit SA. Electric potential of any of
the memory cell MC positioned at an intersection point of any of
the word lines WL (or sub-word lines) and the bit lines BL that
have been selected is amplified by the sense amplifier circuit SA
via the bit line BL and outputted to the outside as data via a
local I/O line. Also, data supplied as electric potential from the
outside via the sense amplifier circuits SA is supplied to the
memory cells MC in order to execute a write process. In the present
embodiment, the main word drivers MWD function as "selection
circuit" for main word line. Next, common structures of the main
word drivers MWD will be explained in association with FIG. 4 to
FIG. 6 and problems therein will be pointed out.
[0032] Turning to FIG. 4, in the prototype example, address
information of fourteen bits (i.e. A0 to A13) are used to select
any of the memory banks 106, the word lines WL (including main word
lines and sub-word lines) and the bit lines BL. Explanation will be
made on the assumption that any of the main word lines MWL is
selected by a total of seven bits including A3 to A9 out of the
address information. The addresses A3 to A9 relating to the
selection of any of the main word lines MWL will be referred to as
"main word address" hereinafter.
[0033] In the configuration of FIG. 4, one hundred twenty eight of
the main word lines MWL are classified into sixteen groups (i.e.
first groups) each of which contains eight lines such as main word
lines MWL0 to 7, MWL8 to 15, . . . , and MWL124 to 127. First group
selection circuits 114 are allocated to the respective first
groups. The main word driver MWD includes sixteen of first group
selection circuits 114a to 114p.
[0034] A reset signal DP is a low active signal. When the reset
signal DP is activated to a low level, the entire main word lines
MWL0 to MWL127 become non-selective. An enable signal EN is also a
low active signal. When the enable signal EN is inactive (in a high
level), selection of the main word lines MWL is impossible.
Addresses A6 to A9 of four bits included the main word address A3
to A9 are used to select any of the first group selection circuits
114. The addresses A6 to A9 relating to the group selection are
referred to as "first address".
[0035] Turning to FIG. 5, the first group selection circuit 114a
includes eight of the main word lines MWL0 to MWL7 to which word
activation circuits 116_0 to 116_7 are related, respectively.
Addresses A3 to A5 of three bits included in the main word address
A3 to A9 are used to select any of the word activation circuits
116. The addresses A3 to A5 relating to the selection of the main
word lines MWL are referred to as "second address".
[0036] Each of the word activation circuits 116 includes a level
shifter 118 and a third inverter 120. The level shifter 118 is
controlled by the second address A3 to A5 and generates first
potential VPP which is inactive potential and second potential VSS
which is active potential for the main word lines MWL. The level
shifter 118 includes a first inverter 122 and a second inverter
124.
[0037] It is assumed that the first group selection circuit 114a is
selected by the first address A6 to A9 when the reset signal DP is
turned off (in a high level) and the enable signal EN is turned on
(in a low level). The first inverter 122 in each of the word
activation circuits 116 is a circuit in which a transistor Tr1 of
PMOS (Positive channel Metal Oxide Semiconductor) and a transistor
Tr2 of NMOS (Negative channel Metal Oxide Semiconductor) are
connected in series to each other and one end of the first inverter
122 (on the transistor Tr1 side) is fixed to the inactive potential
VPP (or first potential). The enable signal EN is inputted to the
other end of the first inverter 122 (on the transistor Tr2 side)
via transistors Tr10 and Tr11 controlled by the first address A6 to
A9. When the transistors Tr10 and Tr11 are turned on and the enable
signal EN is active, the active potential VSS (or second potential)
is supplied to the other end of the first inverter 122 (on the
transistor Tr2 side). Thus, when the first group selection circuit
114a is selected, the inactive potential VPP and the active
potential VSS are supplied to the first inverters 122 in the entire
word activation circuits 116_0 to 116_7.
[0038] Here, it is assumed that the main word line MWL0 is
selected. At this time, the second address (A3, A4, A5) is equal to
(000). In the first inverter 122 of the word activation circuit
116_0, the transistor Tr2 is turned on and the active potential VSS
is outputted. The second inverter 124 includes transistors Tr3 to
Tr6 and outputs the inactive potential VPP by inverting the output
of the first inverter 122. The third inverter 120 includes
transistors Tr7 to Tr9 and outputs the active potential VSS by
inverting the output of the second inverter 124. Thus, the active
potential VSS (or second potential) is supplied to the main word
line MWL0 and the main word line MWL0 is activated. In contrast,
the inactive potential VPP is supplied to the entire remaining main
word lines MWL.
[0039] In the structure as shown above, the level shifter 118 and
the third inverter 120 are provided for each of the word activation
circuits 116. In other words, one hundred twenty eight of the level
shifters 118 need to be prepared for one hundred twenty eight of
the main word lines MWL.
[0040] Turning to FIG. 6, in the prototype example, the main word
drivers MWD shown in FIG. 4 and FIG. 5 control the memory mats 110
only on one side. It is because the main word lines MWL can be
pulled out only from one side of the main word drivers MWD due to a
large circuit scale and a complicated wiring layout in the main
word drivers MWD. The size in a direction to repeat the drivers is
also restricted by the size of the memory cells and there is no
room to spare on the layout, which means there is no room to pull
out the main word lines toward the level shifter 118, whereby
making it difficult for one main word driver MWD to collectively
control the main word lines MWL on both sides thereof.
[0041] FIG. 6 shows memory banks 106a are arranged on both sides in
areas in which a row decoder 102a and a row decoder 102b are
arranged. In the common structure of the main word drivers MWD
shown in FIG. 4 and FIG. 5, four of the main word drivers MWD need
to be arranged for two of the memory banks 106a and 106b. In order
to reduce an area occupied by the main word drivers MWD in the
memory cell arrays 108, the main drivers MWD will be composed as
shown in FIG. 7 to FIG. 9 in the present embodiment.
[0042] Turning to FIG. 7, according to the present embodiment, one
hundred twenty eight of the main word lines MWL are classified into
eight groups (i.e. first groups) each of which contains sixteen
lines such as main word lines MWL0 to 15, MWL16 to 31, . . . , and
MWL96 to 127. First group selection circuits 126 are allocated to
the respective first groups. That is, the main word drivers MWD
include eight of first group selection circuits 126a to 126h.
[0043] The reset signal DP is a low active signal. When the reset
signal DP is activated, the entire main word lines MWL0 to MWL127
become non-selective. The enable signal EN is also a low active
signal. When the enable signal EN is inactive, selection of the
main word lines MWL is impossible. Addresses A7 to A9 of three bits
included in the main word address A3 to A9 are used to select any
of the first group selection circuits 126. In the present
embodiment, addresses A5 to A9 of 5 bits correspond to the "first
address".
[0044] As shown in FIG. 8, sixteen of the main word lines MWL0 to
15 related to the first group selection circuit 126a are further
classified into four groups (i.e. second groups) each of which
contains four lines. Second group selection circuits 128 are
allocated to the respective second groups. That is, the first group
selection circuit 126a includes four of second group selection
circuits 128a to 128d. Addresses A5 and A6 of two bits included in
the first address A5 to A9 are used to select any of the second
group selection circuits 128.
[0045] As shown in FIG. 9, four of the main word lines MWL are
related to the second group selection circuit 128a by which the
level shifter 118 is shared. When the second group selection
circuit 128a is selected, the first inverter 122 outputs potential
of a low level and the second inverter 124 outputs potential of a
high level. As a result, a transistor Tr14 is turned on. Second
address of two bits including A3 and A4 is used to select any one
line out of four of the main word lines MWL0 to MWL3.
[0046] It is assumed that the main word line MWL0 is selected. The
first potential VPP and the second potential VSS are supplied to
each one of four of third inverters 120a to 120d. A transistor
Tr9_0 in the third inverter 120a corresponding to the main word
line MWL0 is turned on by the address (A3, A4) that is equal to (0,
0) and the remaining transistors Tr9_1 to Tr9_3 are turned off. As
a result, the third inverter 120a outputs the active potential VSS
and the remaining third inverters 120b to 120d output high
impedance.
[0047] Transistors Tr12_0 to Tr12_3 are connected to rear stages of
the third inverters 120a to 120d, respectively. The transistors
Tr12 function as "forcibly setting circuit" for supplying the
inactive potential VPP. When the main word line MWL0 is selected,
only the transistor TR12_0 is turned off and the remaining
transistors Tr12_1 to Tr12_3 are turned on. The inactive potential
VPP is supplied to the main word lines MWL1 to 3 that are
non-selected via the transistors Tr12_1 to Tr12_3. The active
potential VSS is supplied to the selected main word line MWL0 via
the transistor Tr9_0 in the third inverter 120a. One of the main
word lines MWL is thus selected.
[0048] When the main word line MWL1 is selected, the transistor
Tr9_1 in the third inverter 120b is turned on and the remaining
transistors Tr9_0, Tr9_2 and Tr9_3 are turned off. As a result, the
active potential VSS is supplied to the main word line MWL1 and the
inactive potential VPP is supplied to the remaining non-selected
main word lines MWL via the transistors Tr12 (forcibly setting
circuit).
[0049] Note that the transistor Tr14 and each of the transistors
Tr9 are desirably controlled so that the transistor Tr14 is turned
on first. By turning on the transistor Tr14 first, a potential
difference between a source and a drain can be alleviated in the
transistor Tr14 and the transistors Tr9, whereby making it easier
to suppress hot carrier degradation. Conventional methods have also
employed insertion of NMOS for suppression of hot carrier
degradation in many cases. The present embodiment can use NMOS (or
the transistor Tr14) without making any changes.
[0050] As stated above, the level shifter 118 is shared by a
plurality of the word activation circuits 116 in the present
embodiment. Therefore, a circuit scale in the second group
selection circuits 128 can be reduced substantially and there is
room to spare for a wiring layout. As a result, it is possible to
pull out the main word lines MWL to both sides of the main word
drivers MWD. Allowing more room for layout will result in easier
use of a transistor with a high driving capacity in the third
inverters 120. This will result in easier supply of sufficient
active potential and inactive potential to the main word lines MWL,
which also contributes to pulling out the main word lines MWL to
both sides. Meanwhile, the size of the transistors Tr12 that do not
contribute to a driving speed of the main word lines MWL is made
smaller than the size of other transistors Tr included in the third
inverters 120.
[0051] Turning to FIG. 10, the main word drivers MWD control the
memory banks 106 on both sides thereof in the present embodiment.
As a result, two of the memory banks 106a and 106b can be
controlled by two of the main word drivers MWD as shown in FIG. 10.
This will result in reduction of an area occupied by the main word
drivers MWD in the memory cell arrays 108.
[0052] As shown in FIG. 11 four of the main word lines MWL0 to MWL3
corresponding to the second group selection circuit 128a and four
of the main word lines MWL4 to MWL7 corresponding to the second
group selection circuit 128b are arranged alternately. This is for
the purpose of suppressing disturbances of potential in the main
word lines MWL caused by coupling.
[0053] Referring now to FIG. 12 assumed that the main word line
MWL1 of the second group selection circuit 128a is selected.
Firstly, a level shifter 118a in the second group selection circuit
128a is activated and the active potential VSS is supplied to the
main word line MWL1. At this time, transistors Tr7_1 and Tr9_1 are
both turned on. In contrast, the inactive potential VPP is supplied
to the main word lines MWL0, MWL2 and MWL3 by turning on the
transistors Tr12_0, Tr12_2 and Tr12_3 (i.e. forcibly setting
circuit). At this time, due to coupling to the main word line MWL1,
a voltage drop from the inactive potential VPP to the active
potential VSS may possibly occur in potential of the non-selected
main word lines MWL0, MWL2 and MWL3. It is because a force to fix
the main word lines MWL0, MWL2 and MWL3 to the inactive potential
VPP is weaker than a force to fix the main word line MWL1 to the
active potential VSS due to the fact that the transistors Tr12
(i.e. forcibly setting circuit) have a less driving capacity than
the transistors Tr7 and the transistors Tr9.
[0054] Meanwhile, since the second group selection circuit 128b is
non-selected, a level shifter 118b in the second group selection
circuit 128b is inactive. As a result, transistors Tr7_4 to Tr7_7
are turned on entirely to supply the inactive potential VPP to the
main word lines MWL4 to MWL7. Since the transistors Tr7 have a
larger capacity than the transistors Tr12 (i.e. forcibly setting
circuit), a force to fix the main word lines MWL to the inactive
potential VPP is strong. Therefore, by alternatively arranging the
main word lines MWL in the adjacent second group selection circuits
128a and 128b, it is made easier to suppress a voltage drop caused
by the aforementioned coupling.
[0055] As shown in FIG. 13, three inverters including the first
inverter 122 to the third inverter 120 are accommodated in one word
activation circuit 116. As shown in FIG. 14, since two inverters
that are the first inverter 122 and the second inverter 124 are
shared, the word activation circuits 116 are allowed to have a
simple structure which substantially includes only AND gate.
[0056] It is apparent that the present invention is not limited to
the above embodiments, but may be modified and changed without
departing from the scope and spirit of the invention.
* * * * *