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Noguchi; Hidekazu Patent Filings

Noguchi; Hidekazu

Patent Applications and Registrations

Patent applications and USPTO patent grants for Noguchi; Hidekazu.The latest application filed is for "apparatuses and methods for generating refresh addresses".

Company Profile
0.21.25
  • Noguchi; Hidekazu - Tokyo JP
  • Noguchi; Hidekazu - Shinjuku-ku JP
  • Noguchi, Hidekazu - Saitama JP
*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.
Patent Activity
PatentDate
Apparatuses and methods of power supply control for threshold voltage compensated sense amplifiers
Grant 11,450,378 - Sato , et al. September 20, 2
2022-09-20
Average interval generator
Grant 11,356,081 - Noguchi June 7, 2
2022-06-07
Apparatuses And Methods For Generating Refresh Addresses
App 20220148646 - NOGUCHI; HIDEKAZU
2022-05-12
Apparatuses and methods for calculating row hammer refresh addresses in a semiconductor device
Grant 11,322,192 - Morohashi , et al. May 3, 2
2022-05-03
Apparatuses And Methods Of Power Supply Control For Threshold Voltage Compensated Sense Amplifiers
App 20220101910 - Sato; Toshiyuki ;   et al.
2022-03-31
Apparatuses And Methods For Controlling Refresh Operations
App 20220093165 - MITSUBORI; SHINGO ;   et al.
2022-03-24
Apparatuses and methods for DRAM wordline control with reverse temperature coefficient delay
Grant 11,257,529 - Joo , et al. February 22, 2
2022-02-22
Apparatuses and methods for controlling refresh timing
Grant 11,222,686 - Noguchi January 11, 2
2022-01-11
Apparatuses And Methods For Distributed Targeted Refresh Operations
App 20210166752 - Noguchi; Hidekazu
2021-06-03
Apparatuses and methods for distributed targeted refresh operations
Grant 10,957,377 - Noguchi March 23, 2
2021-03-23
Average Interval Generator
App 20210075408 - Noguchi; Hidekazu
2021-03-11
Apparatuses And Methods For Dram Wordline Control With Reverse Temperature Coefficient Delay
App 20210074341 - Joo; Yangsung ;   et al.
2021-03-11
Apparatuses and methods for DRAM wordline control with reverse temperature coefficient delay
Grant 10,878,862 - Joo , et al. December 29, 2
2020-12-29
Apparatuses And Methods For Distributed Targeted Refresh Operations
App 20200211632 - Noguchi; Hidekazu
2020-07-02
Apparatuses And Methods For Calculating Row Hammer Refresh Addresses In A Semiconductor Device
App 20200202921 - Morohashi; Masaru ;   et al.
2020-06-25
Apparatuses And Methods For Dram Wordline Control With Reverse Temperature Coefficient Delay
App 20200090713 - Joo; Yangsung ;   et al.
2020-03-19
Apparatuses and methods for calculating row hammer refresh addresses in a semiconductor device
Grant 10,580,475 - Morohashi , et al.
2020-03-03
Apparatuses And Methods For Calculating Row Hammer Refresh Addresses In A Semiconductor Device
App 20190228815 - Morohashi; Masaru ;   et al.
2019-07-25
Semiconductor Device Having Plural Selection Lines
App 20150269988 - Noguchi; Hidekazu
2015-09-24
Semiconductor device
Grant 9,076,503 - Noguchi July 7, 2
2015-07-07
Semiconductor device having plural selection lines
Grant 9,053,759 - Noguchi June 9, 2
2015-06-09
Semiconductor device having redundant select line to replace regular select line
Grant 8,726,106 - Noguchi May 13, 2
2014-05-13
Semiconductor Device
App 20130134788 - NOGUCHI; Hidekazu
2013-05-30
Semiconductor Device Having Plural Selection Lines
App 20130135947 - Noguchi; Hidekazu
2013-05-30
Semiconductor Device Having Redundant Select Line To Replace Regular Select Line
App 20130007510 - NOGUCHI; Hidekazu
2013-01-03
Semiconductor Device
App 20120320699 - NOGUCHI; Hidekazu
2012-12-20
Semiconductor Device Having Redundant Select Line To Replace Regular Select Line
App 20120307578 - NOGUCHI; Hidekazu
2012-12-06
Semiconductor device, method of fabricating semiconductor device, and semiconductor device layout method
Grant 8,125,248 - Noguchi February 28, 2
2012-02-28
Semiconductor Device, Method Of Fabricating Semiconductor Device, And Semiconductor Device Layout Method
App 20110057685 - Noguchi; Hidekazu
2011-03-10
Device for eliminating clock signal noise in a semiconductor integrated circuit
Grant 7,295,055 - Noguchi , et al. November 13, 2
2007-11-13
Level shift circuit
Grant 7,161,405 - Noguchi January 9, 2
2007-01-09
Semiconductor integrated circuit
App 20060119716 - Noguchi; Hidekazu ;   et al.
2006-06-08
Semiconductor integrated circuit
Grant 7,005,931 - Noguchi February 28, 2
2006-02-28
Semiconductor memory device
Grant 6,977,851 - Noguchi December 20, 2
2005-12-20
Semiconductor memory device
App 20050047225 - Noguchi, Hidekazu
2005-03-03
Level shift circuit
App 20050007175 - Noguchi, Hidekazu
2005-01-13
Semiconductor integrated circuit
App 20040257164 - Noguchi, Hidekazu
2004-12-23
Semiconductor memory device having shortened testing time
Grant 6,751,128 - Kuroki , et al. June 15, 2
2004-06-15
Semiconductor memory device with redundant memory cells
Grant 6,738,299 - Noguchi May 18, 2
2004-05-18
Semiconductor memory device with redundant memory cells
App 20030169628 - Noguchi, Hidekazu
2003-09-11
Semiconductor memory device
App 20020182800 - Kuroki, Koji ;   et al.
2002-12-05
Semiconductor memory circuit including a data output circuit
App 20010048633 - Noguchi, Hidekazu
2001-12-06
Power circuit and clock signal detection circuit
Grant 6,218,893 - Noguchi April 17, 2
2001-04-17

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