U.S. patent application number 14/259432 was filed with the patent office on 2015-09-17 for method for fabricating equal height metal pillars of different diameters.
This patent application is currently assigned to LSI Corporation. The applicant listed for this patent is LSI Corporation. Invention is credited to Steven D. Cate, John W. Osenbach.
Application Number | 20150262949 14/259432 |
Document ID | / |
Family ID | 54069710 |
Filed Date | 2015-09-17 |
United States Patent
Application |
20150262949 |
Kind Code |
A1 |
Osenbach; John W. ; et
al. |
September 17, 2015 |
Method for Fabricating Equal Height Metal Pillars of Different
Diameters
Abstract
A process to form metal pillars on a flip-chip device. The
pillars, along with a layer of solder, will be used to bond die
pads on the device to respective substrate pads on a substrate. A
photoresist is deposited over the device and first openings in the
photoresist are formed. Metal layers are formed by electroplating
metal into the first openings for a first time period. Then the
photoresist is patterned to form second openings having a smaller
diameter than the first openings. Narrow pillars are formed by
electroplating metal into the second openings for a second time
period during which the metal is also added to the metal layers in
the first openings to form wide pillars having substantially the
same height as the narrow pillars. The photoresist is then removed
along with conductive layers on the device used as part of the
plating process.
Inventors: |
Osenbach; John W.;
(Kutztown, PA) ; Cate; Steven D.; (Los Altos,
CA) |
|
Applicant: |
Name |
City |
State |
Country |
Type |
LSI Corporation |
San Jose |
CA |
US |
|
|
Assignee: |
LSI Corporation
San Jose
CA
|
Family ID: |
54069710 |
Appl. No.: |
14/259432 |
Filed: |
April 23, 2014 |
Related U.S. Patent Documents
|
|
|
|
|
|
Application
Number |
Filing Date |
Patent Number |
|
|
61952963 |
Mar 14, 2014 |
|
|
|
Current U.S.
Class: |
438/113 |
Current CPC
Class: |
H01L 24/14 20130101;
H01L 2224/814 20130101; H01L 2224/94 20130101; H01L 24/13 20130101;
H01L 2224/03912 20130101; H01L 2224/05082 20130101; H01L 2224/11462
20130101; H01L 2224/13005 20130101; H01L 2224/0345 20130101; H01L
2224/05166 20130101; H01L 2224/05583 20130101; H01L 2224/94
20130101; H01L 2924/20756 20130101; H01L 2224/05124 20130101; H01L
2224/11903 20130101; H01L 2224/1403 20130101; H01L 2224/05147
20130101; H01L 2924/20752 20130101; H01L 24/03 20130101; H01L
2224/0603 20130101; H01L 2224/81191 20130101; H01L 2924/20759
20130101; H01L 2224/05147 20130101; H01L 2224/131 20130101; H01L
24/81 20130101; H01L 2224/11622 20130101; H01L 2224/13007 20130101;
H01L 2224/13023 20130101; H01L 2224/1147 20130101; H01L 2224/814
20130101; H01L 2924/01029 20130101; H01L 2224/0345 20130101; H01L
2224/05124 20130101; H01L 2224/05647 20130101; H01L 24/17 20130101;
H01L 2224/118 20130101; H01L 2924/20753 20130101; H01L 2224/05023
20130101; H01L 2224/05568 20130101; H01L 2924/20758 20130101; H01L
24/11 20130101; H01L 21/565 20130101; H01L 2224/05166 20130101;
H01L 2224/16237 20130101; H01L 2224/81447 20130101; H01L 2924/20755
20130101; H01L 2924/2076 20130101; H01L 21/563 20130101; H01L
2924/37 20130101; H01L 2224/13005 20130101; H01L 2224/13147
20130101; H01L 21/78 20130101; H01L 24/05 20130101; H01L 24/06
20130101; H01L 2224/11906 20130101; H01L 2224/13147 20130101; H01L
2224/16113 20130101; H01L 2224/16225 20130101; H01L 2224/131
20130101; H01L 2924/20754 20130101; H01L 21/00 20130101; H01L
2224/05647 20130101; H01L 2924/01022 20130101; H01L 2224/13082
20130101; H01L 2924/20757 20130101; H01L 2224/81447 20130101; H01L
2224/03 20130101; H01L 2924/00014 20130101; H01L 2924/00014
20130101; H01L 2924/00014 20130101; H01L 2924/00014 20130101; H01L
2924/00014 20130101; H01L 2924/00014 20130101; H01L 2924/014
20130101; H01L 2924/00014 20130101; H01L 2924/01074 20130101; H01L
2924/206 20130101; H01L 2924/014 20130101; H01L 2224/05166
20130101 |
International
Class: |
H01L 23/00 20060101
H01L023/00 |
Claims
1. A method comprising the steps of: A) providing, a wafer having a
plurality of flip-chip devices, each flip-chip device having a
plurality of die pads thereon; B) depositing a first layer of
photoresist on the wafer; C) patterning the first layer of
photoresist to form a first plurality of openings therein, each of
the first openings having a first diameter and exposing a first set
of die pads; D) plating metal into the first openings to form a
first metal pillar in each of the first openings for a first time
period; E) patterning the first layer of photoresist to form a
second plurality of openings therein, each of the second openings
having a second diameter and exposing a second set of die pads; and
F) plating metal into the first and second openings for a second
time period to add to each of the metal pillars in the first
openings and form a metal pillar in each of the second openings;
wherein the first diameter is greater than the second diameter, the
first set of die pads is different from the second set of die pads,
and the first and second time periods and plating conditions are
chosen such that, after step F) each of the pillars in the second
openings has substantially the same height as a pillars in each of
the first openings.
2. The method of claim 1 wherein the plated metal is copper.
3. The method of claim 1 further comprising the steps of: G)
plating, after step F), solder into the first and second openings
to form a solder layer in each of the openings and on exposed ends
of the metal pillars; H) depositing a second layer of photoresist
to at least cover the second openings in the first photoresist
layer; and I) plating solder into the first openings to form a
second solder layer in each of the first openings and on the first
solder layer therein.
4. The method of claim 3 wherein each of the metal pillars of the
first and second plurality of metal pillars has a height above a
die pad and each of the solder layers has a height above its
respective metal pillar, and a ratio of the height of a metal
pillar to the height of its respective solder layer is 1:10 to
100:1.
5. The method of claim 4 wherein the height of each of the metal
pillars is 20 to 70 microns, the height of each solder layers is 10
to 60 microns, and the first and second diameters range from 20 to
80 microns.
6. The method of claim 4 wherein a sum of the height of each of the
metal pillars and its respective solder layer is between 5 microns
and 130 microns and the first and second diameters range from
substantially 5 to 150 microns.
7. The method of claim 4 wherein the first diameter is less than 80
microns and the second diameter is greater than 80 microns, and a
sum of the height of each metal pillar and its respective solder
layer is 80 microns or less.
8. The method of claim 3 wherein in step H) comprises the steps of:
depositing a second layer of photoresist covering the first
photoresist layer; patterning the second photoresist layer form a
plurality of openings therein, the openings having a diameter
substantially equal to the first diameter and exposing the solder
layers in the first openings of the first photoresist layer.
9. The method of claim 1 further comprising the step of:
depositing, before step B), a conductive layer over the plurality
of die pads; wherein in steps D) and G) the plating is by
electroplating using the conductive layer as a electroplating
electrode.
10. The method of claim 9 wherein the conductive layer comprises a
barrier layer and a strike layer deposited over the barrier
layer.
11. The method of claim 10 wherein the barrier comprises titanium
and the strike layer comprises copper.
12. The method of claim 1 further comprising the step of removing,
after step F), the first photoresist layer.
13. A method of claim 12 further comprising the steps of:
singulating the wafer to separate the plurality of a flip-chip
devices into individual devices; selecting one of the singulated
devices; providing a substrate having a plurality of substrate
pads, each of the plurality of substrate pads positioned on the
substrate to align with a respective one of the metal pillars of
the first and second plurality of metal pillars on the selected
flip-chip device; bringing the selected flip-chip device in
proximity to the substrate such that all the plurality of substrate
pads positioned on the substrate are aligned with a respective one
of the metal pillars on the selected flip-chip device; and bonding
the metal pillars to their respective substrate pads using solder
to form a package.
14. The method of claim 13 wherein the flip-chip device comprises a
material selected from the group consisting of silicon, gallium
arsenide, indium phosphide, and a combination thereof and wherein
the substrate is selected from the group consisting of glass-epoxy,
polytetrafluoroethylene, ceramic, silicon, glass, and a combination
thereof.
15. The method of claim 13 further comprising the steps of:
forming, after the bonding step, an underfill layer between the
flip-chip device and the substrate; and forming, after forming the
underfill layer, an overmold on the flip-chip device and the
substrate.
16. A method comprising the steps of: A) providing a wafer having a
plurality of flip-chip devices, each flip-chip device having a
plurality of die pads thereon; B) depositing a first layer of
photoresist on the wafer; C) patterning the first layer of
photoresist to form a first plurality of openings therein, each of
the first openings having a first diameter and exposing a first set
of die pads; D) plating metal into the first plurality of openings
to form a first metal pillar in each of the first plurality of
openings, each of the first metal pillars having substantially the
first diameter and a first height above its respective die pad; E)
patterning the first layer of photoresist to form a second
plurality of openings therein, each of the second openings having a
second diameter and exposing a second set of die pads; and F)
plating metal into the first and second openings and onto the first
metal pillars and exposed second set of die pads, respectively, to
form a second metal pillar in each of the first openings and a
metal pillar in each of the second openings, each of the metal
pillars in the second openings having substantially the second
diameter and a height above its respective die pad, and each of the
second pillars in the first plurality of openings having
substantially the first diameter and a height above its respective
first metal pillar; wherein the first diameter is greater than the
second diameter, a sum of the first and second pillar heights in
each of the first openings is substantially equal to the height of
the metal pillar in each of the second openings, and the first set
of die pads is different from the second set of die pads.
17. The method of claim 16 wherein each of the copper pillars of
the first and second plurality of copper pillars has a height above
a die pad and each of the solder layers has a height above its
respective copper pillar, and the height of each of the copper
pillars is 20 to 70 microns, the height of each solder layers is 10
to 60 microns, a sum of the height of each copper pillar and its
respective solder layer is 80 microns or less, and the first
diameter is less than 80 microns and the second diameter is greater
than 80 microns.
18. The method of claim 16 wherein each of the copper pillars of
the first and second plurality of copper pillars has a height above
a die pad and each of the solder layers has a height above its
respective copper pillar, and a sum of the height of each of the
copper pillars and its respective solder layer is between 5 microns
and 130 microns and the first and second diameters range from
substantially 5 to 150 microns.
19. The method of claim 16 wherein the barrier comprises titanium
and the strike layer comprises copper.
20. The method of claim 15 further comprising the steps of:
forming, after the bonding step, an underfill layer between the
flip-chip device and the substrate; and forming, after forming the
underfill layer, an overmold on the flip-chip device and the
substrate.
Description
CROSS-REFERENCE TO RELATED APPLICATIONS
[0001] This application claims the benefit of the filing date of
U.S. provisional patent application No. 61/952,963 filed 14 Mar.
2014 as attorney docket no. L14-0124US1, the teachings of which are
incorporated herein by reference, and the subject matter of this
application is related to U.S. patent application Ser. No. ______,
filed concurrently herewith as attorney docket no. L14-0124US1,
titled "Method for Fabricating Equal Height Metal Pillars of
Different Diameters", the teachings of which are incorporated
herein by reference.
BACKGROUND OF THE INVENTION
[0002] 1. Field of the invention
[0003] The present invention relates to semiconductor packaging
technology generally and, more specifically, to a process for
forming copper pillars, and a solder layer thereon, on
semiconductor devices for flip-chip bonding to it substrate.
[0004] 2. Description of the Related Art
[0005] Copper pillars are a widely used technique for electrically
interconnecting a flip-chip semiconductor device or "chip" to
conductors on an organic-based substrate, such as a thin (less than
one millimeter thick) glass-epoxy board, because copper pillar
interconnects have superior geometric control, higher density, and
electrical performance relative to solder bump interconnects. The
copper pillars on the device's die pads, formed by selectively
plating copper onto the die pads, connect to the substrate's
substrate pads by using a solder layer between each pillar and the
respective substrate pad to join the copper pillars to the
substrate pads. Plating is usually used to form the solder layer
onto the ends of the copper pillars.
[0006] To bond a flip-chip device to a substrate, the device and
substrate are brought together and heated until the solder on the
ends of the copper pillars melts and wets the substrate pads on the
substrate, each pillar and solder combination forming a "joint".
Then the device-substrate combination is cooled down and the solder
solidifies to bond the device to the substrate, forming a bonded
device-substrate structure or "package".
[0007] In order to insure all substrate-to-die joints are formed
during bonding, all of the copper pillars and solder layers on the
die before heating are to have the same nominal height. In addition
it is generally desirable for all of the joints to have
substantially the same diameter. However, having joints with the
same diameter might not be desirable in all instances. For example,
for carrying a large number of high-speed signals between the chip
and the substrate, it might be desirable to use thinner than
"normal" diameter joints spaced to provide a high density of signal
paths while at the same time providing a desired transmission line
characteristic impedance between the joints, e.g., 50 or
100.OMEGA.. In other instances where a large current is to be
carried by a joint, e.g., a power supply connection,
electromigration might with time cause failure of a joint with a
normal diameter. To address the high current problem, multiple
joints with a normal diameter are placed in parallel or one or more
of the joints are formed with a larger or wider diameter than a
"normal" joint so that the current density in each joint is less
than a maximum amount that would otherwise cause the joint to fail
from electromigration. However, using a conventional plating
process to make joints with different diameters with substantially
uniform height has been problematic. For a given electrochemical
plating process and plating bath solution, the mass or volume per
unit of time of the plated material is essentially a constant
except for any local variations in the bath current density or
concentration of all of the plating species in a particular plating
bath. As a result, using a conventional electroplating process to
form different diameter joints will result in a device with smaller
diameter joints that are taller than adjacent larger diameter
joints. The uneven joint height might not allow the shorter joints
on the device to be completely attached, if at all, to their
respective substrate pads, while all of the taller joints will be
completely attached, thus causing the completed package to be
inoperable or prone to high rates of failure in the field. Further,
any warpage of the substrate might exacerbate this situation,
possibly increasing the number of partial or incomplete joints.
SUMMARY OF THE INVENTION
[0008] This Summary is provided to introduce a selection of
concepts in a simplified form that are further described below in
the Detailed Description. This Summary is not intended to identify
key features or essential features of the claimed subject matter,
nor is it intended to be used to limit the scope of the claimed
subject matter.
[0009] Described embodiments include method comprising the steps of
providing a wafer having a plurality of flip-chip devices, each
flip-chip device having a plurality of die pads thereon; depositing
a first layer of photoresist on the wafer; patterning the first
layer of photoresist to form a first plurality of openings therein,
each of the first openings having a first diameter and exposing a
first set of die pads; plating metal into the first openings to
form a first metal pillar in each of the first openings for a first
time period; patterning the first layer of photoresist to form a
second plurality of openings therein, each of the second openings
having a second diameter and exposing a second set of die pads; and
plating, metal into the first and second openings for a second time
period to add to each of the metal pillars in the first openings
and form a metal pillar in each of the second openings. The first
diameter is greater than the second diameter, and the first set of
die pads is different from the second set of die pads. The first
and second time periods and plating conditions are chosen such
that, after plating metal into the first and second openings for a
second time period, each of the pillars in the second openings has
substantially the same height as a pillars in each of the first
openings.
BRIEF DESCRIPTION OF THE DRAWINGS
[0010] Other embodiments of the present invention will become more
fully apparent from the following detailed description, the
appended claims, and the accompanying drawings in which like
reference numerals identify similar or identical elements. The
drawings are not to scale.
[0011] FIG. 1 is a cross-section of a flip-chip device bonded to a
substrate using copper pillars and solder of different diameters in
one embodiment of the invention;
[0012] FIG. 2 is a cross-section of one pillar and solder layer of
FIG. 1 prior to bonding;
[0013] FIG. 3 a flowchart illustrating an exemplary process for
forming metal pillars of different diameters and uniform height on
a flip-chip device and then bonding the device to a substrate
according to one embodiment of the invention; and
[0014] FIGS. 4-9 are diagrams illustrating the various steps in the
process described in connection with FIG. 3.
DETAILED DESCRIPTION
[0015] Reference herein to "one embodiment" or "an embodiment"
means that a particular feature, structure, or characteristic
described in connection with the embodiment can be included in at
least one embodiment of the invention. The appearances of the
phrase "in one embodiment" in various places in the specification
are not necessarily all referring to the same embodiment, nor are
separate or alternative embodiments necessarily mutually exclusive
of other embodiments. The same applies to the term
"implementation".
[0016] As used in this application, the word "exemplary" is used
herein to mean serving as an example, instance, or illustration.
Any aspect or design described herein as "exemplary" is not
necessarily to be construed as preferred or advantageous over other
aspects or designs. Rather, use of the word exemplary is intended
to present concepts in a concrete fashion.
[0017] The term "or" should be interpreted as inclusive unless
stated otherwise. Further, elements in a figure having subscripted
reference numbers, e.g., 100.sub.1, 100.sub.2, . . . 100.sub.K, or
100.sub.A, 100.sub.B, etc. might be collectively referred to herein
using a single reference number, e,g 100.
[0018] It should be understood that the steps of the exemplary
methods set forth herein are not necessarily required to be
performed in the order described, and the order of the steps of
such methods should be understood to be merely exemplary. Likewise,
additional steps might be included in such methods, and certain
steps might be omitted or combined, in methods consistent with
various embodiments of the present invention.
[0019] Also for purposes of this description, the terms "couple",
"coupling", "coupled", "connect", "connecting", or "connected"
refer to any manner known in the art or later developed in which
energy or a signal is allowed to be transferred between two or more
elements, and the interposition of one or more additional elements
is contemplated, although not required. Conversely, the terms
"directly coupled", "directly connected", etc., imply the absence
of such additional elements.
[0020] The present invention will be described herein in the
context of illustrative embodiments of a process to form metal
pillars on a flip-chip device that will be bonded to a substrate by
joining die pads on the flip-chip device to substrate pads on the
substrate using joints of metallic pillars, such as copper pillars,
and solder. The pillars and the solder on them are formed by
electroplating a metal onto the die pads. According to Faraday's
Law, the total amount of metal deposited on a workpiece by
electroplating is proportional to the current passed through the
workpiece in an electroplating bath the device is immersed in, and
the amount of time the current is applied, i.e., the amount of
charge (in coulombs) applied to the workpiece. However, the rate at
which each pillar is formed is inversely proportional to the
surface area of the pillar. Thus, the wider pillars grow more
slowly than narrow pillars. To form narrow and wide pillars having
approximately the same height, the wide pillars are first partially
formed before forming the narrow pillars by using a photoresist
layer with two different diameter openings. First, a photoresist
layer is deposited on a device and the photoresist is patterned to
form a first plurality of openings therein, each of the first
openings having a first diameter and exposing a first set of die
pads on the device. Next, pillar metal (e.g., copper) is plated
into the first openings to form a first metal pillar in each of the
first openings for a first time period. Then the photoresist is
patterned to form a second plurality of openings therein, each of
the second openings having a diameter smaller than the first
diameter and exposing a second set of die pads. Then pillar metal
is plated into the first and second openings for a second time
period to add metal to each of the metal pillars in the first
openings and form a metal pillar in each of the second openings.
The first and second time periods and plating conditions are chosen
such that, after plating metal into the first and second openings
for the second time period, each of the pillars in the second
openings has substantially the same height as the pillars in each
of the first openings. As described below, the solder layers might
also be formed by plating solder into the openings and in
conjunction with the formation of the pillars.
[0021] FIG. 1 is a cross-section of a flip-chip device 102 bonded
to a substrate 104 to form a flip-chip package 100 in accordance
with an embodiment of the invention. Die pads (not shown) on the
device 102 are bonded to substrate pads 114 on the substrate 104
using multiple conductors or joints 106. The device 102 might be
formed from silicon, gallium arsenide, indium phosphide, or another
semiconductor material suitable for the desired function of the
device 102. The substrate 104 might be formed from a glass-epoxy
(commonly known as FR-4), polytetrafluoroethylene (PTFE),
polyimide, ceramics, silicon, glass, another insulating material
suitable as a substrate, or a combination of these materials.
Typically, the thickness of the substrate 104 is less than two
millimeters and might be as thin as 50 microns (.mu.m). The lateral
dimensions of the substrate 104 are typically larger than that of
the device 102.
[0022] In this example, the joints 106 are arranged with narrow
joints 106.sub.N on the right side of the package 100 and wide
joints 106.sub.W on the left side of the package 100. Generally,
power and ground are supplied to the device 100 using the wide
joints 106.sub.W on the left side of the device 102 and high-speed
signals are carded by the narrow joints 106.sub.N on the right side
of the device 102. It is understood that in various instances, the
wide joints carry the high-speed signals and the narrow joints
supply power and ground to the device 102. Further, the positions
of the wide and narrow joints are greatly simplified for
illustrative purposes; typically hundreds of joints are present and
power/ground interconnections are generally made in the center of
the device 102 while high-speed signals are generally carried by
joints near the periphery of the device 102.
[0023] Each joint is formed from a metallic pillar 108, such as
copper, and a layer of solder 110. For the proper bonding of all
the joints between the device 102 and substrate 104, the height of
all of the pillars 108 and solder layers 110 prior to bonding
should be of uniform height, otherwise when the device 102 is
bonded to substrate 104, a gap between some of the solder layers
110 and the respective substrate pad 114 might be so large that
during reflow when the device and substrate are heated sufficiently
for the solder to melt, balling-up by the solder on the end of the
pillar (caused by surface tension of the molten solder) is
insufficient to bridge the gap so that the solder does not wet the
substrate pad and no electrical/mechanical joint is made.
[0024] Referring to FIG. 2, one of the joints 106 in FIG. 1 is
shown as the joint appears prior to bonding the device 102 to the
substrate 104. As discussed above, a joint 106 is formed from a
copper pillar 108 and a layer of solder 110. The copper pillar is
formed on a die pad 212 that has, in this embodiment, three layers.
A contact layer 214 is typically in or on the surface of the device
102, is made of copper or aluminum, and connects to circuitry (not
shown) within the device 102. Over the contact layer 214 is a layer
216 of titanium or titanium-tungsten that operates as a
barrier/glue layer. Next, a strike layer 218, typically of the same
metal as used to form the pillar 108 (e.g., copper). As will be
explained in more detail below, the layers 216 and 218 are
sputtered onto the device 102 and are typically less than 100 nm
thick. Not shown are one or more conventional passivation layers
(e.g., silicon nitride or alternating layers of silicon nitride and
silicon dioxide) on the surface of the device 102 that has openings
therein to expose the layer 214 and serves to protect the device
from contaminants and physical damage.
[0025] On substrate 104 is a respective one of the substrate pads
114, also typically made of copper, shown aligned with the die pad
212. The substrate copper pad might be coated with another metal
such as tin, silver, a nickel-gold eutectic, or solder.
[0026] The copper pillar 108 has a height of H.sub.P and the solder
layer 110 has a height of H.sub.S (before melting), and both have
an approximate diameter D. The height of the joint is
H.sub.P+H.sub.S so that the total height of the pillar and solder
is H. In various embodiments, the height of the joint prior to
melting ranges from 5 .mu.m to 130 .mu.m. In one embodiment, the
copper pillars have a diameter ranging from approximately 20 .mu.m
to approximately 80 .mu.m, a height H.sub.P of 20-70 .mu.m, and the
solder layers, prior to melting, have a height H.sub.S of 10-60
.mu.m so that the total height is approximately 80 .mu.m and might
range from 5 .mu.m to 130 .mu.m. However, it is understood that the
ratio of the height of the copper pillar to the height of the
solder layer before melting can range from 1:10 to 100:1 and the
pillar diameter can range from 5-150 .mu.m.
[0027] Assuming a possible pillar diameter accuracy of +/-1 .mu.m
for openings less than 10 .mu.m, +/-2 .mu.m for openings less than
30 .mu.m, +/-5 for openings less than 50 .mu.m, and +/-7 .mu.m for
openings less than 100 .mu.m, and +/-8 .mu.m for openings less than
150 .mu.m, then for the following exemplary ranges in opening
diameters, it might be desirable to perform two separate pillar
plating steps in accordance with the disclosed embodiments when the
exemplary percentage difference between the narrow and wide
openings is at least that in the following table:
TABLE-US-00001 Minimum % diameter Both opening diameters two
separate plating steps <60 10 60 < dia. < 100 7 100 <
dia. < 150 5 indicates data missing or illegible when filed
[0028] However, it is understood that while the above percentage
differences and ranges in opening diameters are merely exemplary,
two separate plating steps might still be used were the percentage
difference between the narrow and wide openings is less than the
above-described amounts.
[0029] FIG. 3 is a flowchart illustrating an exemplary process 300
for forming the pillars 108 and the solder layers 110 onto device
102 according to one embodiment of the invention. Beginning with
step 302, a wafer containing multiple devices 102 is provided, each
device having contact layers 214 thereon. For simplicity and
because of the scale of a joint compared to that of a wafer, the
process 300 is described below in the context of a single flip-chip
device 102 but in practice the process steps are done at a wafer
level because a wafer (not shown) comprises multiple flips-chip
devices and all of the devices in the wafer are processed at the
same time. It is not until an individual device is attached to a
substrate (step 324) that the described steps are applied to a
device individually.
[0030] Next step 304, the barrier/glue layer 216 and the strike
layer 218 are deposited over the device 102. These two steps are
illustrated in FIG. 4. Here, a partial cross-sectional view of the
device 102 of FIG. 1 is shown but with just four contact layers
214, the two on the left being wider than the two on the right.
Over the contact layer 214 are two layers 216 and 218, shown here
for simplicity as one layer. As discussed above, these layers are
each about 100 nm thick and are sputtered, onto the device 102
although other techniques might be used to deposit the layers 216,
218, such as by evaporation. Because the barrier layer and the
strike layers are conductive, the combined layers 216, 218 also
serve as an electrode when the pillars and solder layer are later
deposited by electroplating. While the die pad 212 in FIG. 2 is
shown having three separate and laterally defined layers, for
purposes of describing the embodiment in FIGS. 4-9, a contact layer
214, along with the metal layers immediately above the contact
layer, are referred to herein as either a wide die pad 212.sub.W or
a narrow die pad 212.sub.N as illustrated in FIG. 4. The widths of
the contact layers 214 and die pads 212 are illustrative (e.g.,
wider pillars on wider die pads 212.sub.W and narrow pillars on
narrow die pads 212.sub.N) and all of the die pads might be the
same size or have different sizes. However, the size of a die pad
212 should be at least as wide as the pillar formed thereon.
[0031] Returning to FIG. 3, in step 306 a first photoresist layer
is deposited across the device 102 and is photolithigraphically
patterned using conventional techniques to form openings having a
wide diameter in the photoresist over the wider die pads. This is
shown in FIG. 5 where wide openings 502 are shown in photoresist
504 over the wide die pads 212.sub.W and the narrow die pads
212.sub.N remain covered by the photoresist 504. The width of the
later-formed pillars will be approximately equal to the width of
the wide openings 502. Part of the photoresist 504 is also removed
to expose the conductive layers 216, 218 and an electrode 506 is
shown contacting the conductive layers 216, 218 to provide to
current path needed for electroplating. This electrode is not
needed if the pillars and solder layer are formed using electroless
plating.
[0032] In step 308 of FIG. 3, the pillars 108.sub.W are formed by
plating metal onto the exposed portions of layer 216, 218 of the
die pads 212.sub.W. Generally, this is accomplished by submersing
the device 102 in a plating path (not shown) containing an aqueous
solution of the metal being plated, e.g., copper sulfate, copper
cyanide, nickel sulfate, etc. and electroplating the metal into the
openings and onto the exposed die pads by applying current to the
electrode 506 for a first time period that will result in the
deposition of a first layer 506 of pillar metal to a first height,
here H.sub.1, in wide openings 502 as shown in FIG. 5. Then the
device 102 is removed from the plating bath and cleaned.
[0033] Next, in step 310, the first photoresist is again patterned
but this time forming narrow openings in the first photoresist to
expose the narrow die pads while leaving the wide openings intact
and the metal layers in the wide openings exposed. Then, in step
312, the wafer is returned to the plating bath and the deposition
of the pillar metal into the wide and narrow openings occurs for a
second time period until the wide pillars formed in the wide
openings and narrow pillars formed in the narrow openings have
approximately the same height. Thus, the narrow pillars are formed
solely during the second plating step (step 312) while the wide
pillars are formed during both the first plating step (step 308)
and the second plating step. Because the metal being plated will be
deposited more quickly in the narrow openings than in the wide
openings, the first time period and the second time period are
chosen so that the narrow pillars will reach a second or desired
height at approximately the same time the wide pillars reach the
desired height during the second plating step. This is illustrated
in FIG. 6, where narrow openings 602 are formed, exposing narrow
die pads 212.sub.N. During the second plating step described above
(step 312), pillar metal is deposited in opening 502 on top of
metal layer 506 to form metal layer 606, layer 606 having a height
of H.sub.2, and into openings 602 to form the metal pillars
108.sub.N. After the second plating step 312, the combined height
of metal layers 506 and 606 will be approximately equal to the
height of the narrow pillar 108.sub.N, or
H.sub.1-H.sub.2.apprxeq.H.sub.P. Thus, the combined layers 506 and
606 form the pillars 108.sub.W.
[0034] As mentioned above, the rate at which a pillar is formed
(e.g., in microns per minute) is inversely proportional to the
surface area of the pillar. To determine the first and second time
periods for steps 308 and 312, respectively, the second time period
(t2) is chosen so that the narrow pillars have a second or desired
height after the second plating step 312. Assuming that the plating
conditions (e.g., plating current) are substantially the same
during the first and second plating steps, the first time period,
t1, might be calculated as a function of the pillar areas and the
second time period:
t1.apprxeq.t2(A.sub.W/A.sub.S-1);
[0035] where t1 and t2 are the first and second time periods,
respectively, A.sub.W is the area of each of the wide pillars or
that of the wide openings, and A.sub.N is the area of the narrow
pillars or that of the narrow openings.
[0036] It is understood that if the plating conditions are
different during the first plating step 308 from that in the second
plating step 312, the first time period might be adjusted
accordingly. Further, more than two different diameter metal
pillars might be made by the above process where the number of
plating steps is the same as the number of different diameter metal
pillars to be formed and the plating times for the different
plating steps are determined substantially in accordance with the
above equation.
[0037] After the narrow and wide pillars 108.sub.W, 108.sub.N are
formed, then optional solder layers might be formed on the ends of
the pillars. Similar the above-described process to form the
pillars, in step 314 the wafer is placed in a solder plating bath
for a third time period and solder is plated into the narrow and
the wide openings in the first photoresist until the solder layer
in the narrow openings reaches a desired height above the narrow
pillars and then the wafer is removed from the plating bath. As
illustrated in FIG. 7, the wafer having device 102 thereon is
placed in another plating bath (not shown) containing the solder to
be plated, e.g., stannous tin and lead sulfate, stannous tin and
silver nitrate, etc., to deposit the solder layers 706 in the wide
openings 502 and the solder layers 110.sub.N in the narrow openings
602. The height of the pillars 108.sub.N and 108.sub.W are shown as
H.sub.P, the height of the solder layer 110.sub.N on pillars
108.sub.N is shown as H.sub.S, and the total height of the pillar
and solder layer is height H, the same as that shown in FIG. 2. For
convenience, the top of the photoresist 504 is shown coincident
with the total height H of the pillar and solder layer but the
height H might be below the top of the photoresist 504.
[0038] As shown in FIG. 7, the solder layer 706 will be
significantly shorter than the solder layer 110.sub.N after plating
step 314. To make the solder layer in the wider openings 502
thicker without impacting the solder layers in the narrow openings
602, in step 316 a second photoresist layer is deposited over the
first photoresist layer, the second photoresist layer covering at
least the solder layers in the narrow openings. Alternatively, the
second photoresist layer covers the entire first photoresist and
openings are formed in the second photoresist layer to expose the
solder layers in the wide openings of the first photoresist layer.
Preferably, the diameter of the openings in the second photoresist
layer is substantially the same as the diameter of the wide
openings in the first photoresist layer but it is understood that
the diameters might be different. Then in step 320 the wafer is
placed back in the solder plating bath for a fourth time period to
complete the plating of the solder layers in the wide openings to
the desired height. The preceding two steps are illustrated in FIG.
8. A second photoresist layer 804 overlays the first photoresist
layer 504, covering the narrow solder layers 110.sub.N. Openings
802 are formed in the photoresist layer 804 to expose the solder
layers 606 using, for example, a conventional plasma etch or a
conventional liquid chemical etch that selectively removes the
patterned photoresist 804. The diameter of openings 802 is
approximately the same diameter as the openings 502 (FIG. 7) so
that the diameter of openings 502 are not significantly changed
when the openings 802 are formed since the photoresist layer 804
will extend into the opening 502 when deposited. Then, the wafer
with device 102 thereon is placed back in the solder plating bath
(not shown) for the fourth time period to form the solder layer
806. The result is the combined heights of the solder layers 606
and 806 are approximately equal to the height H.sub.S of the solder
layer 110.sub.N. Thus, layers 606 and 806 together are referred to
as solder layer 110.sub.W.
[0039] Like the above calculation to determine the first time
period, the third time period (t3) is chosen so that the narrow
solder layers 110.sub.N have a desired height H.sub.S after the
first solder plating step 314. Then, assuming the plating
conditions (e.g., plating current) are substantially the same
during the first and second solder plating steps, the fourth time
period, t4, is determined
t4.apprxeq.t3(A.sub.W/A.sub.S-1);
[0040] where t3 and t4 are the third and fourth time periods,
respectively, A.sub.W is the area of each of the wide pillars or
that of the wide openings, and A.sub.N is the area of the narrow
pillars or that of the narrow openings.
[0041] Alternatively and assuming the plating conditions (e.g.,
plating current) are substantially the same during the first and
second solder plating steps, t4 can be calculated based on the
amount of time T needed to plate the solder layers in the wide
openings to the same height as the solder layers in the narrow
openings plated in time period t3. Thus t4 is approximately T-t3.
However, it is understood that if the plating conditions are
different during the first solder plating step 314 from that in the
second solder plating step 320, the fourth time period might be
adjusted accordingly.
[0042] As stated above, the height of the pillars and the solder
layer is proportional to the plating current and time used to form
them. Knowing the diameter of the opening 502 allows the relatively
precise control of the height of the pillars and solder layer
during formation with an accuracy of approximately 10% or
better.
[0043] Next, in step 322 the photoresist layers 504, 704 are
removed by ashing using an oxygen plasma or by dipping the device
102 into a chemical stripping bath. Then the conductive layer 216,
218 exposed by the removed photoresist is removed in step 324 by
plasma etching or by wet etching. The result is shown in FIG. 9
where two sets of joints are shown, a two wide joints 106.sub.W and
two narrow joints 106.sub.N, each having substantially the same
height above the device 102.
[0044] In step 326, the wafer (not shown) is singulated into
multiple devices 102. Then in step 328, each flip-chip device is
bonded to a substrate using a conventional flip-chip bonding
technique to form the package 100 shown in FIG. 1. Briefly, the
package 100 is formed by bringing the flip-chip device 102 into
proximity to the substrate such that the substrate pads 114 are
aligned with respective metal pillars 108 on the flip-chip device.
Then the metal pillars are then bonded to their respective
substrate pads by melting the solder layers 110 so that the solder
wets both the pillars and the substrate pads and then the device
and substrate are cooled to solidify the solder.
[0045] Next, in step 330, the final steps to complete the packaging
of the bonded device and substrate are done, such as forming an
underfill layer between the device and the substrate, adding a heat
spreader lid, forming an overmold of epoxy to the device and
substrate for environmental protection, testing, package marking,
etc.
[0046] In an alternative embodiment, instead of applying the solder
to the ends of the copper pillars, a layer of solder is deposited
on each of the substrate pads 114 by using a patterned solder mask
(not shown) on the substrate 104 with the substrate pads exposed
and the solder plated onto the exposed pads, using either
conventional electroplating, or electroless plating. In this
example, the solder layers 110 are not formed and steps 314 through
320 are not performed.
[0047] While the embodiments described above entail the formation
of wide pillars before narrow pillars, three or more different
pillar widths might be formed on a device using the concepts
described above.
[0048] Although the elements in the following method claims are
recited in a particular sequence with corresponding labeling,
unless the claim recitations otherwise imply a particular sequence
for implementing some or all of those elements, those elements are
not necessarily intended to be limited to being implemented in that
particular sequence.
[0049] It is understood that various changes in the details,
materials, and arrangements of the parts which have been described
and illustrated in order to explain the nature of this invention
might be made by those skilled in the art without departing from
the scope of the invention as expressed in the following
claims.
* * * * *