U.S. patent application number 14/677503 was filed with the patent office on 2015-07-30 for ultrathin body fully depleted silicon-on-insulator integrated circuits and methods for fabricating same.
The applicant listed for this patent is GLOBALFOUNDRIES, Inc.. Invention is credited to Stefan Flachowsky, Ralf Illgen.
Application Number | 20150214121 14/677503 |
Document ID | / |
Family ID | 49773702 |
Filed Date | 2015-07-30 |
United States Patent
Application |
20150214121 |
Kind Code |
A1 |
Illgen; Ralf ; et
al. |
July 30, 2015 |
ULTRATHIN BODY FULLY DEPLETED SILICON-ON-INSULATOR INTEGRATED
CIRCUITS AND METHODS FOR FABRICATING SAME
Abstract
Methods for fabricating integrated circuits are provided. In an
embodiment, a method for fabricating an integrated circuit includes
providing an ultrathin body fully depleted silicon-on-insulator
substrate. The method forms a temporary gate structure over the
substrate and forms lightly doped source/drain extension areas
around the gate structure. Further, the method includes performing
an annealing process on the lightly doped source/drain extension
areas. Outdiffusion from the lightly doped source/drain extensions
is less than 5 nm during the annealing process. The method includes
forming a strain region around the gate structure.
Inventors: |
Illgen; Ralf; (Dresden,
DE) ; Flachowsky; Stefan; (Dresden, DE) |
|
Applicant: |
Name |
City |
State |
Country |
Type |
GLOBALFOUNDRIES, Inc. |
Grand Cayman |
|
KY |
|
|
Family ID: |
49773702 |
Appl. No.: |
14/677503 |
Filed: |
April 2, 2015 |
Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
|
|
13530449 |
Jun 22, 2012 |
9023713 |
|
|
14677503 |
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Current U.S.
Class: |
438/154 ;
438/163 |
Current CPC
Class: |
H01L 29/6659 20130101;
H01L 21/32133 20130101; H01L 21/324 20130101; H01L 29/161 20130101;
H01L 21/823814 20130101; H01L 29/7843 20130101; H01L 21/02576
20130101; H01L 29/78696 20130101; H01L 21/02532 20130101; H01L
29/66628 20130101; H01L 29/165 20130101; H01L 27/1203 20130101;
H01L 21/02529 20130101; H01L 29/51 20130101; H01L 21/28035
20130101; H01L 21/02579 20130101; H01L 29/7848 20130101; H01L
21/823807 20130101; H01L 29/167 20130101; H01L 21/31111 20130101;
H01L 29/7834 20130101; H01L 29/1608 20130101; H01L 21/76283
20130101; H01L 29/6653 20130101; H01L 21/02636 20130101; H01L 21/84
20130101; H01L 29/66553 20130101 |
International
Class: |
H01L 21/84 20060101
H01L021/84; H01L 21/324 20060101 H01L021/324; H01L 29/66 20060101
H01L029/66; H01L 21/02 20060101 H01L021/02; H01L 29/165 20060101
H01L029/165; H01L 21/3213 20060101 H01L021/3213; H01L 29/161
20060101 H01L029/161; H01L 29/78 20060101 H01L029/78; H01L 29/167
20060101 H01L029/167; H01L 21/28 20060101 H01L021/28; H01L 21/311
20060101 H01L021/311; H01L 21/8238 20060101 H01L021/8238; H01L
29/16 20060101 H01L029/16 |
Claims
1. A method for fabricating an integrated circuit comprising:
providing an ultrathin body fully depleted silicon-on-insulator
substrate; forming a temporary gate structure over the substrate;
forming lightly doped source/drain extension areas around the gate
structure; performing an annealing process on the lightly doped
source/drain extension areas, wherein outdiffusion from the lightly
doped source/drain extensions is less than 5 nm during the
annealing process; and forming a strain region around the gate
structure.
2. The method of claim 1 wherein outdiffusion from the lightly
doped source/drain extensions is less than 4 nm.
3. The method of claim 1 wherein outdiffusion from the lightly
doped source/drain extensions is less than 3 nm.
4. The method of claim 1 wherein forming the strain region around
the gate structure comprises forming the strain region around the
gate structure after performing the annealing process.
5. The method of claim 1 wherein the lightly doped source/drain
extension areas are doped with a first dopant and wherein the
method further comprises growing a boron-doped silicon layer free
of the first dopant on the lightly doped source/drain extension
areas.
6. The method of claim 1 wherein forming the compressive strain
region around the PFET gate structure comprises growing a
boron-doped silicon germanium (SiGe) layer.
7. The method of claim 1 wherein forming the compressive strain
region around the PFET gate structure comprises growing a
boron-doped silicon germanium (SiGe) layer, and wherein the method
further comprises growing a boron-doped germanium-free silicon
layer overlying the boron-doped SiGe layer.
8. The method of claim 1 wherein forming the strain region around
the gate structure comprises growing a phosphorus-doped silicon
carbon (SiC) layer.
9. The method of claim 1 wherein forming the strain region around
the gate structure comprises growing a phosphorus-doped silicon
carbon (SiC) layer, and wherein the method further comprises
growing a phosphorus-doped carbon-free silicon layer overlying the
phosphorus-doped SiC layer.
10. A method for fabricating an integrated circuit comprising:
providing an ultrathin body fully depleted silicon-on-insulator
substrate; forming a PFET temporary gate structure and an NFET
temporary gate structure over the substrate; forming lightly doped
active areas around the gate structures; performing a diffusionless
annealing process on the active areas; after performing the
diffusionless annealing process, forming a compressive strain
region around the PFET gate structure; and after performing the
diffusionless annealing process, forming a tensile strain region
around the NFET gate structure.
11. The method of claim 10 wherein performing the diffusionless
annealing process on the active areas comprises limiting
outdiffusion from the active areas to less than 4 nm.
12. The method of claim 10 further comprising: growing a
boron-doped germanium-free silicon layer overlying the compressive
strain region; and growing a phosphorus-doped carbon-free silicon
layer overlying the tensile strain region.
13. The method of claim 10 wherein forming a compressive strain
region around the PFET gate structure comprises growing a
boron-doped silicon germanium (SiGe) layer; wherein forming a
tensile strain region around the NFET gate structure comprises
growing a phosphorus-doped silicon carbon (SiC) layer; and wherein
the method further comprises: growing a boron-doped germanium-free
silicon layer overlying the boron-doped SiGe layer; and growing a
phosphorus-doped carbon-free silicon layer overlying the
phosphorus-doped SiC layer.
14. A method for fabricating an integrated circuit comprising:
providing an ultrathin body fully depleted silicon-on-insulator
substrate; forming a PFET temporary gate structure and an NFET
temporary gate structure on the substrate; forming a compressive
strain region around the PFET temporary gate structure; forming a
tensile strain region around the NFET temporary gate structure;
replacing the PFET temporary gate structure and the NFET temporary
gate structure with high K metal gate HKMG structures.
15. The method of claim 14 wherein forming the compressive strain
region around the PFET temporary gate structure comprises
selectively epitaxially growing an in situ boron-doped (ISBD)
silicon germanium (SiGe) region on the semiconductor substrate, and
wherein forming the tensile strain region around the NFET temporary
gate structure comprises selectively epitaxially growing an in situ
phosphorus-doped (ISPD) silicon carbon (SiC) region.
16. The method of claim 15 further comprising: growing a
boron-doped germanium-free silicon layer overlying the SiGe region;
and growing a phosphorus-doped carbon-free silicon layer overlying
the SiC region.
17. The method of claim 14 wherein providing the semiconductor
substrate comprises providing an ultrathin body fully depleted
silicon-on-insulator (SOI) substrate having an undoped SOI layer
with a thickness of about 5 nanometers (nm).
18. The method of claim 14 further comprising: forming lightly
doped active areas around the gate structures; and performing a
diffusionless annealing process on the active areas.
19. The method of claim 18 wherein performing the diffusionless
annealing process comprises annealing the active areas at a
temperature of about 1200.degree. C. to about 1300.degree. C. and
for a duration of about 1 ms to about 10 ms.
20. The method of claim 14 wherein forming the PFET and NFET
temporary gate structures on the substrate comprises: forming STI
regions in the substrate; depositing a gate oxide layer over the
substrate, a polysilicon layer over the gate oxide layer, and
alternating oxide and nitride layers over the polysilicon layer;
etching the gate oxide, polysilicon, and alternating oxide and
nitride layers to form the temporary gate structures.
Description
CROSS-REFERENCE TO RELATED APPLICATIONS
[0001] This is a divisional of U.S. application Ser. No.
13/530,449, filed Jun. 22, 2012.
TECHNICAL FIELD
[0002] The present disclosure generally relates to integrated
circuits and methods for fabricating integrated circuits, and more
particularly relates to integrated circuits formed from ultrathin
body fully depleted silicon-on-insulator substrates and methods for
fabricating integrated circuits from ultrathin body fully depleted
silicon-on-insulator substrates.
BACKGROUND
[0003] Generally, integrated circuits comprise electronic
components, such as transistors, capacitors, and the like, formed
on and within a wafer. The trend in the semiconductor industry is
towards the miniaturization or scaling of integrated circuits, in
order to provide smaller integrated circuits and improved
performance, such as increased speed and decreased power
consumption. Integrated circuits formed from ultrathin body (UTB)
fully depleted silicon-on-insulator (FDSOI) substrates exhibit
improved performance due to undoped channels and excellent
electrostatic control. Further, the use of UTB FDSOI substrates
leads to very high drive currents and good off-state leakage, ideal
subthreshold slope, and small drain-induced barrier lowering (DIBL)
in devices as short as 20 nm.
[0004] While UTB FDSOI substrates have been identified as providing
improved performance, the introduction of new materials and new
processing schemes is necessary to continue improvement of
performance as device size decreases. Accordingly, it is desirable
to provide integrated circuits formed from ultrathin body fully
depleted silicon-on-insulator substrates that achieve such
improvement of performance and methods for fabricating such
integrated circuits using new materials and new processing schemes.
In addition, it is desirable to provide integrated circuits and
methods for fabricating integrated circuits which include both
compressive strain regions and tensile strain regions to improve
channel mobility. Also, it is desirable to provide methods for
fabricating integrated circuits which utilize diffusionless
annealing. Furthermore, other desirable features and
characteristics will become apparent from the subsequent detailed
description and the appended claims, taken in conjunction with the
accompanying drawings and the foregoing technical field and
background.
BRIEF SUMMARY
[0005] Integrated circuits and methods for fabricating integrated
circuits are provided. In accordance with one embodiment, a method
for fabricating an integrated circuit includes providing an
ultrathin body fully depleted silicon-on-insulator substrate. A
PFET temporary gate structure and an NFET temporary gate structure
are formed on the substrate. The method implants ions to form
lightly doped active areas around the gate structures. A
diffusionless annealing process is performed on the active areas.
Further, a compressive strain region is formed around the PFET gate
structure and a tensile strain region is formed around the NFET
gate structure.
[0006] In another embodiment, a method for fabricating an
integrated circuit is provided and includes providing an ultrathin
body fully depleted silicon-on-insulator substrate and forming a
PFET temporary gate structure and an NFET temporary gate structure
on the substrate. A compressive strain region is formed around the
PFET temporary gate structure and a tensile strain region is formed
around the NFET temporary gate structure. Then, the PFET temporary
gate structure and the NFET temporary gate structure are replaced
with high K metal gate (HKMG) structures.
[0007] In accordance with another embodiment, an integrated circuit
includes an ultrathin body fully depleted silicon-on-insulator
substrate. The integrated circuit also includes a PFET high K metal
gate structure and an NFET high K metal gate structure formed on
the substrate. Further, a silicon germanium compressive strain
region is formed around the PFET high K metal gate structure, and a
silicon carbon tensile strain region formed around the NFET high K
metal gate structure.
BRIEF DESCRIPTION OF THE DRAWINGS
[0008] Embodiments of the integrated circuits and methods for
fabricating integrated circuits will hereinafter be described in
conjunction with the following drawing figures, wherein like
numerals denote like elements, and wherein:
[0009] FIGS. 1-25 illustrate, in cross section, a portion of an
integrated circuit and method steps for fabricating an integrated
circuit in accordance with various embodiments herein.
DETAILED DESCRIPTION
[0010] The following detailed description is merely exemplary in
nature and is not intended to limit the integrated circuits or the
methods for fabricating integrated circuits as claimed herein.
Furthermore, there is no intention to be bound by any expressed or
implied theory presented in the preceding technical field,
background or brief summary, or in the following detailed
description.
[0011] In accordance with the various embodiments herein,
integrated circuits are formed with ultrathin body (UTB) fully
depleted silicon-on-insulator (FDSOI) substrates and exhibit
improved performance due to undoped channels and excellent
electrostatic control. Further, the use of UTB FDSOI substrates
leads to very high drive currents and good off-state leakage, ideal
subthreshold slope, and small drain-induced barrier lowering (DIBL)
in devices as short as 20 nm. The integrated circuits are formed
with compressive strain regions, such as in situ boron-doped (ISBD)
silicon germanium (SiGe) regions, and tensile strain regions, such
as in situ phosphorus-doped (ISPD) silicon carbon (SiC) regions.
Also, the integrated circuits include high K metal gate (HKMG)
structures.
[0012] The integrated circuits fabricated according to the methods
herein exhibit superior short channel behavior, as well as a
greatly reduced random dopant fluctuation due to the combination of
the UTB FDSOI device, the HKMG structures, and diffusionless
annealing processes utilized in the method. The superior short
channel behavior allows for further scaling of gate length and a
reduction of lateral device dimensions, which is important for high
packing density.
[0013] Due to the use of diffusionless annealing in the methods
described herein, ISPD SiC can be utilized to provide for tensile
stressing of NFET regions. As a result, higher electron mobility in
the NFET channel region is achieved. Further, by using in situ
boron doping, the SiGe compressive strain regions can include a
higher germanium content, thereby increasing the strain and
increasing hole mobility in the PFET channel region. As a result of
the non-equilibrium growth conditions of the ISBD and ISPD epitaxy,
the boron and phosphorus content can be much higher than for ion
implantation, which reduces sheet resistance of the extension as
well as of the source/drain areas.
[0014] Further, due to the in situ doping process, deep
source/drain implantations for the NFET and PFET regions are not
necessary. Therefore, the formation of stacking faults for both
transistor types is minimized compared to ion implantation methods.
As a result, a possible relaxation of the SiGe and SiC layers can
be avoided, and a higher stress can be transferred from the strain
regions to the channels, leading to higher drive currents.
[0015] Turning now to FIG. 1, in an exemplary embodiment, the
process of fabricating an integrated circuit 8 begins by providing
a semiconductor substrate 10, such as an ultrathin body (UTB)
silicon-on-insulator (SOI) wafer with an undoped SOI layer 12
having a thickness of about 5 nanometers (nm) overlying a buried
oxide layer 14 and a semiconductor layer 16. Using conventional
processing, shallow trench isolation (STI) regions 20 are formed in
the substrate 10 as shown in FIG. 2 and define an NFET region 22
and a PFET region 24. A temporary gate oxide layer 30, temporary
polysilicon layer 32, an oxide (SiO.sub.2) liner 34, a nitride
(Si.sub.3N.sub.4) cap 36, an oxide (SiO.sub.2) liner 38, and a
nitride (Si.sub.3N.sub.4) cap 40 are then deposited and etched to
form an NFET gate structure 42 and a PFET gate structure 44.
Optionally, the polysilicon of polysilicon layer 32 and the SOI
layer 12 can be reoxidized after formation of the gate structures
42, 44.
[0016] In FIG. 3, an oxide (SiO.sub.2) liner 48 is deposited over
the SOI layer 12 and the gate structures 42, 44. Then, conventional
mask/implantation processes are performed to implant ions to form
lightly doped source/drain extension implants around the NFET gate
structure 42 and the PFET gate structure 44, respectively. An ultra
fast anneal (UFA) process, such as a laser spike anneal (LSA) or
flash lamp anneal (FLA) process is performed to activate the
implants to form active areas 50, 52 while minimizing implant
damage. In an exemplary embodiment, the UFA process is performed in
a temperature range of about 1200.degree. C. to about 1300.degree.
C. and for a duration of about 1 microsecond (ms) to about 10 ms.
The anneal process is diffusionless. As used herein, a
"diffusionless" process exhibits no to very little diffusion, i.e.,
no more than 5 nm outdiffusion from an implanted profile, such as
less than 4 nm outdiffusion, for example less than 3 nm
outdiffusion. Typical rapid thermal anneal (RTA) processes exhibit
outdiffusion of more than about 20 nm.
[0017] After the anneal, a process is commenced for compressively
straining the PFET gate structure 44. In FIG. 4, a nitride layer 56
is deposited over the oxide liner 48. Then, a lithography mask 60
is formed over the NFET region 22, as shown in FIG. 5. In the PFET
region 24, the nitride layer 56 is anisotropically etched to form a
spacer 58. The spacer 58 defines the proximity of compressive
strain regions relative to the channel 62 below the PFET gate
structure 44. The lithography mask 60 is then removed and a
pre-clean process is performed to remove oxide, specifically the
exposed portions of oxide liner 48, i.e., the portions not covered
by the nitride layer 56 or spacer 58, as shown in FIG. 6.
[0018] In FIG. 7, raised compressive strain regions 64 are formed
around the PFET gate structure 44. In an exemplary embodiment, the
regions 64 are formed by in situ boron doped (ISBD) silicon
germanium (SiGe). Specifically, a boron-doped SiGe layer is grown
by a process of selective epitaxial growth on the active area 52
with, for example, a germanium content of about 20% to about 30%
and a boron concentration of about 1e20 to about 5e20 ions/cm.sup.3
to form the compressive strain regions 64. As shown, the
compressive strain regions 64 are formed with epitaxial facets to
reduce parasitic capacitance. Highly boron-doped germanium-free
silicon layers 66 are grown over the regions 64 with, for example,
a boron concentration of about 1e20 to about 5e20 ions/cm.sup.3.
Then the nitride cap 40, nitride spacer 58 and nitride layer 56 are
removed, such as by hot phosphorus etching, resulting in the
structure shown in FIG. 8.
[0019] With the compressive strain regions 64 formed, the process
moves on to tensile straining the NFET gate structure 42. As shown
in FIG. 9, a nitride layer 70 is deposited over the NFET region 22
and PFET region 24. Then, a lithography mask 72 is formed over the
PFET region 24, as shown in FIG. 10. In the NFET region 22, the
nitride layer 70 is anisotropically etched to form a spacer 74. The
spacer 74 is used to define the proximity of tensile strain regions
relative to the channel 76 below the NFET gate structure 42. The
lithography mask 72 is then removed and a pre-clean process is
performed to remove oxide, specifically the exposed portions of
oxide liner 48, i.e., the portions not covered by the nitride layer
70 or spacer 74, as shown in FIG. 11
[0020] In FIG. 12, raised tensile strain regions 80 are formed
around the NFET gate structure 42. In an exemplary embodiment, the
regions 80 are formed by in situ phosphorus doped (ISPD) silicon
carbon (SiC). Specifically, a highly phosphorus-doped SiC layer is
grown on the active area 50 with, for example, a carbon content of
about 1% to about 3% and a phosphorus concentration of about 2e20
to about 6e20 ions/cm.sup.3 to form the regions 80. The tensile
strain regions 80 are formed with epitaxial facets to reduce
parasitic capacitance. Highly phosphorus-doped carbon-free silicon
layers 82 are grown over the regions 80 with, for example, a
phosphorus concentration of about 2e20 to about 6e20 ions/cm.sup.3.
After forming the tensile strain regions 80, the nitride cap 40,
nitride spacer 74 and nitride layer 70 are removed, such as by hot
phosphorus etching, resulting in the structure shown in FIG. 13,
with symmetric NFET and PFET regions 22, 24.
[0021] In FIG. 14, spacers 88 have been formed around gate
structures 42, 44, such as by typical nitride deposition and
etching steps. Then an ultrafast annealing (UFA) process, such as
laser spike annealing (LSA) is performed to activate the dopants in
the extension and deep source/drain areas. The deep source/drain
areas are formed "in-situ" with the epitaxial growth of SiGe:B for
PFET (region 64) and SiC:P for NFET (region 80). The purpose of the
LSA at this step is more or less only to activate the already
present dopants (extension region and in-situ doped epitaxial grown
deep source/drain areas) above the equilibrium solubility limit
since the peak temperature of the LSA is extreme high
(>1250.degree. C. compared to .about.1050.degree. C. with rapid
thermal anneal (RTA) As shown in FIG. 15, the oxide liner 38 and
the exposed portion of the oxide liner 48 are removed in a
pre-clean process to expose the nitride cap 36 in regions 22, 24.
Then a metal layer, such as nickel or platinum, is deposited on and
reacts with the silicon layers 66, 82 to form silicide contacts
92.
[0022] With the silicide contacts 92 formed over the active areas
50, 52, processing continues in FIG. 16 by depositing an interlayer
material 94, such as tetraethyl orthosilicate (TEOS) oxide, over
the NFET and PFET regions 22, 24. Then the interlayer material 94
is polished, such as by chemical mechanical planarization (CMP),
back down to the polysilicon layer 32. As shown in FIG. 17, the
nitride cap 36 and oxide liner 34 are removed during the CMP
process. In FIG. 18, the polysilicon layer 32, the gate oxide layer
30, and vertical portions of oxide liner 48 are removed and will be
replaced by a high K metal gate structure as described below. By
replacing the polysilicon gate structures with high K metal gate
structures, local stress from the strain regions is increased by up
to 50% due to the elimination of repulsive forces from the
temporary polysilicon 32. Further, high K metal gate structures
suppress gate oxide leakages and improve short channel control by
reducing the effective electrical gate oxide thickness.
[0023] To form the HKMG structures, a high-k dielectric 96, such as
Hf-based or Zr-based oxide, is deposited across the NFET and PFET
regions 22, 24. In FIG. 19, a p-metal work function layer 98 is
sputtered over the high-k dielectric 96. A nitride hard mask 100 is
then formed over layer 98, and a mask 102 is formed over the hard
mask 100 in the PFET region 24 as shown in FIG. 20.
[0024] In FIG. 21, the nitride hard mask 100 and p-metal work
function layer 98 are etched from the NFET region 22, before the
mask 102 is removed from the PFET region 24. The nitride hard mask
100 is removed from the PFET region 24 in FIG. 22. Then, an n-metal
work function layer 102 is sputtered over the NFET and PFET regions
22, 24 and a metal fill 104 is deposited as shown in FIG. 23.
[0025] Another polishing step is performed down to the interlayer
material 94 and results in exposing high K metal gate (HKMG)
structures 106, 108 shown in FIG. 24. In FIG. 25, additional
interlayer material 110, such as TEOS, is deposited as an isolator
for further contacts. Then contact holes are formed in the
interlayer materials 94, 110 over the silicide contacts 92 and
metal gate structures 106, 108. A metal layer 112, such as
tungsten, is deposited and fills the contact holes to form vias 114
providing electrical contact with the silicide contacts 92 and
metal gate structures 106, 108. Further back-end-of-line (BEOL)
processing may then occur to finalize the desired integrated
circuit 8.
[0026] To briefly summarize, the fabrication methods described
herein result in integrated circuits 8 with improved performance.
Specifically, the integrated circuit fabrication methods herein
provide for the formation of compressive strain regions and tensile
strain regions through selective epitaxial growth of SiGe and SiC
in a UTB FDSOI device, utilize diffusionless annealing processes
characterized by minimum lateral diffusion and high dopant
activation, and high K metal replacement gate structures. As a
result, the fabricated integrated circuits 8 exhibit superior short
channel behavior, as well as greatly reduced random dopant
fluctuation. This permits further scaling of gate length and a
reduction of lateral device dimensions--an important feature for
high packing density. Also, the implementation of the NFET tensile
strain regions provides for higher electron mobility in the NFET
channel region. The diffusionless annealing process allows
integration of the meta-stable SiC layer as the tensile strain
region. Further, the use of ISBD SiGe to form the compressive
strain regions allows for incorporated a higher germanium content
substitutionally into the SiGe layer, thereby increasing the
compressive strain and leading to higher hole mobility in the PFET
channel region.
[0027] While at least one exemplary embodiment has been presented
in the foregoing detailed description, it should be appreciated
that a vast number of variations exist. It should also be
appreciated that the exemplary embodiment or embodiments described
herein are not intended to limit the scope, applicability, or
configuration of the claimed subject matter in any way. Rather, the
foregoing detailed description will provide those skilled in the
art with a convenient road map for implementing the described
embodiment or embodiments. It should be understood that various
changes can be made in the function and arrangement of elements
without departing from the scope defined by the claims, which
includes known equivalents and foreseeable equivalents at the time
of filing this patent application.
* * * * *