U.S. patent application number 14/144676 was filed with the patent office on 2015-07-02 for semiconductor arrangement with capacitor and method of fabricating the same.
The applicant listed for this patent is Taiwan Semiconductor Manufacturing Company Limited. Invention is credited to Xiaomeng Chen, Chern-Yow Hsu, Ming Chyi Liu, Shih-Chang Liu, Chia-Shiung Tsai, Chen-Jong Wang.
Application Number | 20150187777 14/144676 |
Document ID | / |
Family ID | 53372191 |
Filed Date | 2015-07-02 |
United States Patent
Application |
20150187777 |
Kind Code |
A1 |
Hsu; Chern-Yow ; et
al. |
July 2, 2015 |
SEMICONDUCTOR ARRANGEMENT WITH CAPACITOR AND METHOD OF FABRICATING
THE SAME
Abstract
A semiconductor arrangement includes an active region including
a semiconductor device. The semiconductor arrangement includes a
capacitor. The capacitor includes a first electrode over at least
one dielectric layer over the active region. The first electrode
surrounds an open space within the capacitor. The first electrode
has a non-linear first electrode sidewall.
Inventors: |
Hsu; Chern-Yow; (Chu-Bei
City, TW) ; Liu; Ming Chyi; (Hsinchu City, TW)
; Liu; Shih-Chang; (Alian Township, TW) ; Tsai;
Chia-Shiung; (Hsinchu City, TW) ; Chen; Xiaomeng;
(Hsinchu City, TW) ; Wang; Chen-Jong; (Hsinchu
City, TW) |
|
Applicant: |
Name |
City |
State |
Country |
Type |
Taiwan Semiconductor Manufacturing Company Limited |
Hsin-Chu |
|
TW |
|
|
Family ID: |
53372191 |
Appl. No.: |
14/144676 |
Filed: |
December 31, 2013 |
Current U.S.
Class: |
257/532 ;
438/381 |
Current CPC
Class: |
H01L 27/10814 20130101;
H01L 27/10852 20130101; H01L 28/90 20130101 |
International
Class: |
H01L 27/108 20060101
H01L027/108 |
Claims
1. A semiconductor arrangement comprising: an active region
comprising a semiconductor device; and a capacitor comprising a
first electrode over at least one dielectric layer over the active
region, wherein the first electrode surrounds an open space within
the capacitor.
2. The semiconductor arrangement of claim 1, wherein the first
electrode has a non-linear first electrode sidewall.
3. The semiconductor arrangement of claim 2, comprising an
insulating layer over the first electrode, the insulating layer
having a non-linear insulating layer sidewall.
4. The semiconductor arrangement of claim 3, comprising a second
electrode over the insulating layer, the second electrode having a
non-linear second electrode sidewall.
5. The semiconductor arrangement of claim 4, wherein the capacitor
has a non-linear capacitor sidewall comprising the non-linear first
electrode sidewall, the non-linear insulating layer sidewall and
the non-linear second electrode sidewall.
6. The semiconductor arrangement of claim 1, wherein an aspect
ratio of a height of the capacitor to a width of the capacitor is
between about 5 to about 25.
7. The semiconductor arrangement of claim 1, wherein a height of
the capacitor is between about 250 nm to about 1200 nm.
8. The semiconductor arrangement of claim 1, wherein a width of the
capacitor is between about 30 nm to about 200 nm.
9. The semiconductor arrangement of claim 1, wherein between 1
dielectric layer to 5 dielectric layers are above the
capacitor.
10. The semiconductor arrangement of claim 1, wherein at least one
oxide layer is above the capacitor.
11. A semiconductor arrangement comprising: an active region
comprising a semiconductor device; and a capacitor comprising a
first electrode over at least one dielectric layer over the active
region, the first electrode having a non-linear first electrode
sidewall.
12. The semiconductor arrangement of claim 11, comprising an
insulating layer over the first electrode, the insulating layer
having a non-linear insulating layer sidewall.
13. The semiconductor arrangement of claim 12, comprising a second
electrode over the insulating layer, the second electrode having a
non-linear second electrode sidewall.
14. The semiconductor arrangement of claim 13, wherein the
capacitor has a non-linear capacitor sidewall comprising the
non-linear first electrode sidewall, the non-linear insulating
layer sidewall and the non-linear second electrode sidewall.
15. The semiconductor arrangement of claim 11, wherein an aspect
ratio of a height of the capacitor to a width of the capacitor is
between about 5 to about 25.
16. A method of forming a semiconductor arrangement comprising:
forming a first electrode, of a capacitor, over at least one
dielectric layer over an active region of the semiconductor
arrangement such that the first electrode has a non-linear first
electrode sidewall and surrounds an open space within the
capacitor; forming an insulating layer, of the capacitor, over the
first electrode such that the insulating layer has a non-linear
insulating layer sidewall; and forming a second electrode, of the
capacitor, over the insulating layer such that the second electrode
has a non-linear second electrode sidewall and such that the
capacitor has a non-linear capacitor sidewall.
17.-20. (canceled)
21. The semiconductor arrangement of claim 11, the capacitor
comprising: an insulating layer in contact with the first
electrode; and a second electrode in contact with the insulating
layer.
22. The semiconductor arrangement of claim 21, comprising: a pick
up contact in contact with the second electrode.
23. The semiconductor arrangement of claim 21, wherein an opening
is defined by a sidewall of the second electrode.
24. The semiconductor arrangement of claim 11, the first electrode
electrically coupled to a source/drain region of the semiconductor
device.
Description
BACKGROUND
[0001] Capacitors are useful to, among other things, store
electrical charge within circuits.
DESCRIPTION OF THE DRAWINGS
[0002] Aspects of the disclosure are understood from the following
detailed description when read with the accompanying drawings. It
will be appreciated that elements and/or structures of the drawings
are not necessarily be drawn to scale. Accordingly, the dimensions
of the various features may be arbitrarily increased and/or reduced
for clarity of discussion.
[0003] FIG. 1 illustrates a portion of a semiconductor arrangement
and a cross-section view at intermediate steps of manufacturing the
same, according to an embodiment;
[0004] FIG. 2 illustrates a portion of a semiconductor arrangement
and a cross-section view at intermediate steps of manufacturing the
same, according to an embodiment;
[0005] FIG. 3 illustrates a portion of a semiconductor arrangement
and a cross-section view at intermediate steps of manufacturing the
same, according to an embodiment;
[0006] FIG. 4 illustrates a portion of a semiconductor arrangement
and a cross-section view at intermediate steps of manufacturing the
same, according to an embodiment;
[0007] FIG. 5 illustrates a portion of a semiconductor arrangement
and a cross-section view at intermediate steps of manufacturing the
same, according to an embodiment;
[0008] FIG. 6 illustrates a portion of a semiconductor arrangement
and a cross-section view at intermediate steps of manufacturing the
same, according to an embodiment;
[0009] FIG. 7 illustrates a portion of a semiconductor arrangement
and a cross-section view at intermediate steps of manufacturing the
same, according to an embodiment;
[0010] FIG. 8 illustrates a portion of a semiconductor arrangement
and a cross-section view at intermediate steps of manufacturing the
same, according to an embodiment;
[0011] FIG. 9a illustrates a portion of a semiconductor arrangement
and a cross-section view at intermediate steps of manufacturing the
same, according to an embodiment;
[0012] FIG. 9b illustrates a portion of a semiconductor arrangement
and a cross-section view at intermediate steps of manufacturing the
same, according to an embodiment;
[0013] FIG. 10 illustrates a portion of a semiconductor arrangement
and a cross-section view at intermediate steps of manufacturing the
same, according to an embodiment;
[0014] FIG. 11 illustrates a portion of a semiconductor arrangement
and a cross-section view at intermediate steps of manufacturing the
same, according to an embodiment;
[0015] FIG. 12 illustrates a portion of a semiconductor arrangement
and a cross-section view, according to an embodiment;
[0016] FIG. 13 illustrates a portion of a semiconductor arrangement
and a cross-section view at intermediate steps of manufacturing the
same, according to an embodiment; and
[0017] FIG. 14 illustrates a portion of a semiconductor arrangement
and a cross-section view, according to an embodiment; and
[0018] FIG. 15 is a flow chart illustrating a method of forming a
semiconductor arrangement, according to an embodiment.
DETAILED DESCRIPTION
[0019] The claimed subject matter is now described with reference
to the drawings, wherein like reference numerals are generally used
to refer to like elements throughout. In the following description,
for purposes of explanation, numerous specific details are set
forth in order to provide an understanding of the claimed subject
matter. It is evident, however, that the claimed subject matter may
be practiced without these specific details. In other instances,
structures and devices are illustrated in block diagram form in
order to facilitate describing the claimed subject matter.
[0020] One or more techniques for forming a semiconductor
arrangement and resulting structures formed thereby are provided
herein.
[0021] FIG. 1 is a perspective view illustrating a portion of a
semiconductor arrangement 100 according to some embodiments. In
some embodiments, the semiconductor arrangement 100 is formed in or
on a substrate 102, where an active region 103 is formed in the
substrate 102. In some embodiments, the substrate 102 comprises at
least one of silicon, polysilicon, or germanium. According to some
embodiments, the substrate 102 comprises at least one of an
epitaxial layer, a silicon-on-insulator (SOI) structure, a wafer,
or a die formed from a wafer.
[0022] According to some embodiments, the semiconductor arrangement
100 comprises a logic region 110 and a memory region 120. In an
embodiment, the logic region 110 is formed on or within the active
region 103. In some embodiments, the logic region 110 comprises one
or more logic contacts 112 that are electrically connected within
the logic region 110 and connected to the active region 103.
[0023] According to some embodiments, the memory region 120
comprises one or more DRAM cells. In some embodiments, the memory
region 120 comprises a semiconductor device 122 formed on or within
the active region 103. In some embodiments, the semiconductor
device 122 comprises a gate region 124, a source/drain region 126,
etc. In an embodiment, one or more STI regions 128 are formed
within the active region 103. In some embodiments, the memory
region 120 comprises one or more contacts 130 that are electrically
connected to the source/drain regions 126.
[0024] In some embodiments, the semiconductor arrangement 100
comprises one or more dielectric layers 140 formed over the active
region 103 and the semiconductor device 122. According to some
embodiments, the one or more dielectric layers 140 comprise a first
dielectric layer 140a, a second dielectric layer 140b, a third
dielectric layer 140c, a fourth dielectric layer 140d, and a fifth
dielectric layer 140e. In some embodiments, the dielectric layers
140 comprise a standard dielectric material with a medium or low
dielectric constant, such as SiO.sub.2. In some embodiments, the
dielectric layers 140 comprise a dielectric material with a
relatively high dielectric constant.
[0025] In some embodiments, formation of at least one of the
dielectric layers 140 comprises at least one of thermal growth,
chemical growth, atomic layer deposition (ALD), chemical vapor
deposition (CVD), plasma-enhanced chemical vapor deposition
(PECVD), etc.
[0026] In some embodiments, the semiconductor arrangement 100
comprises one or more low-k dielectric layers 141 formed over the
dielectric layers 140. In some embodiments, the low-k dielectric
layer 141 comprises a dielectric material with a relatively low
dielectric constant, such as SiO.sub.2. Formation of the low-k
dielectric layer 141 comprises at least one of thermal growth,
chemical growth, atomic layer deposition (ALD), chemical vapor
deposition (CVD), plasma-enhanced chemical vapor deposition
(PECVD), etc.
[0027] In some embodiments, the semiconductor arrangement 100
comprises one or more etch stop layers 144 separating the
dielectric layers 140. In some embodiments, the etch stop layers
144 stop an etching process between the dielectric layers 140.
According to some embodiments, the etch stop layers 144 comprise a
dielectric material having a different etch selectivity from the
dielectric layers 140. In some embodiments, one or more of the etch
stop layers 144 comprises SiC, SiN, SiCN, SiCO, CN, etc., alone or
in combination. In some embodiments, formation of at least one of
the etch stop layers 144 comprises at least one of thermal growth,
chemical growth, atomic layer deposition (ALD), chemical vapor
deposition (CVD), plasma-enhanced chemical vapor deposition
(PECVD), etc.
[0028] In some embodiments, the semiconductor arrangement 100
comprises a bit line 150. In an embodiment, the bit line 150
extends through the fourth dielectric layer 140d. According to some
embodiments, the bit line 150 comprises a metal material and is
connected to the source/drain region 126 through a contact 152. In
some embodiments, the bit line 150 is formed in a region or portion
of the semiconductor arrangement 100 between the active region 103
and at least one capacitor. According to some embodiments, a
portion of the bit line 150 and a portion of at least one capacitor
overlap in a horizontal plane. In some embodiments, the bit line
150 and capacitor(s) do not overlap in any horizontal plane.
[0029] In some embodiments, the semiconductor arrangement 100
comprises one or more metal structures 160. In an embodiment, the
metal structures 160 extend through the low-k dielectric layer 141
and the dielectric layers 140. In some embodiments, the metal
structures 160 comprise first metal structures 160a and second
metal structures 160b. Formation of the metal structures 160
comprises at least one of a single damascene process, dual
damascene process, etc. In some embodiments, the metal structures
160 provide an electrical connection through at least one of the
dielectric layers 140 to the semiconductor device 122 of the active
region 103. In some embodiments, the metal structures 160 are
connected to the source/drain regions 126 through the contacts 130.
According to some embodiments, the metal structures 160 comprise
copper, a copper glue layer, TaN, TiN, etc., alone or in
combination.
[0030] Turning to FIG. 2, according to some embodiments, a first
mask layer 200 is formed over the low-k dielectric layer 141. In
some embodiments, the first mask layer 200 covers the logic region
110 and the memory region 120. Formation of the first mask layer
200 comprises at least one of deposition, chemical vapor deposition
(CVD), or other suitable methods, for example. The first mask layer
200 comprises any number of materials, including carbon, oxides,
silicon oxide, nitrides, silicon nitride, Si.sub.3N.sub.4, etc.,
alone or in combination.
[0031] Turning to FIG. 3, according to some embodiments, a second
mask layer 300 is formed over the first mask layer 200. Formation
of the second mask layer 300 comprises at least one of deposition,
chemical vapor deposition (CVD), or other suitable methods, for
example. The second mask layer 300 comprises any number of
materials, including carbon, oxides, silicon oxide, nitrides,
silicon nitride, Si.sub.3N.sub.4, etc., alone or in
combination.
[0032] In some embodiments, the second mask layer 300 is patterned
and etched to form a second mask opening 302. In an embodiment, the
second mask opening 302 is formed over the first metal structures
160a. In some embodiments, the second mask opening 302 is formed
over the second metal structures 160b.
[0033] Turning to FIG. 4, according to some embodiments, the first
mask layer 200 is patterned and etched to form a first mask opening
402. In an embodiment, the first mask opening 402 is formed over
the first metal structures 160a. In some embodiments, the first
mask opening 402 is formed over the second metal structures
160b.
[0034] Turning to FIG. 5, according to some embodiments, the second
mask layer 300 is removed, such as by wet etching, dry etching,
etc. In some embodiments, a first opening 500 and a second opening
502 are formed in the low-k dielectric layer 141 and the dielectric
layers 140. The first opening 500 and second opening 502 are formed
in any number of ways. In some embodiments, the first opening 500
and second opening 502 are formed by etching and removing portions
of the low-k dielectric layer 141, such as by wet etching, copper
wet etching, etc.
[0035] In some embodiments, the first opening 500 is formed by
etching and removing one or more of the first metal structures
160a. According to some embodiments, the first opening 500 is
formed by etching and removing three of the first metal structures
160a. In some embodiments, the second opening 502 is formed by
etching and removing one or more of the second metal structures
160b. According to some embodiments, the second opening 502 is
formed by etching and removing three of the second metal structures
160b. According to some embodiments, an etch chemistry for etching
through the first metal structures 160a or the second metal
structures 160b comprises HNO.sub.3, H.sub.3PO.sub.4, NH.sub.3,
NH.sub.4Cl, H.sub.2SO.sub.4, HCl, HaC, KCN, H.sub.2O.sub.2, etc.,
alone or in combination. In some embodiments, the first opening 500
and second opening 502 are formed by etching through the etch stop
layer 144, such as with a plasma metal etch.
[0036] Turning to FIG. 6, according to some embodiments, a first
electrode 600 is formed within the first opening 500 and second
opening 502 and over the low-k dielectric layer 141. Formation of
the first electrode 600 comprises at least one of atomic layer
deposition (ALD), sputtering, thermal evaporation, chemical vapor
deposition (CVD), etc., for example. According to some embodiments,
a surface portion 602 of the first electrode 600 is formed over the
low-k dielectric layer 141 and the first mask layer 200. In an
embodiment, the first electrode 600 comprises a non-linear first
electrode sidewall 604. In some embodiments, the first electrode
600 comprises a conductive material, such as Ti, TiN, Ta, TaN, TaC,
W, Ir, Ru, Pt, aluminum, copper, polysilicon, etc., alone or in
combination. In an embodiment, the first electrode 600 is
electrically connected to the first metal structures 160a and
second metal structures 160b.
[0037] Turning to FIG. 7, in some embodiments, a bottom
anti-reflective coating (BARC) layer 700 is formed over the first
electrode 600. The BARC layer 700 comprises any number of
materials, including silicon, SiOC, other semiconductor materials,
etc. In some embodiments, the BARC layer 700 is formed within the
first opening 500 and second opening 502.
[0038] Turning to FIG. 8, in some embodiments, the first mask layer
200, the BARC layer 700 and the surface portion 602 of the first
electrode 600 are removed, such as by wet etching, dry etching,
etc. The first mask layer 200 is removed in any number of ways,
such as by wet etching, dry etching, etc. In some embodiments, an
etch chemistry for etching through and removing the BARC layer 700
from the first electrode 600 comprises CF.sub.4, CHF.sub.3,
CH.sub.2F.sub.2, SF.sub.6, O.sub.2, N.sub.2, Ar, He, CO, CO.sub.2,
H.sub.2, Cl.sub.2, etc., alone or in combination. In some
embodiments, a chemical mechanical polishing (CMP) process and
etching back process is used to remove the BARC layer 700 and the
surface portions 602 (illustrated in FIG. 6) of the first electrode
600. In some embodiments, the BARC layer 700 (illustrated in FIG.
7) is formed over the first electrode 600 before removing the
surface portion 602 of the first electrode 600.
[0039] Turning to FIG. 9a, in some embodiments, an insulating layer
900 is formed on the first electrode 600 and on the low-k
dielectric layer 141. In some embodiments, the insulating layer 900
comprises a dielectric material with a relatively high dielectric
constant, such as Al.sub.2O.sub.3, ZrO.sub.2, Ta.sub.2O.sub.5,
HfO.sub.2, La.sub.2O.sub.3, TiO.sub.2, SiO.sub.2, etc., alone or in
combination. In some embodiments, the insulating layer 900
comprises a standard dielectric material with a medium or low
dielectric constant, such as SiO.sub.2. Formation of the insulating
layer 900 comprises at least one of thermal growth, chemical
growth, atomic layer deposition (ALD), chemical vapor deposition
(CVD), plasma-enhanced chemical vapor deposition (PECVD), etc. In
some embodiments, an insulating surface portion 901 is formed over
a portion of the low-k dielectric layer 141. In some embodiments,
the insulating layer 900 has a non-linear insulating layer sidewall
902.
[0040] According to some embodiments, a second electrode 950 is
formed within the first opening 500 and second opening 502 and over
the insulating layer 900. Formation of the second electrode 950
comprises at least one of atomic layer deposition (ALD),
sputtering, thermal evaporation, chemical vapor deposition (CVD),
etc., for example. In some embodiments, the second electrode 950
comprises a conductive material, such as Ti, TiN, Ta, TaN, TaC, W,
Ir, Ru, Pt, aluminum, copper, polysilicon, etc., alone or in
combination. In some embodiments, an electrode surface portion 951
is formed over the insulating surface portion 901 of the insulating
layer 900. According to some embodiments, the insulating layer 900
is between the first electrode 600 and the second electrode 950. In
some embodiments, the second electrode 950 has a non-linear second
electrode sidewall 952.
[0041] In some embodiments, a capacitor 975 is comprised of the
first electrode 600, insulating layer 900, and second electrode 950
and is over the memory region 120. Although first 975a and second
975b capacitors are illustrated, any number of capacitors are
contemplated. In some embodiments, the capacitor 975 extends
through between 2 dielectric layers 140 to 10 dielectric layers
140. In an embodiment, the capacitor 975 has a non-linear capacitor
sidewall 980 comprising the non-linear first electrode sidewall
604, the non-linear insulating layer sidewall 902, and the
non-linear second electrode sidewall 952. According to some
embodiments, the first electrode 600, along with the insulating
layer 900 and second electrode 950, surrounds an open space 982
within the capacitor 975. In an embodiment, the second electrode
950 defines the open space 982 within the capacitor 975. In some
embodiments, the open space 982 defines an area that is
substantially void of material.
[0042] In some embodiments, the open space 982 extends, or is
formed in (or within) any number of layers of material disposed
over the substrate 102, or, any number of dielectric layers 140 in
the semiconductor arrangement 100. In some embodiments, the open
space 982 extends, or is formed in (or within), 2 to 10 dielectric
layers 140. In some embodiments, the open space 982 is formed in
(or within) the dielectric layer(s) 140a, 140b, 140c above the
fourth dielectric layer 140d that includes the bit line 150.
According to some embodiments, a portion of the open space 982
extends into, or is formed in (or within) the dielectric layer(s)
140 containing the bit line 150.
[0043] In some embodiments, the semiconductor arrangement 100
comprises a plurality of capacitors 975, each of which includes a
capacitor sidewall 980 defining a portion of the open space 982.
According to some embodiments, the semiconductor arrangement 100
includes a first open space 982 associated with or defined by the
first capacitor 975a and a second open space 982 associated with or
defined by the second capacitor 975b, and the height of the first
open space 982 is taller than, or, alternatively, shorter than that
of the second open space 982. According to some embodiments, the
semiconductor arrangement 100 includes a first open space 982
associated with or defined by the first capacitor 975a and a second
open space 982 associated with or defined by the second capacitor
975b, and the width of the first open space 982 is wider than or,
alternatively, narrower than that of the second open space 982. In
some embodiments, the semiconductor arrangement 100 includes a
plurality of capacitors 975 with, or defining, a plurality of open
spaces 982 or areas, where at least two of the open spaces 982 have
different heights and/or widths relative to one another.
[0044] According to some embodiments, the semiconductor arrangement
100 includes at least one capacitor 975 that extends into a region
or layer of the semiconductor arrangement 100 containing the bit
line 150. In some embodiments, the semiconductor arrangement 100
includes at least one capacitor 975 that extends into a region or
layer of the semiconductor arrangement 100 containing the bit line
150 and at least one capacitor 975 that does not extend into a
region or layer of the semiconductor arrangement 100 containing the
bit line 150. According to some embodiments, at least one capacitor
975 and/or open space 982 is higher than or, alternatively, shorter
than, at least one other capacitor 975 and/or open space 982. In
some embodiments, at least one capacitor and/or open space is wider
than, or, alternatively, narrower than, at least one other
capacitor 975 and/or open space 982. According to some embodiments,
width of at least one capacitor 975 and/or open space 982 varies
along a longitudinal axis. In some embodiments, the longitudinal
axis is perpendicular, or, substantially perpendicular, to a top
surface of the substrate 102. According to some embodiments, at
least one capacitor 975 and/or open space 982 includes a region or
portion with decreasing, or, alternatively, increasing,
width(s).
[0045] In some embodiments, a height 984 of the capacitor 975 is
measured from a bottom surface 990 of the first electrode 600 to a
top surface 992 of the second electrode 950. In some embodiments,
the height 984 of the capacitor 975 is between about 250 nm to
about 1200 nm. In some embodiments, a width 986 of the capacitor
975 is measured between opposing non-linear capacitor sidewalls
980. In some embodiments, the width 986 of the capacitor 975 is
between about 30 nm to about 200 nm. According to some embodiments,
an aspect ratio of the capacitor 975 represents the height 984 of
the capacitor 975 to the width 986 of the capacitor 975. In some
embodiments, the aspect ratio of the capacitor 975 is between about
5 to about 25.
[0046] Turning to FIG. 9b, according to some embodiments, the first
capacitor 975a and second capacitor 975b are illustrated in which
the non-linear capacitor sidewalls 980 have a different, non-linear
shape than the non-linear capacitor sidewalls 980 illustrated in
FIG. 9a. In an embodiment, the non-linear capacitor sidewalls 980
comprise a plurality of sidewall portions. According to some
embodiments, the non-linear capacitor sidewalls 980 of the first
capacitor 975a and second capacitor 975b comprise a first sidewall
portion 981a, a second sidewall portion 981b, a third sidewall
portion 981c, and a fourth sidewall portion 981d. In an embodiment,
the first sidewall portion 981a extends non-linearly with respect
to the second sidewall portion 981b. In an embodiment, the second
sidewall portion 981b extends non-linearly with respect to the
third sidewall portion 981c. In an embodiment, the third sidewall
portion 981c extends non-linearly with respect to the fourth
sidewall portion 981d.
[0047] Turning to FIG. 10, according to some embodiments, a third
mask layer 1000 is formed over the second electrode 950 of the
capacitor 975. In some embodiments, the third mask layer 1000
covers the memory region 120. Formation of the third mask layer
1000 comprises at least one of deposition, chemical vapor
deposition (CVD), or other suitable methods, for example. The third
mask layer 1000 comprises any number of materials, including
carbon, oxides, silicon oxide, nitrides, silicon nitride,
Si.sub.3N.sub.4, etc., alone or in combination.
[0048] In some embodiments, the third mask layer 1000 is patterned
and etched to form a third mask opening 1002. In an embodiment, the
third mask opening 1002 is formed over the insulating surface
portion 901 of the insulating layer 900 and over the electrode
surface portion 951 of the second electrode 950.
[0049] Turning to FIG. 11, according to some embodiments, the third
mask layer 1000, the insulating surface portion 901 of the
insulating layer 900 and the electrode surface portion 951 of the
second electrode 950 are removed, such as by wet etching, dry
etching, etc. In some embodiments, an etch chemistry for removing
the insulating surface portion 901 and the electrode surface
portion 951 is selective enough so as to not remove the low-k
dielectric layer 141.
[0050] According to some embodiments, an etch stop layer 1100 is
formed over the second electrode 950, the low-k dielectric layer
141, and the open space 982. In some embodiments, the etch stop
layer 1100 stops an etching process from reaching the low-k
dielectric layer 141. According to some embodiments, the etch stop
layer 1100 comprises a dielectric material having a different etch
selectivity from the low-k dielectric layer 141. In some
embodiments, the etch stop layer 1100 comprises SiC, SiN, SiCN,
SiCO, CN, etc., alone or in combination. Formation of the etch stop
layer 1100 comprises at least one of thermal growth, chemical
growth, atomic layer deposition (ALD), chemical vapor deposition
(CVD), plasma-enhanced chemical vapor deposition (PECVD), etc.
[0051] According to some embodiments, a dielectric layer 1110 is
formed over the etch stop layer 1100 and over the second electrode
950 of the capacitor 975. In an embodiment, the dielectric layer
1110 comprises a standard dielectric material with a medium or low
dielectric constant, such as SiO.sub.2. In some embodiments, the
dielectric layer 1110 comprises a dielectric material with a
relatively high dielectric constant. Formation of the dielectric
layer 1110 comprises at least one of thermal growth, chemical
growth, atomic layer deposition (ALD), chemical vapor deposition
(CVD), plasma-enhanced chemical vapor deposition (PECVD), etc.
According to some embodiments, between 1 dielectric layer 1110 to 5
dielectric layers 1110 are above the capacitor 975.
[0052] According to some embodiments, a BARC layer 1120 is formed
over the dielectric layer 1110. The BARC layer 1120 comprises any
number of materials, including silicon, SiOC, other semiconductor
materials, etc.
[0053] Turning to FIG. 12, according to some embodiments, the BARC
layer 1120 is removed, such as by wet etching, dry etching, etc. In
some embodiments, an etch chemistry for etching through and
removing the BARC layer 1120 from the first electrode 600 comprises
CF.sub.4, CHF.sub.3, CH.sub.2F.sub.2, SF.sub.6, O.sub.2, N.sub.2,
Ar, He, CO, CO.sub.2, H.sub.2, Cl.sub.2, etc., alone or in
combination. In some embodiments, after the BARC layer 1120 is
removed, a first opening 1200 and a second opening 1202 are formed
in the dielectric layer 1110 and the etch stop layer 1100.
[0054] According to some embodiments, a pick up contact 1220 is
formed in the first opening 1200. In some embodiments, the pick up
contact 1220 is electrically coupled to the capacitor 975. In an
embodiment, the pick up contact 1220 extends through the dielectric
layer 1110 and the etch stop layer 1100. In some embodiments, the
pick up contact 1220 is in contact with the insulating layer 900
and the second electrode 950. Formation of the pick up contact 1220
comprises at least one of a single damascene process, dual
damascene process, etc.
[0055] According to some embodiments, a via contact 1222 is formed
in the second opening 1102. In an embodiment, the via contact 1222
extends through the dielectric layer 1110 and the etch stop layer
1100. In some embodiments, the via contact 1222 is in contact with
the logic contact 112. Formation of the via contact 1222 comprises
at least one of a single damascene process, dual damascene process,
etc.
[0056] FIG. 13 illustrates a second example semiconductor
arrangement 1300. According to some embodiments, the second
semiconductor arrangement 1300 comprises the logic region 110,
active region 103, semiconductor device 122, dielectric layers 140,
capacitor 975, etc.
[0057] According to some embodiments, after the third mask layer
1000, the electrode surface portion 951, and the insulating surface
portion 901 are removed, as illustrated in FIG. 10, etch stop
layers 1100, 1310 and oxide layers 1350 are formed. In some
embodiments, the etch stop layer 1100 is formed over the second
electrode 950 and the low-k dielectric layer 141. In some
embodiments, the etch stop layers 1100, 1310 comprise a dielectric
material having a different etch selectivity from the low-k
dielectric layer 141. In some embodiments, the etch stop layers
1100, 1310 comprise SiN, SiCN, SiCO, CN, etc., alone or in
combination. Formation of the etch stop layers 1100, 1310 comprises
at least one of thermal growth, chemical growth, atomic layer
deposition (ALD), chemical vapor deposition (CVD), plasma-enhanced
chemical vapor deposition (PECVD), etc.
[0058] In some embodiments, at least one oxide layer 1350 is formed
between the etch stop layers 1100, 1310 and above the second
electrode 950 of the capacitor 975. Formation of the oxide layers
1350 comprises at least one of deposition, chemical vapor
deposition (CVD), or other suitable methods, for example. The oxide
layers 1350 comprise any number of materials, including oxides,
silicon oxide, nitrides, silicon nitride, oxynitrides, SiO.sub.2,
etc., alone or in combination.
[0059] According to some embodiments, a BARC layer 1370 is formed
over the oxide layer 1350. The BARC layer 1370 comprises any number
of materials, including silicon, SiOC, SiON, other semiconductor
materials, etc.
[0060] Turning to FIG. 14, according to some embodiments, the BARC
layer 1370 is removed, such as by wet etching, dry etching, etc. In
some embodiments, an etch chemistry for etching through and
removing the BARC layer 1370 from the first electrode 600 comprises
CF.sub.4, CHF.sub.3, CH.sub.2F.sub.2, SF.sub.6, O.sub.2, N.sub.2,
Ar, He, CO, CO.sub.2, H.sub.2, Cl.sub.2, etc., alone or in
combination. In some embodiments, after the BARC layer 1370 is
removed, a first opening 1400 and a second opening 1402 are formed
in the oxide layer 1350 and the etch stop layers 1100, 1310.
[0061] According to some embodiments, a pick up contact 1420 is
formed in the first opening 1400. In an embodiment, the pick up
contact 1420 extends through the oxide layer 1350 and the etch stop
layers 1100, 1310. According to some embodiments, the pick up
contact 1420 is electrically coupled to the capacitor 975. In some
embodiments, the pick up contact 1420 is in contact with the
insulating layer 900 and the second electrode 950. Formation of the
pick up contact 1420 comprises at least one of a single damascene
process, dual damascene process, etc.
[0062] According to some embodiments, a via contact 1422 is formed
in the second opening 1402. In an embodiment, the via contact 1422
extends through the oxide layer 1350 and the etch stop layers 1100,
1310. In some embodiments, the via contact 1422 is in contact with
the logic contact 112. Formation of the via contact 1422 comprises
at least one of a single damascene process, dual damascene process,
etc.
[0063] An example method 1500 of forming a semiconductor
arrangement, such as semiconductor arrangement 100, 1300 according
to some embodiments, is illustrated in FIG. 15. At 1502, a first
electrode 600, of a capacitor 975, is formed over at least one
dielectric layer 140 over an active region 103 of the semiconductor
arrangement 100, 1300 such that the first electrode 600 has a
non-linear first electrode sidewall 604 and surrounds an open space
982 within the capacitor 975. At 1504, an insulating layer 900, of
the capacitor 975, is formed over the first electrode 600 such that
the insulating layer 900 has a non-linear insulating layer sidewall
902. At 1506, a second electrode 950, of the capacitor 975, is
formed over the insulating layer 900 such that the second electrode
950 has a non-linear second electrode sidewall 952 and such that
the capacitor 975 has a non-linear capacitor sidewall 980.
[0064] According to some embodiments, the height of the bit line
150 is less than a height of the active region 103. In some
embodiments, the height of the bit line 150 is less than a height
of the capacitor 975. According to some embodiments, the capacitor
975 is positioned over the bit line 150, such that the
semiconductor arrangement 100, 1300 comprises a
capacitor-over-bitline (COB). As such, in some embodiments, the
resistance (R.sub.b) between the bit line 150 and the capacitor 975
is reduced. Likewise, parasitic capacitance (C.sub.b) is also
reduced. According to some embodiments, the capacitor 975 comprises
the non-linear capacitor sidewalls 980, such that a length of the
non-linear capacitor sidewalls 980 is greater than the height 984
of the capacitor 975. As such, in some embodiments, capacitance of
the capacitor 975 is increased relative to a capacitor without such
non-linear capacitor sidewalls.
[0065] In an embodiment, a semiconductor arrangement comprises an
active region comprising a semiconductor device. In an embodiment,
the semiconductor arrangement comprises a capacitor comprising a
first electrode over at least one dielectric layer over the active
region. In an embodiment, the first electrode surrounds an open
space within the capacitor.
[0066] In an embodiment, a semiconductor arrangement comprises an
active region comprising a semiconductor device. In an embodiment,
the semiconductor arrangement comprises a capacitor comprising a
first electrode over at least one dielectric layer over the active
region. In an embodiment, the first electrode has a non-linear
first electrode sidewall.
[0067] In an embodiment, a method of forming a semiconductor
arrangement comprises forming a first electrode, of a capacitor,
over at least one dielectric layer over an active region of the
semiconductor arrangement such that the first electrode has a
non-linear first electrode sidewall and surrounds an open space
within the capacitor. In an embodiment, the method comprises
forming an insulating layer, of the capacitor, over the first
electrode such that the insulating layer has a non-linear
insulating layer sidewall. In an embodiment, the method comprises
forming a second electrode, of the capacitor, over the insulating
layer such that the second electrode has a non-linear second
electrode sidewall and such that the capacitor has a non-linear
capacitor sidewall.
[0068] Although the subject matter has been described in language
specific to structural features or methodological acts, it is to be
understood that the subject matter of the appended claims is not
necessarily limited to the specific features or acts described
above. Rather, the specific features and acts described above are
disclosed as example forms of implementing at least some of the
claims.
[0069] Various operations of embodiments are provided herein. The
order in which some or all of the operations are described should
not be construed to imply that these operations are necessarily
order dependent. Alternative ordering will be appreciated having
the benefit of this description. Further, it will be understood
that not all operations are necessarily present in each embodiment
provided herein. Also, it will be understood that not all
operations are necessary in some embodiments.
[0070] It will be appreciated that layers, regions, features,
elements, etc. depicted herein are illustrated with particular
dimensions relative to one another, such as structural dimensions
and/or orientations, for example, for purposes of simplicity and
ease of understanding and that actual dimensions of the same differ
substantially from that illustrated herein, in some embodiments.
Additionally, a variety of techniques exist for forming the layers,
regions, features, elements, etc. mentioned herein, such as
implanting techniques, doping techniques, spin-on techniques,
sputtering techniques, growth techniques, such as thermal growth
and/or deposition techniques such as chemical vapor deposition
(CVD), for example.
[0071] Moreover, "exemplary" is used herein to mean serving as an
example, instance, illustration, etc., and not necessarily as
advantageous. As used in this application, "or" is intended to mean
an inclusive "or" rather than an exclusive "or". In addition, "a"
and "an" as used in this application and the appended claims are
generally be construed to mean "one or more" unless specified
otherwise or clear from context to be directed to a singular form.
Also, at least one of A and B and/or the like generally means A or
B or both A and B. Furthermore, to the extent that "includes",
"having", "has", "with", or variants thereof are used, such terms
are intended to be inclusive in a manner similar to the term
"comprising". Also, unless specified otherwise, "first," "second,"
or the like are not intended to imply a temporal aspect, a spatial
aspect, an ordering, etc. Rather, such terms are merely used as
identifiers, names, etc. for features, elements, items, etc. For
example, a first region and a second region generally correspond to
region A and region B or two different or two identical regions or
the same type region.
[0072] Also, although the disclosure has been shown and described
with respect to one or more implementations, equivalent alterations
and modifications will occur to others skilled in the art based
upon a reading and understanding of this specification and the
annexed drawings. The disclosure comprises all such modifications
and alterations and is limited only by the scope of the following
claims. In particular regard to the various functions performed by
the above described components (e.g., elements, resources, etc.),
the terms used to describe such components are intended to
correspond, unless otherwise indicated, to any component which
performs the specified function (e.g., that is functionally
equivalent), even though not structurally equivalent to the
disclosed structure. In addition, while a particular feature of the
disclosure may have been disclosed with respect to only one of
several implementations, such feature may be combined with one or
more other features of the other implementations as may be desired
and advantageous for any given or particular application.
* * * * *