U.S. patent application number 14/508205 was filed with the patent office on 2015-04-09 for spine routing with multiple main spines.
The applicant listed for this patent is Synopsys Taiwan Co., Ltd.. Invention is credited to Tung-Chieh CHEN, Chun-Cheng CHI, Chien-Hung Lu.
Application Number | 20150100938 14/508205 |
Document ID | / |
Family ID | 52778016 |
Filed Date | 2015-04-09 |
United States Patent
Application |
20150100938 |
Kind Code |
A1 |
Lu; Chien-Hung ; et
al. |
April 9, 2015 |
SPINE ROUTING WITH MULTIPLE MAIN SPINES
Abstract
A computer implemented method of routing a net of an electronic
circuit is disclosed. The net connects a plurality of pins of the
electronic circuit. The method includes selecting, using one or
more computer systems, first and second main spine routing tracks
for respective first and second groups of pins of the net. The
method also includes generating, using one or more computer
systems, a first main spine wire on the selected first main spine
routing track and a second main spine wire on the selected second
main spine routing track. A router configured to perform the method
is also disclosed.
Inventors: |
Lu; Chien-Hung; (Hsinchu
City, TW) ; CHI; Chun-Cheng; (Hsinchu City, TW)
; CHEN; Tung-Chieh; (Hsinchu City, TW) |
|
Applicant: |
Name |
City |
State |
Country |
Type |
Synopsys Taiwan Co., Ltd. |
Taipei |
|
TW |
|
|
Family ID: |
52778016 |
Appl. No.: |
14/508205 |
Filed: |
October 7, 2014 |
Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
|
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61888932 |
Oct 9, 2013 |
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Current U.S.
Class: |
716/131 |
Current CPC
Class: |
G06F 30/394 20200101;
G06F 2111/06 20200101; G06F 2119/10 20200101 |
Class at
Publication: |
716/131 |
International
Class: |
G06F 17/50 20060101
G06F017/50 |
Claims
1. A computer implemented method of routing a net of an electronic
circuit, wherein the net connects a plurality of pins of the
electronic circuit, the method comprising: selecting, using one or
more computer systems, at least first and second main spine routing
tracks for respective at least first and second groups of pins of
the net; and generating, using one or more computer systems, a
first main spine wire on the selected first main spine routing
track and a second main spine wire on the selected second main
spine routing track.
2. The method of claim 1, wherein the first and second main spine
routing tracks are selected in accordance with a first cost
function.
3. The method of claim 1, further comprising partitioning, using
the one or more computer systems, the pins of the net into first
and second groups of pins in accordance with a second cost
function.
4. The method of claim 3, wherein the pins of the net are
partitioned based on the locations of the pins.
5. The method of claim 4, wherein the pins of the net are
partitioned such that the locations of the pins of each group are
within a single standard cell row.
6. The method of claim 4, wherein the pins of the net are
partitioned such that the locations of the pins of each group are
within a set of adjacent standard cell rows.
7. The method of claim 4, wherein the pins of the net are
partitioned such that the locations of the pins of each group are
within a predetermined distance of a main spine routing track
associated with the group.
8. The method of claim 1, wherein the first and second main spine
routing tracks are respectively selected based on the locations of
the pins of the first and second groups of pins.
9. The method of claim 1, further comprising generating a main
branch spine connecting the first and second main spine wires.
10. The method of claim 1, further comprising: automatically
selecting third and fourth main spine routing tracks for the first
and second groups of pins, respectively; automatically generating a
third main spine wire on the selected third main spine routing
track and a fourth main spine wire on the selected fourth main
spine routing track; automatically generating an electrical
connection between the first and third main spine wires; and
automatically generating an electrical connection between the
second and fourth main spine wires.
11. The method of claim 1, further comprising: automatically
generating first and second shielding wires parallel to the first
main spine wire, wherein the first and second shielding wires are
connected to a shielding node; and automatically generating the
third and fourth shielding wires parallel to the second main spine
wire, wherein the third and fourth shielding wires are connected to
the shielding node.
12. A router, configured to route a net of an electronic circuit,
wherein the net connects a plurality of pins of the electronic
circuit, the router comprising: a memory comprising instructions;
and a processor configured to execute the instructions, wherein the
instructions cause the computer to perform a method, comprising:
selecting, using one or more computer systems, at least first and
second main spine routing tracks for respective at least first and
second groups of pins of the net; and generating, using one or more
computer systems, a first main spine wire on the selected first
main spine routing track and a second main spine wire on the
selected second main spine routing track.
13. The router of claim 12, wherein the first and second main spine
routing tracks are selected in accordance with a first cost
function.
14. The router of claim 12, wherein the method further comprises
partitioning, using the one or more computer systems, the pins of
the net into first and second groups of pins in accordance with a
second cost function.
15. The router of claim 14, wherein the pins of the net are
partitioned based on the locations of the pins.
16. The router of claim 15, wherein the pins of the net are
partitioned such that the locations of the pins of each group are
within a single standard cell row.
17. The router of claim 15, wherein the pins of the net are
partitioned such that the locations of the pins of each group are
within a set of adjacent standard cell rows.
18. The router of claim 15, wherein the pins of the net are
partitioned such that the locations of the pins of each group are
within a predetermined distance of a main spine routing track
associated with the group.
19. The router of claim 12, wherein the first and second main spine
routing tracks are respectively selected based on the locations of
the pins of the first and second groups of pins.
20. The router of claim 12, wherein the method further comprises
generating a main branch spine connecting the first and second main
spine wires.
21. The router of claim 12, wherein the method further comprises:
automatically selecting third and fourth main spine routing tracks
for the first and second groups of pins, respectively;
automatically generating a third main spine wire on the selected
third main spine routing track and a fourth main spine wire on the
selected fourth main spine routing track; automatically generating
an electrical connection between the first and third main spine
wires; and automatically generating an electrical connection
between the second and fourth main spine wires.
22. The router of claim 12, wherein the method further comprises:
automatically generating first and second shielding wires parallel
to the first main spine wire, wherein the first and second
shielding wires are connected to a shielding node; and
automatically generating the third and fourth shielding wires
parallel to the second main spine wire, wherein the third and
fourth shielding wires are connected to the shielding node.
Description
CROSS-REFERENCES TO RELATED APPLICATIONS
[0001] This application claims benefit under 35 USC 119 (e) of U.S.
provisional Application No. 61/888,932, filed on Oct. 9, 2013, the
contents of all of which are incorporated herein by reference in
their entirety. The present application is related to commonly
assigned U.S. patent application Ser. No. 13/289,965 titled
"Multiple Level Spine Routing" filed Nov. 4, 2011, and U.S. patent
application Ser. No. 13/289,963 titled "Multiple Level Spine
Routing" filed Nov. 4, 2011, both of which claim priority to
commonly assigned U.S. Provisional Application No. 61/417,839 filed
Nov. 29, 2010, the contents of all of which are incorporated herein
by reference in their entirety.
BACKGROUND
[0002] The present invention relates generally to a method and
system for computer aided design (CAD) of integrated circuits and
in particular to finding a flexible way for routing a net.
[0003] In electronic circuits, electrical conductors are typically
layers of conductive material such as copper or aluminum that are
separated by layers of insulating material such as silicon dioxide.
The metal layers are patterned using photolithographic techniques
to form the conductors for interconnecting electrical elements in
an integrated circuit (IC). The design or layout of a complex IC
may, in part, be automated such that the location of
interconnection wires is determined with the aid of a computer
running CAD routing software. The computer is accordingly called a
router. In the context of discussions related to the operation of
the computer, electronic representations of information
corresponding with physical elements are frequently referred to
using terms which more generally identify the corresponding
physical elements. For example, in the context of discussions
related to the operation of the computer, a wire is often an
electronic representation of information corresponding to an
electrical conductor of an electronic device or a circuit. For
example, a wire may be an electronic representation of information
representing an electrical conductor within an electronic
representation of a circuit design. Based on the electronic
representation of the circuit design, a physical circuit may be
generated.
SUMMARY OF THE INVENTION
[0004] One inventive aspect is a computer implemented method of
routing a net of an electronic circuit, where the net connects a
plurality of pins of the electronic circuit. The method includes
selecting, using one or more computer systems, first and second
main spine routing tracks for respective first and second groups of
pins of the net. The method also includes generating, using one or
more computer systems, a first main spine wire on the selected
first main spine routing track and a second main spine wire on the
selected second main spine routing track.
[0005] Another inventive aspect is a router, configured to route a
net of an electronic circuit, where the net connects a plurality of
pins of the electronic circuit. The router including a memory
including instructions, and a processor configured to execute the
instructions, where the instructions cause the computer to perform
a method. The method includes selecting, using one or more computer
systems, first and second main spine routing tracks for respective
first and second groups of pins of the net. The method also
includes generating, using one or more computer systems, a first
main spine wire on the selected first main spine routing track and
a second main spine wire on the selected second main spine routing
track.
BRIEF DESCRIPTION OF THE DRAWINGS
[0006] Various embodiments of the invention are disclosed in the
following detailed description and the accompanying drawings.
[0007] FIG. 1 depicts a simplified plan view of two exemplary net
routing problems.
[0008] FIG. 2 depicts a simplified plan view of a wire routing
example using a single main spine wire for one of the exemplary
routing problems depicted in FIG. 1.
[0009] FIG. 3 depicts a simplified plan view of a wire routing
example using multiple main spine wires for another one of the
exemplary routing problems depicted in FIG. 1, in accordance with
one embodiment of the present invention.
[0010] FIG. 4A depicts a simplified plan view of a wire routing
example using a single main spine wire for routing a net with a
misaligned track pattern.
[0011] FIG. 4B depicts a simplified plan view of a wire routing
example using multiple main spine wires for routing the net
depicted in FIG. 4A, in accordance with one embodiment of the
present invention.
[0012] FIG. 5 depicts a first simplified flow chart for routing a
net using multiple main spine wires, in accordance with one
embodiment of the present invention.
[0013] FIG. 6 depicts a second simplified flow chart for routing a
net using multiple main spine wires, in accordance with one
embodiment of the present invention.
[0014] FIG. 7A depicts a simplified plan view of a wire routing
example using multiple main spine wires for routing a net after
partitioning pins of the net into groups associated with main spine
wires, in accordance with one embodiment of the present
invention.
[0015] FIG. 7B depicts a simplified plan view of a wire routing
example using multiple main spine wires for routing a net after
estimating available tracks associated with main spines, in
accordance with one embodiment of the present invention.
[0016] FIG. 7C depicts a simplified plan view of a wire routing
example using multiple main spine wires for routing a net after
generating main spines and a main branch spine, in accordance with
one embodiment of the present invention.
[0017] FIG. 7D depicts a simplified plan view of a wire routing
example using multiple main spine wires for routing a net after
generating at least one branch spine, in accordance with one
embodiment of the present invention.
[0018] FIG. 7E depicts a simplified plan view of a wire routing
example using multiple main spine wires for routing a net after
generating wires connecting unconnected pins to their associated
branch spine, in accordance with one embodiment of the present
invention.
[0019] FIG. 8 depicts a simplified plan view of a wire routing
example using multiple main spine wires for routing a net using a
re-use prewire, in accordance with one embodiment of the present
invention.
[0020] FIG. 9A depicts a simplified plan view of a wire routing
example using multiple main spine wires for routing without using
compact routing, in accordance with one embodiment of the present
invention.
[0021] FIG. 9B depicts a simplified plan view of a wire routing
example using multiple main spine wires for routing using compact
routing, in accordance with one embodiment of the present
invention.
[0022] FIG. 9C depicts a simplified plan view of a wire routing
example using multiple main spine wires for routing using compact
routing to a power/ground line, in accordance with one embodiment
of the present invention.
[0023] FIG. 10A depicts a simplified plan view of a wire routing
example using multiple main spine wires for routing a net using
loop routing, in accordance with one embodiment of the present
invention.
[0024] FIG. 10B depicts a portion of the simplified plan view of a
wire routing example using multiple main spine wires for routing a
net using loop routing depicted in FIG. 10A, in accordance with one
embodiment of the present invention.
[0025] FIG. 11 depicts a simplified plan view of a wire routing
example multiple main spine wires for routing a net using shield
routing, in accordance with one embodiment of the present
invention.
[0026] FIGS. 12A-12B depict a simplified plan view of wire routing
examples using one of the multiple main spine wires for routing a
net using finger pin connection routing, in accordance with one
embodiment of the present invention.
[0027] FIG. 13A depicts a simplified plan view of wire routing
example using a first exemplary constraint for partitioning pins of
the net into groups associated with main spine wires, in accordance
with one embodiment of the present invention.
[0028] FIG. 13B depicts a simplified plan view of wire routing
example using a second exemplary constraint for partitioning pins
of the net into groups associated with main spine wires, in
accordance with one embodiment of the present invention.
[0029] FIG. 13C depicts a simplified plan view of wire routing
example using a third exemplary constraint for partitioning pins of
the net into groups associated with main spine wires, in accordance
with one embodiment of the present invention.
[0030] FIG. 14 is a block diagram of a computer system that may
incorporate embodiments of the present invention.
DETAILED DESCRIPTION
[0031] The following examples provide a brief introduction to wire
routing. FIG. 1 depicts a simplified plan view of two exemplary net
routing problems 100. The first net routing problem includes a
multitude of pins 110, a multitude of blockages 120, and a first
layout plane 130. The second net routing problem includes the same
multitude of pins 110 and multitude of blockages 120, but in
contrast includes a second layout plane 140. Solving the two
routing problems includes determining the paths for wires between
blockages 120 such that each pin of multitude of pins 110 of the
net are connected together by wires within either first layout
plane 130 or second layout plane 140, respectively.
[0032] Wires extending from within a net beyond the layout boundary
of the same net may cause problems with routing other adjacent
nets. Accordingly, the routing problem posed by first layout plane
130 may be easier to solve than the routing problem posed by second
layout plane 140 because second layout plane 140 includes a smaller
layout area, which imposes additional routing constraints compared
to first layout plane 130, as will be explained below. The area and
boundaries of a layout plane, the locations of blockages, and the
locations of pins may be included as part of the data or
specification of the net for a given IC design and may be
positioned in fixed locations before routing, or placed during or
as a part of the routing process.
[0033] Blockages 120 occur where certain parts of a layout plane
may be blocked by wire segments, hereinafter also referred to as
"pre-wires", placed in predetermined locations associated with IC
components that are fixed in position, for example, by a separate
placement process executed before routing, or are placed during or
as a part of the routing process. Examples of pre-wires include
power and ground lines not arranged in a regular row structure. The
blockages on an interconnect layer form a "maze" that the routing
process will avoid or route around when routing that interconnect
layer.
[0034] Various techniques and styles exist for routing an
integrated circuit design. Spine routing, also known as fishbone
routing, provides many advantages over other routing techniques.
For example, spine routing can reduce vias and jogs on
interconnects and can result in better routing quality in terms of
factors such as timing delay and signal integrity.
[0035] FIG. 2 depicts a simplified plan view 200 of a wire routing
example 200 using a single main spine wire 210, hereinafter also
referred to as "main spine," for the first net routing problem of
plane 130 in FIG. 1. The wire routing connects each pin of the
multitude of pins 110 of the net together. The wire routing
includes a single main spine 210, a multitude of branch spines 220,
and a multitude of wires 230. For example, single main spine 210
may be formed on a patterned metal two layer, hereinafter also
referred to as "M2", which may be a horizontal routing layer. The
multitude of branch spines 220 may be formed on a patterned metal
one layer, hereinafter also referred to as "M1", which may be a
vertical routing layer that underlies the M2 layer on the IC. The
multitude of wires 230 may be formed on M2. Similar fill code
patterns in the figures denote the same metal layer.
[0036] It is understood that M2 has been assigned as a horizontal
routing layer by way of example and could, alternatively, be
assigned as a vertical routing layer. Although in some of the
provided examples horizontal and/or vertical routing of spines is
described, the techniques disclosed herein may be similarly
employed for any other spine orientations. Adjacent metal layers
such as M1 and M2 are commonly assigned to substantially orthogonal
routing layers. Although the figures show just two metal layers by
way of example, the embodiments of the present invention may be
applicable to an arbitrary number of wire layers. For example,
single main spine 210 may be formed on a metal three layer (M3),
the multitude of branch spines 220 may be formed on M2, and the
multitude of wires 230 may be formed on M1.
[0037] There may be conductive vias connecting different metal
layers, for example at an intersection of a M1 wire and M2 wire
such as at locations 240 and 250 to complete the electrical
continuity of the electrical path between each of the multitude of
pins of the net. However, for better clarity, the conductive vias
are not shown in the figures but are understood to be present. A
circle symbolically denotes a pin of the multitude of pins 110,
which may be one end point of the net. Typically, each pin
represents a connection point to an electrical component of the IC
design. Generally, a net associated with an integrated circuit
design includes a wiring connection that carries a signal from a
driving pin to receiving pins. A net, hereinafter also referred to
as a "path," includes any combination of electrically connected
wire segments such as single main spine 210, the multitude of
branch spines 220, and the multitude of wires 230 that electrically
connect pins of the net using only wires or vias to make the
electrical connection. In other words, a single net is
schematically represented by a single electrical node in a
schematic drawing.
[0038] Nets may also include patterned polysilicon or
single-crystal-diffusion wire segments that are commonly overlaid
with a refractory metal layer to reduce resistivity. In other
words, a net or path is a continuous electrical connection of metal
wires and metal vias that is unbroken by any other passive or
active components such as resistors, capacitors, transistors, or
the like. For example, a resistor may have a resistivity per unit
length that is at least an order of magnitude higher than that of
any portion of a net. In another example, first and second nets may
be separated by a transistor having a drain connected to the first
net and a source connected to the second net. However, it is
understood that nets may have distributed electrical attributes
such as parasitic resistance and capacitance, which are usually
undesired and become larger for longer paths. Thus, when routing a
net a shorter length is more desirable than a longer length.
[0039] Potential locations for wires may be in predetermined tracks
separated by a spacing specified by design rules for a given
process technology and fabrication facility. The data representing
track locations may be part of the specification of the net. Thus,
the locations of wires are constrained to the tracks that for a
given layer. For example, M2 may only run in one direction, e.g.
horizontal or vertical. The figures may depict a wire as a long
rectangular shape or alternatively as a simplified symbolic line
segment with a longitudinal axis typically placed or generated by
the routing process in the centerline of an available track and
spaced away from a blockage by a spacing design rule.
[0040] The routing process may be constrained because the locations
of the blockages and pin locations may typically be fixed prior to
routing. For the example depicted in FIG. 2 using first layout
plane 130, it is noted that the multitude of pins 110 of the net
fall generally into two regions that are separated by blockages 120
such that solutions to link the two regions of pins via a single
main spine wire having a horizontal longitudinal direction are
constrained to the region below blockages 120. Further, because the
single main spine is positioned relatively far from the two groups
of pins, the total length of the net is relatively large. However,
referring to FIGS. 1 and 2, a single main spine wire solution would
be difficult for the routing problem as constrained by second
layout plane 140, which is coincident with the lower border of
blockages 120 and thereby may prevent single main spine wire
routing solutions.
[0041] FIG. 3 depicts a simplified plan view of a wire routing
example 300 using multiple main spines 310, 320 for the second
routing problem of FIG. 1, and which includes second layout plane
140. FIG. 3 depicts similar features as FIG. 2 with the following
exceptions being noted. FIG. 3 depicts a wire routing including a
first main spine 310, a second main spine 320, a main branch spine
330, a multitude of branch spines 340, and a multitude of wires
230. Main branch spine 330 directly connects first main spine 310
to a second main spine 320.
[0042] Although the second layout plane 140 provides less routing
area than first layout plane 130, an advantageous routing solution
is obtained by using a multitude of main spine wires that are
oriented both horizontally and vertically. Thus, the use of
multiple main spine wires, according to embodiments of the present
invention, provides greater flexibility in obtaining routing
solutions for certain situations where preexisting constraints may
make a single main spine routing solution less desirable or
impossible due to lack of available main spine tracks. As shown by
comparing the routing results of FIGS. 2 and 3, the total length of
the net may be reduced by using multiple main spine routing,
thereby improving circuit performance by reducing unwanted
parasitic capacitance and/or resistance of the net. Reducing the
length of the net may also free up routing tracks, which
consequently may be made available to route other nets, saving
routing resources and potentially reducing chip size and cost.
These advantages of multiple main spine routing are greater when
the net extends for a longer distance.
[0043] In one embodiment, pins that are horizontally spaced apart
by more than a predetermined distance may connect directly to the
branch spines 340. In some embodiments, pins that are horizontally
spaced apart by less than a predetermined distance connect directly
to one of the multitude of wires 230, which connect the pins to one
of the multitude of branch spines 340.
[0044] FIG. 4A depicts a simplified plan view of a wire routing
example 400A using a single main spine wire 420 for routing a net
with a misaligned track pattern. Example 400A includes first and
second multitudes of regularly spaced horizontal tracks 430, 440.
The leftmost ends of the first multitude of regularly spaced
horizontal tracks 430 overlap with the rightmost ends of the second
multitude of regularly spaced horizontal tracks 440. However, the
pitch of the first multitude of regularly spaced horizontal tracks
430 is different than the pitch of the second multitude of
regularly spaced horizontal tracks 440. Accordingly, single main
spine wire 420 may be placed so as to be properly centered
longitudinally on one track of the first multitude of regularly
spaced horizontal tracks 430 but not on one of the tracks of the
second multitude of regularly spaced horizontal tracks 440.
[0045] FIG. 4B depicts a simplified plan view of a wire routing
example 400B using multiple main spine wires 450, 460 for routing a
net to the pins depicted in FIG. 4A, in accordance with one
embodiment of the present invention. In example 400B, the net is
routed using multiple main spines 450, 460, where each main spine
is placed so as to be properly centered on one of the first and
second multitude of regularly spaced horizontal tracks 430, 440. In
addition, main spines 450 and 460 are connected by main branch
spine 470.
[0046] FIG. 5 depicts a first simplified flow chart 500 of an
embodiment of routing a net having multiple pins using multiple
main spine wires. Referring to FIGS. 3 and 5, the computer selects
510, using one or more computer systems, a first spine routing
track from a first set of preexisting selectable routing tracks for
a first group of the multitude of pins, and selecting a second
spine routing track from a second set of preexisting selectable
routing tracks for a second group of the multitude of pins.
[0047] In some embodiments, the multitude of pins are partitioned
into groups based on their location, for example, as discussed in
more detail elsewhere herein. In some embodiments, each of the
groups of pins are associated with a set of selectable routing
tracks based on their location, for example, as discussed in more
detail elsewhere herein. The first and second spine routing tracks
are selected in accordance with a first cost function and further
in accordance with data associated with the net and the first and
second multitudes of routing tracks. The data may include the
positions of each of the pins of the net and each of the available
routing tracks of the first and second multitudes of routing tracks
for the net, for a given IC design. The computer implemented method
may further include generating 520 a first spine wire 310 on the
selected first spine routing track and a second spine wire 320 on
the selected second spine routing track.
[0048] In some embodiments, the method also includes generating 530
a main branch spine 470 which first spine wire 310 and second spine
wire 320.
[0049] In one embodiment, the first cost function may include a
wire length of a portion of the net or of the total net wire
length. In another embodiment, the first cost function may include
a count of the number of vias of the net and/or other cost
functions described below.
[0050] FIG. 6 depicts a second simplified flow chart 600 for
routing a net using multiple main spine wires, in accordance with
one embodiment of the present invention. The data associated with
the net and the first and second multitude of routing tracks is
received 610 for the routing process. The data received may include
locations of pins, blockages, and selectable tracks available for
wire placement for the net. Routing an entire integrated circuit
generally includes routing a large number of nets.
[0051] FIG. 7A depicts a simplified plan view of a wire routing
example 700A using multiple main spine wires for routing a net
after partitioning 620 a multitude of pins 710 associated with the
net into a multitude of groups 715, 716, 717, in accordance with
one embodiment of the present invention. Referring to FIGS. 6 and
7A, each group of the multitude of groups 715, 716, 717 includes
one or more pins. Wire routing example 700A includes a multitude of
blockages 720 similar to blockage 120 depicted in FIG. 1. The
multitude of pins 710 are depicted as small circles. Pins 710
within the same group are depicted with the same fill pattern
different than the fill pattern of pins 710 in other groups. Each
one of the multitude of groups 715, 716, 717 may be associated with
a different one of the multitude of main spine wires, as will be
discussed below.
[0052] In this embodiment, the method includes partitioning 620 the
pins 710 associated with the net into at least a first and a second
group of pins. In this embodiment, first group of pins 715 may be
associated with the main spine routing track to be selected as the
first main spine routing track, second group of pins 716 may be
associated with the main spine routing track to be selected later
as the second main spine routing track, and third group of pins 717
may be associated with the main spine routing track to be selected
later as the third main spine routing track. It is understood that
the multitude of pins 710 may be decomposed or partitioned into a
multitude of groups corresponding to different ones of a multitude
of main spine wires, and that the three groups of pins
corresponding to the first, second, and third second main spine
wires are an example and do not limit the scope of the present
invention. Partitioning 620 may be done in accordance with a second
cost function. In one embodiment, the first cost function includes
the second cost function. In one embodiment, the second cost
function includes a wire length. In one embodiment, the second cost
function includes a rule associated with a constraint, which will
be discussed below.
[0053] FIG. 7B depicts a simplified plan view of a wire routing
example 700B using multiple main spine wires for routing a net
after estimating or selecting 630 available horizontal M2 tracks
725, 726, 727 associated with main spines, in accordance with one
embodiment of the present invention. Recall that wires are
constrained to run in available tracks that are not blocked by
blockages. Thus, available tracks are potential locations that
wires may be placed. Thus, the multitude of available horizontal M2
routing tracks 725, 726, 727 are available for placement of main
spine wires. However, no wires have been placed yet at this stage
in the method.
[0054] Referring to FIGS. 6 and 7B, the multitude of available
horizontal M2 routing tracks 725, 726, 727 may be partitioned
according to the locations of the nearest groups of partitioned
pins. For example, the multitude of horizontal M2 routing tracks
725, 726, 727 may be associated with respective ones of the
multitude of partitioned groups of pins 715, 716, 717. In other
words, the multitude of available horizontal M2 routing tracks 725
may be associated with the first group of pins 715, the multitude
of available horizontal M2 routing tracks 726 may be associated
with the second group of pins 716, and the multitude of available
horizontal M2 routing tracks 727 may be associated with the third
group of pins 717. In one embodiment, the multitude of available
horizontal M2 routing tracks 725 is substantially parallel to the
multitude of available horizontal M2 routing tracks 726 and
727.
[0055] Similarly, a multitude of routing tracks for at least one
main branch spine may be estimated at step 630 from a multitude of
available vertical M1 routing tracks (not shown) in accordance with
a third cost function, and further in accordance with data
associated with the multitude of available vertical M1 routing
tracks. The data may include the positions of each of the available
vertical M1 routing tracks for a given IC design. In one
embodiment, a multitude of vertical M1 routing tracks may be
estimated to connect all of the selected horizontal M2 routing
tracks to obtain a routing solution around blockages or to obtain
the optimally shortest total net wire length. In one embodiment,
the longitudinal orientation of the multitude of available M1
routing tracks may be substantially orthogonal to the longitudinal
orientation of the multitude of available M2 routing tracks. In one
embodiment, the third cost function may include a wire length of
the selected M1 track. In one embodiment, one or more of the first
cost function, the second cost function, and the third cost
function are the same.
[0056] FIG. 7C depicts a simplified plan view of a wire routing
example 700C using multiple main spine wires for routing a net
after generating 640 main spines 735, 736, 737 and a main branch
spine 740, in accordance with one embodiment of the present
invention. Referring to FIGS. 6 and 7B-7C, main spines are
generated or placed 640 after determining which available tracks to
use for each of the multitude of horizontal M2 routing tracks 725,
726, 727. As shown in FIG. 7C, a different main spine wire 735,
736, 737 is generated for each group of pins 715, 716, 717. For
example, available horizontal M2 main spine track 735T may be
selected to generate horizontal M2 main spine wire 735 associated
with the first group of pins 715, available horizontal M2 main
spine track 736T may be selected to generate horizontal M2 main
spine wire 735 associated with the second group of pins 716, and an
available horizontal M2 main spine track 737T may be selected to
generate horizontal M2 main spine wire 737 associated with the
third group of pins 717.
[0057] Similarly, at least one main branch spine is generated or
placed 640 by deciding which single available track to use from the
multitude of vertical M1 routing tracks (not shown) to generate a
vertical M1 main branch spine wire that connects the multitude of
generated horizontal M2 main spine wires. For example, an available
vertical M1 main branch track (not shown) may be selected to
generate vertical M1 main branch spine wire 740 to connect together
horizontal M2 main spine wires 735, 736, 737.
[0058] FIG. 7D depicts a simplified plan view of a wire routing
example 700D using multiple main spine wires for routing a net
after generating 650 at least one branch spine 745, 747, in
accordance with one embodiment of the present invention. Referring
to FIGS. 6 and 7D, in this embodiment, branch spines are generated
by the following actions. For each branch spine, one of the group
of pins, is partitioned into a sub-group of pins to connect with
the branch spine and another sub-group of pins including the
remaining pins of the one group of pins according to a fourth cost
function. A vertical M1 spine routing track may then be selected
from the multitude of selectable vertical M1 routing tracks (not
shown) associated with the one group of pins in accordance with a
position of at least one of main spine wires. In the example of
FIG. 7D, the third main spine wire 737 may be used to select the
selected vertical M1 routing track. A vertical M1 branch spine wire
747 is subsequently generated on the selected vertical M1 spine
routing track.
[0059] In one embodiment, the selected vertical M1 routing track
for vertical M1 branch spine wire 747 is substantially orthogonal
to horizontal M2 main spine track 735T and horizontal M2 main spine
track 737T. In one embodiment, a vertical M1 branch spine wire 745
is generated such that vertical M1 branch spine wire 745 connects a
single pin sub-group to the first main spine wire 735. In this
example, the selected vertical M1 routing track is used to connect
to the first spine wire 735.
[0060] FIG. 7E depicts a simplified plan view of a wire routing
example 700E using multiple main spine wires for routing a net
after generating wires 750 connecting unconnected pins to their
associated branch spine 747, in accordance with one embodiment of
the present invention. Referring to FIGS. 6 and 7D, for each
sub-group of pins, a wire 750 is generated connecting the
unconnected pins to the closest branch spine of that sub-group. In
one embodiment, wire 750 is substantially orthogonal to the
associated branch spine 747 connected to wire 750.
[0061] FIG. 8 depicts a simplified plan view of a wire routing
example 800 using multiple main spine wires for routing a net using
a re-use prewire 833, in accordance with one embodiment of the
present invention. Features depicted in FIG. 8 are similar to the
features depicted in FIG. 7E with the following exceptions being
noted. In one embodiment, any combination of the first, second
and/or third cost functions may include a distance to a
predetermined feature of the net. In one embodiment, the
predetermined feature of the net may include at least one of a pin,
a preexisting wire, or a via that may be placed by the designer in
the data associated with the net before the routing is performed.
The predetermined feature may be identified such that the presence
of the predefined feature triggers and/or instructs the routing
process to perform special functions. In one embodiment, the
predetermined feature may be a preexisting wire identified as the
re-use prewire, e.g. re-use prewire 833 on M2.
[0062] In some embodiments, in response to an identification of a
re-use prewire 833, the computer uses the first and/or second cost
function to select the same horizontal M2 track as used by re-use
prewire 833 to generate a horizontal M2 main spine wire 835. For
this function, the distance for the cost function associated with
the re-use prewire is zero, i.e. the distance from the spine track
to be selected and the re-use pre-wire's track is zero. Thus, the
track of re-use prewire 833 is "reused" for the horizontal M2 main
spine wire 835. Analogously, in one embodiment, a vertical M1
pre-wire may be placed in the net data as a prewire to instruct the
routing process to select the M1 pre-wire's routing track for the
main branch spine. This feature is useful, for example, if a wire
track is used by a previously placed layout cell and it is desired
to minimize the use of tracks to conserve routing resources.
[0063] FIG. 9A depicts a simplified plan view of a wire routing
example 900A using multiple main spine wires for routing without
using compact routing, in accordance with one embodiment of the
present invention. Wire routing example 900A includes horizontal M2
power or ground wires 910 placed in predetermined positions before
or during routing. Wire routing example 900A further includes
horizontal M2 main spines 920, 930, and 940, which are placed
according to the standard routing process without the special
feature of compact routing. Horizontal M2 main spines 920, 930, and
940 may be associated with the same net or different nets.
[0064] FIG. 9B depicts a simplified plan view of a wire routing
example 900B using multiple main spine wires for routing using
compact routing, in accordance with one embodiment of the present
invention. Features depicted in FIG. 9B are similar to the features
depicted in FIG. 9A with the following exceptions being noted. Wire
routing example 900B includes horizontal M2 main spines 922, 942
which correspond to horizontal M2 main spines 920, 940,
respectively, except the process is run with the added cost
function constraint that any combination of the first, second
and/or third cost functions includes a distance to a predetermined
feature of another net. In the depicted example, spine wires of a
same metal layer are compacted. As shown, horizontal M2 main spines
922, 942 are placed in selected tracks next to horizontal M2 main
spine 930. In this example, the feature is any other selected track
on the same metal layer and the distance in the cost function may
be the closest adjoining track on the same metal layer. This
compact routing feature may be useful for situations where
additional space is desirable, for example, to place other
components or interconnections after running the routing
process.
[0065] FIG. 9C depicts a simplified plan view of a wire routing
example 900C using multiple main spine wires for routing using
compact routing to a power/ground line, in accordance with one
embodiment of the present invention. Features depicted in FIG. 9C
are similar to the features depicted in FIG. 9B with the following
exceptions being noted. Wire routing example 900C includes
horizontal M2 main spines 920, 932, 944 which respectively
correspond with horizontal M2 main spines 922, 930, 942,
respectively, except the process is run with the added cost
function constraint that the predetermined feature may be any power
or ground wires on the same metal layer. Accordingly, the
horizontal main spine wires 920, 932, 944 are placed preferentially
in tracks adjacent the horizontal M2 power or ground wires 910.
This feature may help isolate noise transmission between wires by
using adjacent power or ground lines as electromagnetic
shielding.
[0066] In some embodiments, the computer may receive information
indicating that a particular net is to be routed with low
resistance. In response to the indication, the computer may
automatically cause the net to be routed with low resistance
connections. For example, in response to the information, the
computer may reduce the length or increase the width of wires. In
some embodiments, in response to the information, the computer is
configured to generate more than one main spine wire for a single
group of pins to be connected therewith. In some embodiments, the
information includes an indication of which layer of metal to use
for a main spine wire, in response to which, the computer causes
the main spine wire to be routed with the indicated layer. The
information may, for example, be provided to the computer in a
description of the circuit to be routed.
[0067] FIG. 10A depicts a simplified plan view of a wire routing
example 1000A using multiple horizontal M2 main spine wires 1032,
1036 for routing a group of pins of a net using loop routing, in
accordance with one embodiment of the present invention. Wire
routing example 1000A includes blockages 1020 analogous to
blockages 720 depicted in FIG. 7A, horizontal M2 main spine wire
1036 analogous to horizontal M2 main spine wire 736, and vertical
M1 main branch spine wire 1040 analogous to vertical M1 main branch
spine wire 740 depicted in FIG. 7C. As depicted in FIG. 10A during
routing, the computer may select an additional horizontal M2 main
spine track from the multitude of M2 routing tracks associated with
a group of pins. The computer then generates additional horizontal
M2 main spine wire 1032 on the selected additional horizontal M2
main spine track. Vertical M1 main branch spine wire 1040 may be
connected to the additional horizontal M2 main spine wire 1032 by
an extension 1040B to the vertical M1 main branch spine wire 1040
as depicted in more detail in FIG. 10B. In some embodiments, an
additional vertical main branch spine wire (not shown) is
additionally generated, where the additional vertical main branch
spine wire is also connected to main spine wires 1032, 1036.
[0068] In some embodiments, the computer fills the gap or at least
a portion of the gap between the main spine wires 1032, 1036 with a
wire (not shown). In some embodiments, the computer fills the gap
or at least a portion of the gap between main branch spine wire
1040 and the additional vertical main branch spine wire with a wire
(not shown).
[0069] FIG. 10B depicts a detailed portion 1000B of the wire
routing example 1000A of an example using multiple horizontal M2
main spine wires 1032, 1036 for routing a net using loop routing
depicted in FIG. 10A, in accordance with one embodiment of the
present invention. Detailed portion 1000B includes M1/M2 vias 1050
that connect vertical M1 main branch spine wire 1040 and extension
1040B to one of the two longitudinal ends of horizontal M2 main
spine wire 1036 and additional horizontal M2 main spine wire 1032.
As shown, main branch spine wire 1040 forms a parallel connection
of a multitude of horizontal M2 main spine wires. This provides
improved performance and reliability for the net. Additional
horizontal M2 main spine wire 1032 may be formed, for example, in a
horizontal M2 spine track adjacent to the wire track selected for
horizontal M2 main spine wire 1036 or in a non-adjacent track.
Analogously, in another embodiment, main branch spine wire 1040 may
be connected to an additional main branch spine wire (not shown).
Any additional number of spine wires may be added by the routing
process.
[0070] In some embodiments, the computer may receive information
indicating that a particular net is to be shielded. In response to
the indication, the computer may automatically cause the net to be
routed with a shielding wire. For example, in response to the
information, the computer may generate a shielding wire adjacent to
the particular net, where the adjacent shielding wire is connected
to a power supply or ground net. In some embodiments, the shielding
wire surrounds or substantially surrounds the particular net. The
information may, for example, be provided to the computer in a
description of the circuit to be routed.
[0071] FIG. 11 depicts a simplified plan view of a wire routing
example 1100 using multiple main spine wires 1135, 1136, 1140 for
routing a net using shield routing, in accordance with one
embodiment of the present invention. The M1 layer is shown
overlying the M2 layer to better describe the embodiments in the
figure. However, it is understood that the M1 layer is below the M2
when deposited on the IC. As described above, routing a spine wire
adjacent to another wire on the same metal layer may provide
electromagnetic shielding. The shielding may be further improved by
partially or completely surrounding a spine wire with additional
wires placed in adjacent tracks. The additional wires, may, for
example, be connected to another net such as power or ground. Wire
routing example 1100 further includes M2 ring wires 1135R, 1136R
that respectively shield horizontal M2 main spine wires 1135, 1136,
and includes M1 ring wire 1140R that shields vertical M1 main
branch spine wire 1140. In this example, M2 ring wires 1135R, 1136R
and M1 ring wire 1140R may be connected to ground (VSS) by vias
(not shown). The spines of the net may thus be completely
surrounded by shielding wires when the routing process is run
automatically. Alternatively, partially shielding the net spines
may be nearly as effective and may be provided by adding shielding
wires in parallel adjacent tracks to the spine wires without using
fully enclosing ring shield wires.
[0072] In some embodiments, the computer may receive information
indicating that a particular net is to be connected to one or more
circuit cell pins at more than one pin location. In response to the
indication, the computer may automatically cause the net to be
connected with the circuit at multiple pin locations. For example,
in response to the information, the computer may generate a wire
for the net extending across the circuit cell such that the
generated wire crosses multiple pin locations of the circuit cell.
The computer may additionally generate vias or contacts at
intersections of the generate wire and the pin locations. The
information may, for example, be provided to the computer in a
description of the circuit to be routed.
[0073] FIGS. 12A-12B depict a simplified plan view of wire routing
examples using one of the multiple main spine wires 1235 for
routing a net using finger pin connection routing, in accordance
with one embodiment of the present invention. In one embodiment,
any combination of the first, second and/or third cost functions
may include a resistivity of an interconnect layer. In some circuit
cells, such as in memory cell designs, there may be interconnect
layers, such as polysilicon or diffusion with higher resistivity
than metal spine layers. The pin connection layer of such a circuit
cell corresponds with portions of the cell to which wires may be
routed to electrically connect the circuit cell with other
circuits. As shown in FIGS. 12A and 12B, the computer may
automatically extend or route one of the main spine wires 1235 to
extend over the circuit cell such that the main spine wire may be
connected to pin connection layer 1260 at multiple locations.
Because the low resistance main spine wire connects to the circuit
cell at multiple locations, at least a portion of the internal high
resistance interconnect layers is shunted by the main spine wire.
Contacts or vias 1250 may be added by the computer at locations
where the main spine wire 1235 overlaps the pin connection layer
1260. The overlap regions where contacts or vias are to be placed
are automatically spaced apart to meet the corresponding spacing
design rules for contact or vias.
[0074] FIG. 12A depicts one embodiment of the present invention
where main spine wire 1235A overlaps the pin connection layer 1260
close to an end of the circuit cell. FIG. 12B depicts one
embodiment of the present invention where main spine wire 1235B
overlaps the pin connection layer 1260 close to a middle region of
the circuit cell.
[0075] FIG. 13A depicts a simplified plan view of wire routing
example 1300A using a first exemplary constraint for partitioning
pins of the net into a multitude of groups 1315, 1316, 1317 each
associated with a different one of the multitude of main spine
wires 1335, 1336, 1337 respectively, in accordance with one
embodiment of the present invention. During standard-cell placement
before routing, a multitude of cell-placement rows 1361, 1362,
1363, 1364 may be defined and the standard-cells or other layout
cell types may be placed according to these rows. Each row defines
an area or region where standard-cells may be placed. The use of
such cell-placement rows may be called row-based design.
Standard-cells may include various circuit components such as
transistors, resistors, capacitors, or other components including
connection pins for routing a net thereto. Standard-cells or other
layout cell types not placed in cell-placement rows may be placed
anywhere on the design, called row-less-based design.
[0076] During or in preparation for routing the design, for
example, during net decomposition, the pins of a net may be
partitioned (e.g., step 620 depicted in FIG. 6) into groups
according to a cost function, which may include a rule associated
with one or more constraints. For row-based designs, the cost
function may include the multitude of cell-placement rows. One
constraint may be that pins of the net are partitioned into a group
according to an associated row of the multitude of cell-placement
rows. Thus, the multitude of groups 1315, 1316, 1317 may each be
partitioned according to a different one of the associated
multitude of cell-placement rows 1361, 1363, 1364. Accordingly,
each of the multitude of groups 1315, 1316, 1317 is associated with
a different one of the multitude of main spine wires 1335, 1336,
1337. As a result, because pins on a same row share a corresponding
same spine, this type of pin partitioning may be called one-row
one-spine. For example, the pins of group 1315 may be partitioned
into group 1315 from the multitude of pins of the net as a result
of being located in cell-placement row 1363, and group of pins 1316
may be partitioned into group 1316 from the multitude of pins of
the net as a result of being located in cell-placement row
1361.
[0077] FIG. 13B depicts a simplified plan view of wire routing
example 1300B using a second exemplary constraint for partitioning
pins of the net into groups 1315, 1316 associated with main spine
wires, in accordance with one embodiment of the present invention.
FIG. 13B depicts similar features as those depicted in FIG. 13A
with the following exceptions being noted. For row-based designs,
the constraint may be that pins of the net are partitioned into
groups according to an adjacent rows of the cell-placement rows.
Thus, the multitude of groups 1315, 1316 may each be partitioned
according to a different one of the pairs of cell-placement rows
1361-1362, 1363-1364. Each of the groups 1315, 1316 is associated
with a different one of the multitude of main spine wires 1336,
1338. As a result, because pins on a same pair of rows share a same
corresponding main spine wire, this type of pin partitioning may be
called two-row one-spine. For example, the pins of group 1315 may
be partitioned into group 1315 from the multitude of pins of the
net as a result of being located in cell-placement row pair
1363-1364, and the pins of group 1316 may be partitioned into group
1316 from the multitude of pins of the net as a result of being
located in cell-placement row 1361-1362.
[0078] In this two-row one-spine example, because the group of pins
1315 is evenly distributed between cell-placement rows 1362 and
1364, the computer selects a track for routing main spine 1338 that
is located close to the intersection of cell-placement rows 1362
and 1364. However, because the group of pins 1316 is distributed
within cell-placement row 1361, the computer selects a track for
routing main spine 1336 that is located within that same
cell-placement row 1361. It is understood that the computer may
additionally use other constraints, such as total wire length and
blockage locations, to partition groups of pins. Further, the
computer may use total wire length and blockage locations along
with any combination of one-row one-spine or two-row one-spine
constraints.
[0079] FIG. 13C depicts a simplified plan view of wire routing
example 1300C using a third exemplary constraint for partitioning
pins of the net into groups 1315, 1316 associated with main spine
wires 1338, 1336, respectively, in accordance with one embodiment
of the present invention. FIG. 13C depicts similar features as
those depicted in FIG. 13B with the following exceptions being
noted. For either row-based designs (not shown) or for
row-less-based designs, one constraint may be that pins of the net
are partitioned into a group according to a predefined distance, D.
In one embodiment D is defined in the direction orthogonal to the
longitudinal axis of one of the main spine wires, 1338. In one
embodiment, D is defined as the maximum length of one edge of a
rectangular region enclosing a group of pins. Thus, the multitude
of groups 1315, 1316 may be partitioned according to a rectangular
box 1370 having one side of length D perpendicular to the direction
of main spine wire 1338. Pins enclosed by rectangular box thousand
370 are partitioned into group of pins 1350. Pins not enclosed by
rectangular box 1370 are partitioned into group of pins 1316. Each
of the multitude of groups 1315, 1316 may be associated with a
different one of the multitude of main spine wires 1336, 1338. In
one embodiment, the computer similarly constrains the length of
branch spines (not shown) to be roughly D/2.
[0080] FIG. 14 is a simplified block diagram of a computer system
that may incorporate aspects and features of the disclosed
embodiments of the present invention. FIG. 14 is merely
illustrative of an embodiment incorporating the present invention
and does not limit the scope of the invention as recited in the
claims. One of ordinary skill in the art would recognize other
variations, modifications, and alternatives.
[0081] In one embodiment, computer system 1400 typically includes a
monitor 1410, a computer 1420, user output devices 1430, user input
devices 1440, communications interface 1450, and the like.
[0082] As shown in FIG. 14, computer 1420 may include a
processor(s) 1460 that communicates with a number of peripheral
devices via a bus subsystem 1490. These peripheral devices may
include user output devices 1430, user input devices 1440,
communications interface 1450, and a storage subsystem, such as
random access memory (RAM) 1470 and disk drive 1480.
[0083] User input devices 1430 include all possible types of
devices and mechanisms for inputting information to computer system
1420. These may include a keyboard, a keypad, a touch screen
incorporated into the display, audio input devices such as voice
recognition systems, microphones, and other types of input devices.
In various embodiments, user input devices 1430 are typically
embodied as a computer mouse, a trackball, a track pad, a joystick,
wireless remote, drawing tablet, voice command system, eye tracking
system, and the like. User input devices 1430 typically allow a
user to select objects, icons, text and the like that appear on the
monitor 1410 via a command such as a click of a button or the
like.
[0084] User output devices 1440 include all possible types of
devices and mechanisms for outputting information from computer
1420. These may include a display (e.g., monitor 1410), non-visual
displays such as audio output devices, etc.
[0085] Communications interface 1450 provides an interface to other
communication networks and devices. Communications interface 1450
may serve as an interface for receiving data from and transmitting
data to other systems. Embodiments of communications interface 1450
typically include an Ethernet card, a modem (telephone, satellite,
cable, ISDN), (asynchronous) digital subscriber line (DSL) unit,
FireWire interface, USB interface, and the like. For example,
communications interface 1450 may be coupled to a computer network,
to a FireWire bus, or the like. In other embodiments,
communications interfaces 1450 may be physically integrated on the
motherboard of computer 1420, and may be a software program, such
as soft DSL, or the like.
[0086] In various embodiments, computer system 1400 may also
include software that enables communications over a network such as
the HTTP, TCP/IP, RTP/RTSP protocols, and the like. In alternative
embodiments of the present invention, other communications software
and transfer protocols may also be used, for example IPX, UDP or
the like.
[0087] In some embodiment, computer 1420 includes one or more Xeon
microprocessors from Intel as processor(s) 1460. Further, one
embodiment, computer 1420 includes a UNIX-based operating
system.
[0088] RAM 1470 and disk drive 1480 are examples of tangible media
configured to store data such as embodiments of the present
invention, including executable computer code, human readable code,
or the like. Other types of tangible media include floppy disks,
removable hard disks, optical storage media such as CD-ROMS, DVDs
and bar codes, semiconductor memories such as flash memories,
read-only-memories (ROMS), battery-backed volatile memories,
networked storage devices, and the like. RAM 1470 and disk drive
1480 may be configured to store the basic programming and data
constructs that provide the functionality of the present
invention.
[0089] Software code modules and instructions that provide the
functionality of the present invention may be stored in RAM 1470
and disk drive 1480. These software modules may be executed by
processor(s) 1460. RAM 1470 and disk drive 1480 may also provide a
repository for storing data used in accordance with the present
invention.
[0090] RAM 1470 and disk drive 1480 may include a number of
memories including a main random access memory (RAM) for storage of
instructions and data during program execution and a read only
memory (ROM) in which fixed instructions are stored. The
instructions may be readable by the processor(s) 1460 and may, when
executed, cause the computer to perform the various actions
described in the embodiments discussed herein. RAM 1470 and disk
drive 1480 may include a file storage subsystem providing
persistent (non-volatile) storage for program and data files. RAM
1470 and disk drive 1480 may also include removable storage
systems, such as removable flash memory.
[0091] Bus subsystem 1490 provides a mechanism for letting the
various components and subsystems of computer 1420 communicate with
each other as intended. Although bus subsystem 1490 is shown
schematically as a single bus, alternative embodiments of the bus
subsystem may utilize multiple busses.
[0092] FIG. 14 is representative of a computer system capable of
embodying the present invention. It will be readily apparent to one
of ordinary skill in the art that many other hardware and software
configurations are suitable for use with the present invention. For
example, the computer may be a desktop, portable, rack-mounted or
tablet configuration. Additionally, the computer may be a series of
networked computers. Further, the use of other microprocessors are
contemplated, such as Pentium.TM. or Itanium.TM. microprocessors;
Opteron.TM. or AthlonXP.TM. microprocessors from Advanced Micro
Devices, Inc; and the like. Further, other types of operating
systems are contemplated, such as Windows.RTM., WindowsXP.RTM.,
WindowsNT.RTM., or the like from Microsoft Corporation, Solaris
from Sun Microsystems, LINUX, UNIX, and the like. In still other
embodiments, the techniques described above may be implemented upon
a chip or an auxiliary processing board.
[0093] Various embodiments of the present invention can be
implemented in the form of logic in software or hardware or a
combination of both. The logic may be stored in a computer readable
or machine-readable storage medium as a set of instructions adapted
to direct a processor of a computer system to perform a set of
steps disclosed in embodiments of the present invention. The logic
may form part of a computer program product adapted to direct an
information-processing device to perform a set of steps disclosed
in embodiments of the present invention. Based on the disclosure
and teachings provided herein, a person of ordinary skill in the
art will appreciate other ways and/or methods to implement the
present invention.
[0094] The specification and drawings are, accordingly, to be
regarded in an illustrative rather than a restrictive sense.
However, it will be evident that various modifications and changes
may be made thereunto without departing from the broader spirit and
scope of the invention as set forth in the claims. In addition, the
technique and system of the present invention is suitable for use
with a wide variety of EDA tools and methodologies for designing,
testing, and/or manufacturing integrated circuits or other
electronic devices. The scope of the invention should, therefore,
be determined not with reference to the above description, but
instead should be determined with reference to the pending claims
along with their full scope or equivalents.
* * * * *