loadpatents
Patent applications and USPTO patent grants for Synopsys Taiwan Co., Ltd..The latest application filed is for "spine routing and pin grouping with multiple main spines".
Patent | Date |
---|---|
Method and apparatus for transaction recording and visualization Grant 10,068,040 - Chen , et al. September 4, 2 | 2018-09-04 |
IR-aware sneak routing Grant 9,881,118 - Chiu , et al. January 30, 2 | 2018-01-30 |
Manipulating parameterized cell devices in a custom layout design Grant 9,852,251 - Lu , et al. December 26, 2 | 2017-12-26 |
Spine Routing And Pin Grouping With Multiple Main Spines App 20170316143 - Lu; Chien-Hung ;   et al. | 2017-11-02 |
Prototype and emulation system for multiple custom prototype boards Grant 9,449,138 - Chang , et al. September 20, 2 | 2016-09-20 |
Systems and methods for increasing debugging visibility of prototyping systems Grant 9,384,313 - Chiu , et al. July 5, 2 | 2016-07-05 |
Method And Apparatus For Transaction Recording And Visualization App 20160110484 - CHEN; Yung Chuan ;   et al. | 2016-04-21 |
Switch cell Grant 9,311,441 - Liu , et al. April 12, 2 | 2016-04-12 |
P-cell caching Grant 9,305,127 - Chen , et al. April 5, 2 | 2016-04-05 |
Method of fast analog layout migration Grant 9,286,433 - Chen , et al. March 15, 2 | 2016-03-15 |
Knowledge-based analog layout generator Grant 9,256,706 - Chen , et al. February 9, 2 | 2016-02-09 |
Systems And Methods For Increasing Debugging Visibility Of Prototyping Systems App 20150294055 - Chiu; Hung Chun ;   et al. | 2015-10-15 |
Ir-aware Sneak Routing App 20150278421 - CHIU; HSIEN-SHIH ;   et al. | 2015-10-01 |
Method and apparatus for transaction recording and visualization Grant 9,081,924 - Chen , et al. July 14, 2 | 2015-07-14 |
Method For Wire Widening In Circuit Routing System App 20150178441 - CHIU; HSIEN-SHIH ;   et al. | 2015-06-25 |
What-if simulation methods and systems Grant 9,053,264 - Yen , et al. June 9, 2 | 2015-06-09 |
Switch Cell App 20150143322 - Liu; Jui-Hsiang ;   et al. | 2015-05-21 |
P-cell Caching App 20150143310 - Chen; Wei-Cheng ;   et al. | 2015-05-21 |
Spine Routing With Multiple Main Spines App 20150100938 - Lu; Chien-Hung ;   et al. | 2015-04-09 |
Multiple level spine routing Grant 9,003,350 - Chang , et al. April 7, 2 | 2015-04-07 |
Separation And Minimum Wire Length Constrained Maze Routing Method And System App 20150089465 - Chang; Fong-Yuan ;   et al. | 2015-03-26 |
Gateway model routing with slits on wires Grant 8,990,756 - Wang , et al. March 24, 2 | 2015-03-24 |
Knowledge-based Analog Layout Generator App 20150067626 - CHEN; Tung-Chieh ;   et al. | 2015-03-05 |
Efficient Analog Layout Prototyping By Layout Reuse With Routing Preservation App 20150067632 - CHEN; Tung-Chieh ;   et al. | 2015-03-05 |
Multiple level spine routing Grant 8,959,473 - Chang , et al. February 17, 2 | 2015-02-17 |
Hierarchical power map for low power design Grant 8,943,452 - Hsu , et al. January 27, 2 | 2015-01-27 |
Systems And Methods For Designing And Making Integrated Circuits With Consideration Of Wiring Demand Ration App 20150007123 - Chang; Fong-Yuan ;   et al. | 2015-01-01 |
Method of recording and replaying call frames for a test bench Grant 8,924,912 - Ho , et al. December 30, 2 | 2014-12-30 |
Method of recording and replaying call frames for a test bench Grant 08924912 - | 2014-12-30 |
Prototype And Emulation System For Multiple Custom Prototype Boards App 20140351777 - Chang; Yingtsai ;   et al. | 2014-11-27 |
Method of schematic driven layout creation Grant 8,893,069 - Su , et al. November 18, 2 | 2014-11-18 |
Systems and methods for designing and making integrated circuits with consideration of wiring demand ratio Grant 8,875,081 - Chang , et al. October 28, 2 | 2014-10-28 |
Parameterized cell layout generation guided by a design rule checker Grant 8,869,084 - Chung , et al. October 21, 2 | 2014-10-21 |
Prototype and emulation system for multiple custom prototype boards Grant 8,839,179 - Chang , et al. September 16, 2 | 2014-09-16 |
Method for detecting and debugging design errors in low power IC design Grant 8,832,615 - Hsieh , et al. September 9, 2 | 2014-09-09 |
Compact routing Grant 8,832,632 - Chang , et al. September 9, 2 | 2014-09-09 |
Methods for generating device layouts by combining an automated device layout generator with a script Grant 8,789,008 - Chen , et al. July 22, 2 | 2014-07-22 |
Multiple level spine routing Grant 8,782,588 - Chang , et al. July 15, 2 | 2014-07-15 |
Method Of Recording And Replaying Call Frames For A Test Bench App 20140165023 - Ho; Chia-Ling ;   et al. | 2014-06-12 |
Systems and methods for increasing debugging visibility of prototyping systems Grant 8,739,089 - Chiu , et al. May 27, 2 | 2014-05-27 |
Gateway Model Routing with Slits on Wires App 20140143747 - Wang; Hsin-Po ;   et al. | 2014-05-22 |
Method and apparatus for versatile controllability and observability in prototype system Grant 8,732,650 - Chang , et al. May 20, 2 | 2014-05-20 |
Method and apparatus for turning custom prototype boards into co-simulation, co-emulation systems Grant 8,719,762 - Chang , et al. May 6, 2 | 2014-05-06 |
Multiple level spine routing Grant 8,683,417 - Chang , et al. March 25, 2 | 2014-03-25 |
Method of Fast Analog Layout Migration App 20140075402 - Chen; Tung-Chieh ;   et al. | 2014-03-13 |
Viewing and debugging HDL designs having SystemVerilog interface constructs Grant 8,671,383 - Hsu , et al. March 11, 2 | 2014-03-11 |
Hierarchical Power Map For Low Power Design App 20140013293 - Hsu; Chih-Neng ;   et al. | 2014-01-09 |
Method of fast analog layout migration Grant 8,607,182 - Chen , et al. December 10, 2 | 2013-12-10 |
Method For Detecting And Debugging Design Errors In Low Power Ic Design App 20130305207 - Hsieh; Ming Han ;   et al. | 2013-11-14 |
Hierarchical Power Map For Low Power Design App 20130275933 - Hsu; Chih-Neng ;   et al. | 2013-10-17 |
Prototype And Emulation System For Multiple Custom Prototype Boards App 20130227509 - Chang; Yingtsai ;   et al. | 2013-08-29 |
Method And Apparatus For Turning Custom Prototype Boards Into Co-simulation, Co-emulation Systems App 20130117007 - Chang; Yingtsai ;   et al. | 2013-05-09 |
uspto.report is an independent third-party trademark research tool that is not affiliated, endorsed, or sponsored by the United States Patent and Trademark Office (USPTO) or any other governmental organization. The information provided by uspto.report is based on publicly available data at the time of writing and is intended for informational purposes only.
While we strive to provide accurate and up-to-date information, we do not guarantee the accuracy, completeness, reliability, or suitability of the information displayed on this site. The use of this site is at your own risk. Any reliance you place on such information is therefore strictly at your own risk.
All official trademark data, including owner information, should be verified by visiting the official USPTO website at www.uspto.gov. This site is not intended to replace professional legal advice and should not be used as a substitute for consulting with a legal professional who is knowledgeable about trademark law.