U.S. patent application number 14/311496 was filed with the patent office on 2014-12-25 for photonic integrated circuit and fabrication process.
The applicant listed for this patent is STMicroelectronics (Crolles 2) SAS, STMicroelectronics SA. Invention is credited to Alain Chantre, Sebastien Cremer.
Application Number | 20140376857 14/311496 |
Document ID | / |
Family ID | 48906425 |
Filed Date | 2014-12-25 |
United States Patent
Application |
20140376857 |
Kind Code |
A1 |
Chantre; Alain ; et
al. |
December 25, 2014 |
PHOTONIC INTEGRATED CIRCUIT AND FABRICATION PROCESS
Abstract
A photonic integrated circuit may include a silicon layer
including a waveguide and at least one other photonic component.
The photonic integrated circuit may also include a first insulating
region arranged above a first side of the silicon layer and
encapsulating at least one metallization level, a second insulating
region arranged above a second side of the silicon layer and
encapsulating at least one gain medium of a laser source optically
coupled to the waveguide.
Inventors: |
Chantre; Alain; (Seyssins,
FR) ; Cremer; Sebastien; (Sassenage, FR) |
|
Applicant: |
Name |
City |
State |
Country |
Type |
STMicroelectronics SA
STMicroelectronics (Crolles 2) SAS |
Montrouge
Crolles |
|
FR
FR |
|
|
Family ID: |
48906425 |
Appl. No.: |
14/311496 |
Filed: |
June 23, 2014 |
Current U.S.
Class: |
385/14 ;
438/31 |
Current CPC
Class: |
G02B 6/12002 20130101;
H01S 5/1032 20130101; H01S 5/0422 20130101; H01S 2301/176 20130101;
H01S 5/021 20130101; H01S 5/34306 20130101; H01S 5/026 20130101;
G02B 6/12004 20130101; H01S 5/0262 20130101 |
Class at
Publication: |
385/14 ;
438/31 |
International
Class: |
G02B 6/122 20060101
G02B006/122 |
Foreign Application Data
Date |
Code |
Application Number |
Jun 24, 2013 |
FR |
1355991 |
Claims
1-24. (canceled)
25. An integrated circuit comprising: a silicon layer; a waveguide
carried within said silicon layer; at least one other photonic
component carried within said silicon layer; a first insulating
layer above a first side of said silicon layer; at least one
metallization level encapsulated by said first insulating layer; a
second insulating layer above a second side of said silicon layer;
and a laser source optically coupled to said waveguide and
comprising a gain medium encapsulated by said second insulating
layer.
26. The integrated circuit according to claim 25, wherein said
laser source comprises at least one an additional waveguide
optically coupled to said waveguide above the second side of said
silicon layer, and wherein said at least one additional waveguide
is encapsulated by said second insulating layer.
27. The integrated circuit according to claim 26, wherein said gain
medium is adjacent said at least one additional waveguide.
28. The integrated circuit according to claim 26, wherein said gain
medium is spaced apart from said at least one additional waveguide
by a portion of said second insulating having a thickness less than
or equal to 100 nm.
29. The integrated circuit according to claim 25, wherein said
laser source further comprises at least one additional waveguide
above the first side of said silicon layer and optically coupled to
said waveguide; wherein said at least one additional waveguide is
encapsulated by said first insulating layer; and wherein said gain
medium is adjacent the second side of said silicon layer.
30. The integrated circuit according to claim 29, wherein said gain
medium is spaced apart from the second side of said silicon layer
by a distance of 100 nm.
31. The integrated circuit according to claim 25, wherein said
silicon layer comprises a coupler; and wherein said first
insulating layer comprises a metal mirror facing said coupler.
32. The integrated circuit according to claim 31, wherein said
metal mirror is carried within the first arranged in the at least
one metallization level opposite the first side of the silicon
layer.
33. The integrated circuit according to claim 25, further
comprising a grating coupler carried within said silicon layer,
said grating coupler having a relief surface facing said first
insulating layer.
34. The integrated circuit according to claim 25, further
comprising a heat-dissipating radiator carried within said first
insulting layer and coupled to said silicon layer opposite said
gain medium.
35. The integrated circuit according to claim 25, further
comprising a modulator carried within said silicon layer, said
modulator having a relief surface facing said first insulating
layer and another surface opposite the relief surface and facing
said second insulating layer; and wherein said at least one
metallization level is coupled to the relief surface.
36. The integrated circuit according to claim 25, further
comprising a substrate carrying said first insulating layer.
37. The integrated circuit according to claim 35, further
comprising a substrate carrying said first insulating layer; and
wherein said at least one metallization level comprises a shield
configured to shield said modulator from said substrate.
38. An integrated circuit comprising: a semiconductor layer; a
waveguide carried within said semiconductor layer; a first
insulating layer carried by a first side of said semiconductor
layer; at least one metallization level carried within said first
insulating layer; a second insulating layer carried by a second
side of said semiconductor layer; and a laser source optically
coupled to said waveguide and comprising a gain medium carried
within said second insulating layer.
39. The integrated circuit according to claim 38, wherein said
semiconductor layer comprises silicon.
40. The integrated circuit according to claim 38, wherein said
laser source comprises at least one an additional waveguide
optically coupled to said waveguide adjacent the second side of
said semiconductor layer, and wherein said at least one additional
waveguide is carried within said second insulating layer.
41. The integrated circuit according to claim 40, wherein said gain
medium is adjacent said at least one additional waveguide.
42. An integrated circuit comprising: a silicon layer; a modulator
carried within said silicon layer and having first and second
opposing surfaces; a first insulating layer above a first side of
the silicon layer at least one metallization level encapsulated by
said first insulating layer and coupled to the first surface of
said modulator; and a second insulating layer above a second side
of the silicon layer and above the second surface of said
modulator; no other substrate facing the second surface of said
modulator.
43. The integrated circuit according to claim 42, further
comprising a substrate carrying said first insulating layer.
44. An integrated circuit comprising: a substrate; a silicon layer;
a modulator carried within said silicon layer and having a first
surface facing said substrate and a second surface opposite the
first surface; a first insulating layer arranged between a first
side of said silicon layer and said substrate; at least one
metallization level encapsulated by said first insulating layer and
coupled to the first surface of said modulator; and a second
insulating layer arranged above a second side of said silicon layer
and above the second surface of said modulator.
45. The integrated circuit according to claim 44, wherein said at
least one metallization level comprises a shield configured to
shield the modulator from said substrate.
46. A method of making an integrated circuit, comprising: forming a
semiconductor layer above a buried insulating layer, the buried
insulating layer being above a carrier substrate, a waveguide, and
at least one other photonic component; forming, adjacent a first
side of the semiconductor layer, at least one metallization level
within a first insulating layer; removing the carrier substrate and
the buried insulating layer to at least one of expose and be
adjacent a second side of the semiconductor layer opposite the
first side; and forming a laser source optically coupled to the
waveguide, wherein forming the laser source comprises forming at
least the gain medium of the laser source in a second insulating
layer adjacent the second side.
47. The method according to claim 46, wherein forming the
semiconductor layer comprises forming a silicon layer.
48. The method according to claim 46, wherein forming the laser
source comprises: forming, adjacent at least one additional
insulating layer adjacent the second side; forming, adjacent the at
least one additional insulating layer, an etched semiconductor
heterostructure defining said gain medium; and depositing another
insulating layer adjacent the at least one additional insulating
layer and the heterostructure to define the second insulating
layer.
49. The method according to claim 48, wherein forming the laser
source further comprises, prior to forming of the gain medium,
forming, adjacent the second side of the semiconductor layer, at
least one additional waveguide optically coupled to the
waveguide.
50. The method according to claim 49, wherein forming the at least
one additional waveguide comprises: depositing an additional
semiconductor layer adjacent the additional insulating layer;
etching the additional semiconductor layer; and depositing at least
one additional insulating layer above the etched additional
semiconductor layer and the additional insulating layer; the etched
heterostructure being formed above the at least one additional
insulating layer.
51. The method according to claim 46, further comprising, prior to
forming the at least one metallization layer, forming, above the
first side of the semiconductor layer, at least an additional
waveguide optically coupled to the waveguide.
52. The method according to claim 46, further comprising: forming a
coupler in the semiconductor layer; and forming a metal mirror
within the first insulating layer facing the coupler.
53. The method according to claim 52, wherein the metal mirror is
formed while forming tracks of the at least one metallization
level.
Description
FIELD OF THE INVENTION
[0001] The present invention relates to integrated circuits, and
more particularly to photonic integrated circuits, i.e. those
incorporating one or more photonic components such as, for example,
waveguides, optical modulators, optical couplers, photodetectors,
etc.
BACKGROUND OF THE INVENTION
[0002] Currently, photonic integrated circuits allow the
integration of practically all active or passive optical devices,
such as, for example, coupling structures, waveguides, modulators,
or photodetectors.
[0003] Moreover, another known advantageous component is a hybrid
III-V/Si laser source. Such a laser source includes an amplifying
medium (gain medium) that includes a composite III-V semiconductor
material, a waveguide situated in an underlying silicon layer and
optically coupled to the gain medium, and a cavity resonator
optically coupled to the waveguide and containing Bragg mirrors,
for example. The gain medium emits light when it is excited by
electrical energy (pumping), and the cavity resonator is intended,
in cooperation with the gain medium, to amplify this light so as to
deliver the laser beam.
[0004] Depending on the type of laser (DBR: Distributed Bragg
Reflector or DFB: Distributed Feedback laser), the Bragg mirrors
are situated in the silicon at the periphery of the gain medium or
else under the gain medium.
[0005] Such a hybrid laser source may require a very short
distance, typically not more than a hundred nanometers, between the
gain medium and the underlying silicon waveguide. Moreover, direct
bonding of the gain medium to a waveguide of silicon-on-insulator
type typically requires a planar surface prepared by a
chemical-mechanical polishing step. Currently, a hybrid III-V laser
source on a silicon substrate can be manufactured on an
experimental basis and in isolation.
[0006] Integrated photonic circuits generally do not incorporate
hybrid III-V/Si laser sources due to the great difficulty of
integrating these sources. This is because direct bonding to the
silicon-on-insulator film cannot be carried out after the complete
production of the integrated circuit, and particularly after the
production of the metallization levels of the interconnect part of
the integrated circuit, widely denoted as the Back End Of Line
(BEOL) part by those skilled in the art.
[0007] Furthermore, conventional production of the metallization
levels (using deposition and chemical-mechanical polishing (CMP) of
dielectrics/metals) cannot be carried out after any steps of
integration of the laser source due to the substantial height of
the laser source, typically about 3 microns. As a result hybrid
III-V laser sources may therefore be incompatible with integration
into integrated circuits. Therefore, the approach currently used to
associate a laser source with an integrated circuit includes, after
the integrated circuit and its interconnect (BEOL) part have been
produced, fixing an already assembled laser source to one of the
sides of the chip.
SUMMARY OF THE INVENTION
[0008] According to one aspect, a photonic integrated circuit that
effectively integrates a hybrid laser source while being compatible
with the conventional steps of fabrication of an integrated
circuit, particularly the fabrication of the metallization levels,
is provided. In particular, it may be possible to achieve such
integration by carrying out a treatment of the back-side of the
semiconductor wafer, leading to back-side integration of the laser
source, whereas the metallization levels (BEOL part of the
integrated circuit) are arranged on the front side.
[0009] According to one aspect, a photonic integrated circuit may
include a silicon layer that includes a waveguide and at least one
other electronic component, for example, an optical coupler, a
modulator, or a photodetector. The photonic integrated circuit may
also include a first insulating region arranged above a first side,
for example the front side, of the silicon layer and encapsulating
at least one metallization level, and typically several
metallization levels. A second insulating region may be arranged
above a second side, for example the back side, of the silicon
layer and encapsulating at least the gain medium of a laser source
optically coupled to the waveguide.
[0010] The cavity resonator of the laser source may include Bragg
mirrors, for example. When the silicon layer is thick enough, the
cavity resonator, typically the Bragg mirrors, and the waveguide
may be produced inside the silicon layer. However, in some
applications, it may be preferable for the silicon layer not to be
too thick, i.e. typically less than or equal to 300 nanometers in
thickness, so as not to compromise the operational efficiency of
the other photonic components. Furthermore, in such a
configuration, either the laser is a DBR laser and an additional
waveguide is then advantageously arranged above the second side of
the silicon layer, and the second insulating region then also
encapsulates this additional waveguide, or the laser is a DFB laser
and an additional waveguide as well as the Bragg mirrors of the
cavity resonator are then advantageously arranged above the second
side of the silicon layer, and the second insulating region then
also encapsulates this additional waveguide, as well as the Bragg
mirrors.
[0011] The gain medium of the laser source is then advantageously
situated in the immediate vicinity of this additional means or
additional waveguide and possible cavity resonator, for example
separated from this additional means by part of the second
insulating region having a thickness less than or equal to 100
nanometers.
[0012] As a variant, the additional means, or additional waveguide
and possible cavity resonator, can be arranged not above the second
side of the silicon layer, but above the first side of this silicon
layer. The first insulating region then also encapsulates the
additional means. The gain medium of the laser source is then
situated in the immediate vicinity of the second side of the
silicon layer, for example separated from this second side by an
insulating layer, commonly denoted PADOX by those skilled in the
art, possibly having a thickness about one hundred nanometers.
[0013] The silicon layer may also incorporate a coupler, and the
first insulating region may incorporate a metal mirror arranged
facing the coupler. The coupler will then, for example, send part
of the laser beam emitted by the laser source back across the
second insulating region and another part in the direction of the
metal mirror, which will reflect it towards the second insulating
region. In this way interference with the various insulating
layers, in particular the nitride layers of the first insulating
region is reduced, and losses in the substrate, which
conventionally occur for a coupler produced on an
silicon-on-insulator (SOI) substrate, are also reduced.
[0014] This feature, i.e. a metal mirror incorporated into the
first insulating region and arranged facing a coupler, can be
considered independently of the presence of a laser source
integrated into the integrated circuit as defined above. The metal
mirror is advantageously arranged in a first metallization level
situated opposite the first side of the silicon layer. The coupler,
incorporated into the silicon layer, can be a grating coupler
possessing a relief surface turned towards the first insulating
region.
[0015] According to another aspect, a method of fabrication of a
photonic integrated circuit is provided. The method includes
producing, inside a silicon layer arranged above a buried
insulating layer arranged above a carrier substrate, a waveguide
and at least one other photonic component. The method also includes
producing, above a first side of the silicon layer, at least one
metallization level encapsulated in a first insulating region, and
removing the carrier substrate and the buried insulating layer so
as to uncover or approach a second side of the silicon layer,
opposite the first side.
[0016] The method also includes making a laser source optically
coupled to the waveguide. Making the laser source includes
encapsulating at least the gain medium of this laser source in a
second insulating region situated above the second side.
[0017] According to one embodiment, the production of the laser
source includes forming an etched heterostructure above at least
one additional insulating layer itself situated above the second
side. The etched heterostructure may form the gain medium. Another
insulating layer may be deposited above the at least one additional
insulating layer and the heterostructure so as to form the second
insulating layer.
[0018] According to a first variant, the production of the laser
source may include, prior to the formation of the gain medium,
forming, above the second side of the silicon layer, an additional
means or at least one additional waveguide optically coupled to the
waveguide. According to one embodiment of this variant, the
formation of the additional means may include depositing an
additional silicon layer above the additional insulating layer, at
least one etching of the additional silicon layer, and depositing
at least one additional insulating layer above the etched
additional silicon layer and the additional insulating layer. The
heterostructure may be formed above the at least one additional
insulating layer.
[0019] According to another variant, the method may include prior
to production of the metallization level or levels, forming, above
the first side of the silicon layer, an additional means or at
least one additional waveguide optically coupled to the waveguide.
According to one embodiment, which can be considered independently
of the production of the laser layer, the method may furthermore
include producing, in the silicon layer, a coupler and producing a
metal mirror encapsulated in the first insulating region facing the
coupler. The mirror may advantageously be produced during the
production of the tracks of a first metallization level.
BRIEF DESCRIPTION OF THE DRAWINGS
[0020] FIG. 1 is a schematic cross-sectional view of a photonic
integrated structure preparatory to obtaining of a photonic
integrated circuit in accordance with an embodiment of the present
invention.
[0021] FIG. 2 is a schematic cross-sectional view of the photonic
integrated structure of FIG. 1 after bonding of a handle
substrate.
[0022] FIG. 3 is a schematic cross-sectional view of the photonic
integrated structure of FIG. 2 after removal of the carrier
substrate of said structure.
[0023] FIG. 4 is a schematic cross-sectional view of the photonic
integrated structure of FIG. 3 after etching of the insulating
layer.
[0024] FIG. 5 is a schematic cross-sectional view of the photonic
integrated structure of FIG. 4 including an additional waveguide
above the waveguide.
[0025] FIG. 6 is a schematic cross-sectional view of the photonic
integrated structure of FIG. 5 after III-V wafer bonding.
[0026] FIG. 7 is a schematic cross-sectional view of the photonic
integrated structure of FIG. 6 after selective chemical etching of
the substrate of the wafer and III-V laser patterning and
etching.
[0027] FIG. 8 is a schematic cross-sectional view of a photonic
integrated circuit in accordance with an embodiment of the present
invention.
[0028] FIG. 9 is a schematic cross-sectional view of a photonic
integrated circuit in accordance with another embodiment of the
present invention.
[0029] FIG. 10 is a schematic cross-sectional view of an integrated
circuit in accordance with the prior art.
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS
[0030] In FIG. 1, the reference SB denotes a Silicon-On-Insulator
(SOI) wafer. The SOI substrate includes a silicon layer or film 1
having, in this embodiment, a thickness of about 300 nanometers,
arranged above a buried insulating layer 2, commonly denoted BOX
(Buried Oxide) by those skilled in the art. This buried insulating
layer 2 is itself arranged above a carrier substrate 3.
[0031] Various photonic components are produced in this silicon
layer 1, for example, a waveguide GO arranged in a part 10 of this
layer, a grating coupler 11, another waveguide 12, a modulator 13
and a photodetector 14.
[0032] Although any kind of optical modulator may be used, the
modulator 13 may be an electro-optical modulator, for example a
Mach-Zehnder modulator having an architecture well known by the man
skilled in the art and including a phase shifter (also called phase
modulator) in each of the two branches of the Mach-Zehnder
modulator, both phase shifters being controlled in phase
opposition. For simplicity reasons only one of those phase shifters
of the modulator 13 is illustrated in the figures.
[0033] Of course, FIG. 1 shows a variety of photonic components
that can be produced in the silicon layer without this list being
exhaustive. Of course, it may be possible for only some of these
components to be produced, depending on the desired applications.
These various photonic components are mutually separated by an
insulating region 100, silicon dioxide for example.
[0034] It should be noted that if the laser source to be produced
is a DBR laser, the part 10 of the silicon layer also incorporates
Bragg mirrors optically coupled to the waveguide GO and which are
to be situated on the periphery of the III-V gain medium of the
laser source.
[0035] This silicon layer 1 has a first side F1, or front side, and
a second side F2 or back side, that is arranged above the buried
insulating layer 2. In a conventional way known per se, the process
for producing each photonic integrated circuit of the wafer
includes producing several metallization levels, here four levels
M1, M2, M3, M4 embedded in a first insulating region 4. The
insulating material forming this first insulating region is
commonly denoted as the intermetal dielectric (IMD) by those
skilled in the art. This production may be conventionally based on
deposition and chemical-mechanical polishing (CMP) of dielectrics
(oxide) and metals (copper).
[0036] The tracks produced in these metallization layers can, at
least in some cases, be connected by vias V. These metallization
levels are typically used to interconnect components and to connect
them to external contact pads. The height of the interconnect
region RITX is typically about 3 microns.
[0037] Simultaneously with the production of the tracks of the
first metallization level M1, a metal mirror 5 may be
advantageously produced opposite the relief surface of the grating
coupler 11. Next, a substrate 6 acting as a handle is bonded (FIG.
2) to the upper side of the insulating region 4.
[0038] After the structure has been flipped, the carrier substrate
3 is removed, as illustrated in FIG. 3, typically by grinding. As
illustrated in FIG. 4, the insulating (BOX) layer 2 is etched to
uncover the second side F2 of the silicon layer, i.e. the back
side. It is from this back side that the processing for producing
the laser source will be carried out.
[0039] This being so, generally, no processing is carried out on
bare silicon. This is the reason why, before carrying out further
processing, the silicon layer is covered with an additional
insulating layer 70, commonly denoted the PADOX by those skilled in
the art.
[0040] As a variant, when the buried insulating layer 2 includes a
stack that includes a PADOX layer topped by a silicon layer nitride
topped by a layer of TEOS oxide, the etching of the layer 2 is
carried out as far as the PADOX layer 70, which may make it
possible to avoid consuming the silicon dioxide of the regions 100.
In this case, the side F2 of the silicon layer is approached and
thus it may not be desirable to reform the PADOX layer 70. The
thickness of this PADOX layer is typically about 100
nanometers.
[0041] Next, as illustrated in FIG. 5, an additional waveguide 71
is produced above the waveguide GO of the interconnect part 10.
This waveguide 71 may be for the future laser source that is here
assumed to be a DFB laser.
[0042] In this respect, wafer-scale deposition of an amorphous
silicon layer is carried out on the additional insulating layer 70,
which layer is etched so as to form the additional waveguide 71. In
the event of the future laser source being a DFB laser, the
additional means 71 or additional waveguide also incorporate Bragg
mirrors optically coupled to the additional waveguide to contribute
to the formation of the cavity resonator. In this respect, a double
etching of the amorphous silicon layer is carried out to form the
additional waveguide, then the Bragg mirrors.
[0043] Next, an additional insulating layer 72, for example made of
silicon dioxide, is deposited on the additional means 71 and on the
additional insulating layer 70 (PADOX), and a chemical-mechanical
polishing is then carried out on the additional insulating layer
72. The thickness of the additional means 71 is typically about 200
nanometers, whereas the thickness of the additional insulating
layer 72 is less than or equal to 100 nanometers.
[0044] The stack 7 thus produced and having been polished, is thus
ready to receive the active gain medium that amplifies the laser
source. Thus, as illustrated in FIG. 6, a heterostructure 8 made of
III-V semiconductor material is formed. This formation is carried
out by direct bonding of a wafer 8 formed by a III-V
heterostructure.
[0045] More precisely, the heterostructure 8 includes a substrate
80 that includes a p-type semiconductor material, InP for example,
a stack 81 of layers forming quantum wells, made of InGaAsP for
example, and a layer 82 of an n-type material, for example an
InP/InGaAs stack.
[0046] The thickness of the heterostructure 8 may typically be
about a few hundred microns. The thickness of the stack of quantum
wells 81 may be about 300 nm and the thickness of the layer 82 may
be about 200 nm.
[0047] As illustrated in FIG. 7, selective chemical etching of the
substrate 80 (selective over the active layers 81 and 82) is
carried out, followed by lithography and etching adapted to the
III-V material to obtain the gain medium 800 of the laser source.
Next eutectic deposits 801, 802, 803, based on gold for example,
are deposited to allow metal contacts to be made to the etched
layer 820 and to the etched layer 830.
[0048] As illustrated in FIG. 8, the structure is encapsulated by
depositing another insulating layer above the stack 7 to form a
second insulating region 9 above the structure 800 and the stack 7.
Conventional production of contacts 910 is carried out to make
contact with the eutectic zones 801, 802 and 803, as well as
conventional production of other contacts 903 to connect metal
tracks to contact pads situated on the back side.
[0049] After the steps of finishing and cutting the wafer to
singulate the integrated circuits, a photonic integrated circuit IC
is obtained, as illustrated in FIG. 8. The integrated circuit
includes a silicon layer 1 that includes a waveguide GO and at
least one other photonic component and a first insulating region 4
arranged above a first side F1 of the silicon layer and
encapsulating here several metallization levels M1-M4. The
integrated circuit also includes a second insulating region 9 above
a second side F2 of the silicon layer and encapsulating the gain
medium 800 of the laser source SL and, in this embodiment, an
additional means 71 or at least one additional waveguide, and
possibly also Bragg mirrors. This laser source is optically coupled
to the waveguide GO which is situated in part 10 of the silicon
layer 1.
[0050] As a variant, as illustrated in FIG. 9, it may be possible
to arrange the additional means 71 of the laser source in the first
insulating region 4. The gain medium 800 of the laser source SL is
then arranged in the immediate vicinity of the silicon layer 1 and
is separated from the second side F2 of the latter by the
additional insulating layer 70 (PADOX). In this respect, the
additional means 71 are produced prior to the production of the
metallization levels M1-M4 of the integrated circuit, again by
wafer-scale deposition of a layer of amorphous silicon and
etching(s).
[0051] It should also be noted that, whether in the embodiment of
FIG. 8 or the embodiment of FIG. 9, the grating coupler 11 turns
its relief surface 110 towards the first insulating region 4 in the
direction of the metal mirror 5. The light beam that arrives on the
coupler via the silicon layer is subdivided in the coupler 11 into
a first beam that crosses the insulating region 9 towards an
optical fiber fixed onto the back side FAR of the chip for example,
and into a second beam that travels towards the metal mirror 5 to
be reflected in the direction of the optical fiber. Thus, none of
these beams may be perturbed by the nitride layers that are, for
example, found in the first insulating region 4. The production of
a metal mirror 5 in the first insulating region 4 is generally
independent of the integration (or absence of integration) of a
hybrid III-V laser source in the IC chip.
[0052] Thus, according to another aspect, a photonic integrated
circuit is provided that includes a silicon layer that includes at
least one coupler 11, for example a grating coupler, and a first
insulating region 4 arranged above a first side F1 of the silicon
layer 1 and encapsulating one or more metallization levels. A metal
mirror is situated facing the coupler, for example a first
metallization layer, and a second insulating layer 9 is situated
above a second side F2 of the silicon layer 1, opposite the first
side.
[0053] The advantages of such a structure in relation to a
prior-art structure, as illustrated in FIG. 10, are now described.
In the prior-art structure equipped, for example, with an optical
fiber fixed to its front side FAV, when a light beam reaches the
coupler 11, it is subdivided into a first beam that crosses the
insulating region 4 towards the optical fiber, and into a second
beam that moves towards the substrate 3. Thus, there is a loss in
the substrate and a perturbation of the first beam by the nitride
layers of the first insulating region.
[0054] Thus, according to this other aspect, losses in the
substrate and perturbations by the nitride layers as indicated
above, are reduced or avoided. It may also be possible, as
illustrated in FIG. 9, to incorporate, into the first insulating
region 4, a means 150 or a heat-dissipating radiator connected to
the silicon layer 1, opposite the gain medium of the laser source.
This means or heat-dissipating radiator may be produced by metal
tracks and specific vias simultaneously with the production of the
metal tracks of the various metallization levels of the
interconnect (BEOL) part of the integrated circuit.
[0055] Of course this heat-dissipating radiator can also be
provided in the embodiment in FIG. 8. Also, the heat-dissipating
radiator may improve the heat dissipation of the integrated
circuit.
[0056] As indicated above and illustrated in particular in FIG. 8
or 9, the photonic integrated circuit includes as a photonic
component, a modulator 13. As indicated above, although any kind of
optical modulator may be used, the modulator illustrated is, for
example, a Mach-Zehnder modulator having a structure well-known by
the man skilled in the art. Only one phase shifter of the
Mach-Zehnder modulator is represented for ease of
understanding.
[0057] In integrated circuits of the prior art, such as the one
illustrated in FIG. 10, having an SOI substrate including the
silicon layer or film 1 arranged above the buried insulating layer
(BOX) 2 itself arranged above the carrier substrate 3, the
modulator 13 is above the carrier substrate. However such a prior
structure has drawbacks.
[0058] As a matter of fact if the carrier substrate is a small
resistivity (SR) substrate, some resistive and capacitive (RC)
parasitic effects occur between the silicon film and the carrier
substrate leading to a speed limitation and an increase of power
consumption.
[0059] It may be possible to avoid such drawbacks by using a high
resistivity (HR) substrate as the carrier substrate. However using
such HR-SOI substrates may be relative costly and may lead to
processing issues.
[0060] The fabrication method described above leads, with reference
to FIGS. 1-9, to a photonic integrated circuit that includes a
modulator 13 having, as illustrated in FIG. 8 or 9, without a
carrier substrate above the modulator after the structure has been
flipped and the carrier substrate 3 removed, as illustrated in FIG.
3, typically by grinding.
[0061] Thus RC parasitic effects are greatly reduced while HR-SOI
substrates are no longer needed. For example, a parasitic capacitor
reduction of 50% may be obtained versus a prior art structure based
on an SR-SOI substrate, and a parasitic capacitor reduction of 33%
may be obtained versus a prior art structure based on an HR-SOI
substrate.
[0062] Thus according to another embodiment illustrated in FIG. 8
or 9, a photonic integrated circuit is also proposed, that includes
a silicon layer 1 that includes a modulator 13 having a relief
surface and another surface opposite the relief surface, a first
insulating region 4 arranged above a first side F1 of the silicon
layer and encapsulating at least one metallization level M1-M4
coupled to the relief surface of the modulator, a second insulating
region 9 arranged above a second side F2 of the silicon layer and
above the another surface of the modulator, and no other substrate
turned towards the another surface of the modulator.
[0063] As illustrated also in FIG. 8 or 9, a photonic integrated
circuit is also proposed that includes a substrate (for example the
handle substrate 6), a silicon layer 1 including a modulator 13
having a relief surface turned towards the substrate and another
surface opposite said relief surface, a first insulating region 4
arranged between a first side F1 of the silicon layer and the
substrate and encapsulating at least one metallization level M1-M4
coupled to the relief surface of the modulator, and a second
insulating region 9 arranged above a second side F2 of the silicon
layer and above the another surface of the modulator.
[0064] Further at least one metallization level M1-M4 may be
advantageously used for forming a shield for shielding the
modulator from said handle substrate. Of course the integrated
circuit may include such a modulator with or without the other
photonic components, such as the laser source.
* * * * *