U.S. patent application number 13/920226 was filed with the patent office on 2014-12-18 for nanochannel process and structure for bio-detection.
The applicant listed for this patent is International Business Machines Corporation. Invention is credited to Jingwei Bai, Evan G. Colgan, Christopher V. Jahnes, Stanislav Polonsky.
Application Number | 20140367749 13/920226 |
Document ID | / |
Family ID | 51948354 |
Filed Date | 2014-12-18 |
United States Patent
Application |
20140367749 |
Kind Code |
A1 |
Bai; Jingwei ; et
al. |
December 18, 2014 |
NANOCHANNEL PROCESS AND STRUCTURE FOR BIO-DETECTION
Abstract
Nanochannel sensors and methods for constructing nanochannel
sensors. An example method includes forming a sacrificial line on
an insulating layer, forming a dielectric layer, etching a pair of
electrode trenches, forming a pair of electrodes, and removing the
sacrificial line to form a nanochannel. The dielectric layer may be
formed on insulating layer and around the sacrificial line. The
pair of electrode trenches may be etched in the dielectric layer on
opposite sides of the sacrificial line. The pair of electrodes may
be formed by filling the electrode trenches with electrode
material. The sacrificial line may be removed by forming a
nanochannel between the at least one pair of electrodes.
Inventors: |
Bai; Jingwei; (Elmsford,
NY) ; Colgan; Evan G.; (Chestnut Ridge, NY) ;
Jahnes; Christopher V.; (Upper Saddle River, NJ) ;
Polonsky; Stanislav; (Putnam Valley, NY) |
|
Applicant: |
Name |
City |
State |
Country |
Type |
International Business Machines Corporation |
Armonk |
NY |
US |
|
|
Family ID: |
51948354 |
Appl. No.: |
13/920226 |
Filed: |
June 18, 2013 |
Current U.S.
Class: |
257/253 |
Current CPC
Class: |
G01N 27/403 20130101;
H01L 29/40114 20190801; H01L 21/823871 20130101; H01L 21/283
20130101; H01L 29/401 20130101; G01N 27/4148 20130101 |
Class at
Publication: |
257/253 |
International
Class: |
G01N 27/414 20060101
G01N027/414 |
Claims
1. A nanochannel sensor comprising: a substrate; a dielectric layer
over the substrate; a nanochannel in the dielectric layer; a feed
channel in the dielectric layer, the feed channel including a
bottom portion and a top portion, wherein the top portion has a
greater cross-sectional width than the bottom portion; and a pair
of electrodes positioned on opposing sides of the nanochannel.
2. The nanochannel sensor of claim 1, wherein the dielectric layer
contains silicon dioxide.
3. The nanochannel sensor of claim 1, further comprising a capping
layer over the dielectric layer, and wherein the capping layer
defines a plurality of openings leading to one of at least one of
the nanochannel and the feed channel.
4. The nanochannel sensor of claim 3, further comprising a
conformal layer between the nanochannel and the electrodes, wherein
the conformal layer has high dielectric constant.
5. The nanochannel sensor of claim 4, wherein the nanochannel
sensor is integrated with a complementary metal oxide conductor
(CMOS) chip.
6. The nanochannel sensor of claim 5, wherein the conformal layer
contains at least one of aluminum oxide and hafnium oxide.
7. A nanochannel sensor comprising: a substrate; a dielectric layer
over the substrate; a feed channel in the dielectric layer; a
nanochannel in the dielectric layer; a capping layer over the
dielectric layer, the feed channel, and the nanochannel, the
capping layer defining a plurality of openings leading to one of at
least one of the nanochannel and the feed channel.
8. The nanochannel sensor of claim 7, wherein the feed channel
includes a bottom portion and a top portion, and the top portion
has a greater cross-sectional width than the bottom portion.
9. The nanochannel sensor claim 8, wherein the top portion of the
feed channel has a smaller cross-sectional height than the bottom
portion of the feed channel.
10. The nanochannel sensor of claim 7, wherein the nanochannel
sensor is integrated with a complementary metal oxide conductor
(CMOS) chip.
11. The nanochannel sensor of claim 10, wherein the nanochannel
sensor is integrated with the back end of line (BEOL) wiring
layers.
12-20. (canceled)
Description
BACKGROUND
[0001] This invention relates to molecular sensors, and more
particularly to nanochannel sensors and methods for constructing
nanochannel sensors.
[0002] Biosensors may be constructed by integrating nanochannels
into complementary metal-oxide-semiconductor (CMOS) chips. These
nanochannels may exhibit diameters of a few microns for cell and
bacteria sensing. They may also range from tens of nanometers to a
fraction of a nanometer in diameter for virus and biological
macromolecule sensing.
[0003] Pairs of electrodes may line biosensor nanochannels and may
be used to detect such objects as cells, cell fragments, bacteria,
viruses and biological macromolecules in the nanochannels. The
electrodes detect the objects in the solutions flowing within the
nanochannels. The electrode pairs may also be used to generate
electric fields in and around nanochannels. The electric fields may
be used to manipulate charged objects in the solution within the
nanochannels, for example aligning molecules with the length of the
nanochannel, holding molecules in places, or moving molecules along
the nanochannels.
BRIEF SUMMARY
[0004] Accordingly, one example aspect of the present invention is
a nanochannel sensor which includes a substrate, a dielectric
layer, a nanochannel, a feed channel, and a pair of electrodes. The
dielectric layer may be formed over the substrate. The nanochannel
and the feed channel may be formed in the dielectric layer. The
feed channel may include a bottom portion and a top portion. The
top portion of the feed channel may have a greater cross-sectional
width than the bottom portion of the feed channel. The pair of
electrodes may be positioned on opposing sides of the
nanochannel.
[0005] Another example aspect of the present invention is a
nanochannel sensor which includes a substrate, a dielectric layer,
a nanochannel, a feed channel, a pair of electrodes, and a second
dielectric layer. The first dielectric layer may be formed over the
substrate. The nanochannel and the feed channel may be formed in
the dielectric layer. The pair of electrodes may be positioned on
opposing sides of the nanochannel. The capping layer may cover the
feed channel. The capping layer may also define a plurality of
openings through the second dielectric layer leading to the feed
channel.
[0006] Yet another example aspect of the present invention is a
method of aligning electrodes to a nanochannel sensor including
forming a sacrificial line on an insulating layer, forming a
dielectric layer, etching a pair of electrode trenches, forming a
pair of electrodes, and removing the sacrificial line to form a
nanochannel. The first dielectric layer may be formed on the
substrate and around the sacrificial line. The pair of electrode
trenches may be etched in the first dielectric layer on opposite
sides of the sacrificial line. The pair of electrodes may be formed
by filling the electrode trenches with electrode material. The
sacrificial line may be removed by forming a nanochannel between
the at least one pair of electrodes.
BRIEF DESCRIPTION OF THE DRAWINGS
[0007] The subject matter which is regarded as the invention is
particularly pointed out and distinctly claimed in the claims at
the conclusion of the specification. The foregoing and other
objects, features, and advantages of the invention are apparent
from the following detailed description taken in conjunction with
the accompanying drawings in which:
[0008] FIGS. 1A, 1B, and 1C show a nanochannel sensor in accordance
with one embodiment of the invention.
[0009] FIGS. 2B and 2B show a continuous flow diagram illustrating
a first example method for aligning electrodes to a nanochannel
sensor in accordance with another embodiment of the invention.
[0010] FIGS. 3A and 3B show a continuous flow diagram illustrating
second example method of aligning electrodes to a nanochannel
sensor, in accordance with yet another embodiment of the
invention.
[0011] FIGS. 4A and 4B show a cross-sectional view and a top view,
respectively, of a sacrificial line deposition step, in accordance
with the first example method for aligning electrodes to a
nanochannel sensor.
[0012] FIGS. 5A and 5B show a cross-sectional view and a top view,
respectively, of a dielectric layer formation and planarization
steps, in accordance with the first example method for aligning
electrodes to a nanochannel sensor.
[0013] FIGS. 6A and 6B show a cross-sectional view and a top view,
respectively, of an electrode trench etching step, in accordance
with the first example method for aligning electrodes to a
nanochannel sensor.
[0014] FIGS. 7A and 7B show a cross-sectional view and a top view,
respectively, of an electrode formation step, in accordance with
the first example method for aligning electrodes to a nanochannel
sensor.
[0015] FIGS. 8A and 8B show a cross-sectional view and a top view,
respectively, of a second dielectric layer formation step, and the
formation of openings in the second dielectric layer, in accordance
with the first example method for aligning electrodes to a
nanochannel sensor.
[0016] FIGS. 9A and 9B show a cross-sectional view and a top view,
respectively, of a sacrificial line removal step, in accordance
with the first example method for aligning electrodes to a
nanochannel sensor.
[0017] FIGS. 10A and 10B show a cross-sectional view and a top
view, respectively, of a pinch-off step, in accordance with the
first example method for aligning electrodes to a nanochannel
sensor.
[0018] FIGS. 11A and 11B show a cross-sectional view and a top
view, respectively, of inlet, outlet, and electrode exposure step,
in accordance with the first example method for aligning electrodes
to a nanochannel sensor.
[0019] FIG. 12 shows flow diagram illustrating a third example
method for constructing a nanochannel sensor, according to yet
another embodiment of the invention.
[0020] FIGS. 13A-13C show a nanochannel sensor including a fluid
port region, feed channel region and a nanochannel region
constructed according to the third example method.
[0021] FIGS. 14A, 14B and 14C show cross-sectional views of the
port region, nanochannel region and feed channel region,
respectively, of a thick sacrificial line deposition step, in
accordance with the third example method for constructing a
nanochannel sensor.
[0022] FIGS. 15A, 15B and 15C show cross-sectional views of the
port region, nanochannel region and feed channel region,
respectively, of a first dielectric layer formation and
planarization steps, in accordance with the third example method
for constructing a nanochannel sensor.
[0023] FIGS. 16A, 16B and 16C show cross-sectional views of the
port region, nanochannel region and feed channel region,
respectively, of a thin sacrificial line deposition step, in
accordance with the third example method for constructing a
nanochannel sensor.
[0024] FIGS. 17A, 17B and 17C show cross-sectional views of the
port region, nanochannel region and feed channel region,
respectively, of a second dielectric layer formation step, in
accordance with the third example method for constructing a
nanochannel sensor.
[0025] FIGS. 18A, 18B and 18C show cross-sectional views of the
port region, nanochannel region and feed channel region,
respectively, of a sacrificial line removal step, in accordance
with the third example method for constructing a nanochannel
sensor.
[0026] FIGS. 19A, 19B and 19C show cross-sectional views of the
port region, nanochannel region and feed channel region,
respectively, of a pinch off step, in accordance with the third
example method for constructing a nanochannel sensor.
[0027] FIG. 20 shows a cross-sectional view of a nanochannel sensor
integrated with the back end of line (BEOL) wiring layers on a CMOS
chip.
DETAILED DESCRIPTION
[0028] The present invention is described with reference to
embodiments of the invention. Throughout the description of the
invention reference is made to FIGS. 1A-19C. When referring to the
figures, like structures and elements shown throughout are
indicated with like reference numerals.
[0029] FIGS. 1A, 1B, and 1C show a nanochannel sensor comprising a
nanochannel sensor region 100, a feed channel region 101, and a
port region 109 according to one embodiment of the invention. The
nanochannel sensor region 100 includes a substrate 102, a
dielectric layer 103, a nanochannel 106 and a pair of electrodes
112. The nanochannel sensor region 100 may also include a capping
layer 114. The feed channel region 101 includes a feed channel 107
formed within the dielectric layer 103. The port region 109
includes a fluid inlet/outlet port 121 formed within the dielectric
layers 103, 114 and 118.
[0030] The dielectric layer 103 may be formed over the substrate
102. The dielectric layer 103 may be an insulating film. For
example, the dielectric layer 103 may contain silicon dioxide. The
substrate 102 may also contain a layer of dielectric below the
dielectric layer 103 and the feed channel 107. The nanochannel 106
may be formed in the dielectric layer 103. The feed channel 107 may
also be formed in the dielectric layer 103. The feed channel 107
may include a bottom portion 110 and a top portion 108, with the
top portion 108 having a greater cross-sectional width than the
bottom portion 110. The top portion 108 of the feed channel 107 and
the nanochannel 106 may also have a smaller cross-sectional height
than the bottom portion 110 of the feed channel 107. The top
portion 108 may also extend beyond the edges of the bottom portion
110. The nanochannel 106 may be of the same height as the top
portion 108 of the feed channel 107, and formed from the same
sacrificial layer as the top portion 108 of the feed channel
107.
[0031] According to one embodiment of the invention, the dielectric
layer 103 may include a bottom dielectric layer 104 and a top
dielectric layer 105. The nanochannel 106 may be formed in the top
dielectric layer 105. The top portion 108 of the feed channel 107
may be formed in the top dielectric layer 105, and the bottom
portion 110 of the feed channel 107 may be formed in the bottom
dielectric layer 104.
[0032] The pair of electrodes 112 may be positioned on opposing
sides of the nanochannel 106. Electrodes 112 may contain a thin
palladium (Pd) layer, a titanium nitride (TiN) diffusion barrier,
followed by a copper layer. The electrodes 112 may be formed in the
top dielectric layer 105.
[0033] According to one embodiment of the invention, the
nanochannel sensor may also include a capping layer 114 over the
dielectric layer 103. The capping layer 114 may cover the
nanochannel 106, the feed channel 107, and the electrodes 112. The
capping layer 114 may also define a plurality of openings 116
through the capping layer 114 leading to the feed channel 107
and/or the nanochannel 106. The capping layer 114 may also be a
thin insulator layer.
[0034] According to another embodiment of the invention, the
nanochannel sensor may also include a conformal dielectric layer
120 between the nanochannel 106 and the electrodes 112.
Furthermore, the conformal dielectric layer 120 may contain
aluminum oxide or hafnium oxide. A pinch-off layer 118 of
dielectric material may "pinch-off" or seal the plurality of
openings 116 in the capping layer 114. The pinch-off layer maybe a
thin non-conformal dielectric.
[0035] According to yet another embodiment of the invention, the
port region 109 shown in FIG. 1C, which includes fluid inlet or
outlet port 121 maybe formed simultaneously and by the same
processes used to form the nanochannel channel sensor and feed
channel regions where opening are provided through the bottom
dielectric layer 104, top dielectric layer 105, and capping layer
114. The fluid inlet port 121 is connected to (i.e., fluid
communication with) the feed channel region 101, which is connected
to the nanochannel channel sensor region 100, which is connected to
another feed channel region, and which is connected to the fluid
outlet port 121. To insure that the feed channels are not sealed
where they connect to the port region, a non-conformal dielectric
layer is used for the pinch-off layer. Note that the pinch-off
layer is deposited at the bottom of the fluid inlet or outlet
ports, 121, so the layer thickness should be less than the height
of the feed channel (i.e., sum of the thickness of the bottom
dielectric layer 104 and top dielectric layer 105).
[0036] According to yet another embodiment of the invention, the
substrate 102 may include an insulator layer, such as silicon
dioxide (SiO.sub.2), deposited on a wafer, such as a silicon wafer.
The substrate 102 may also be a portion of a silicon-on-insulator
(SOI) wafer. FIGS. 2A and 2B show a first example method 200 of
aligning electrodes to a nanochannel sensor, in accordance with one
embodiment of the invention. In one embodiment of the invention,
the method 200 is integrated with a back end of line (BEOL) chip
fabrication process. For example, FIG. 20 shows a CMOS substrate
2001 containing the active electronic devices, carrying the back
end of line (BEOL) 2002 wiring layers that interconnect the active
devices, and the nanochannel sensor 2003. The wiring layers provide
electrical connections between the nanochannel sensor 2003 and the
active devices on the CMOS substrate 2001.
[0037] Returning to FIG. 2, the method 200 may include forming a
sacrificial line on a substrate 202, forming a dielectric layer
204, etching one pair of electrode trenches 206, forming one pair
of electrodes 208, depositing a capping layer 210, forming openings
through the capping layer 212, removing the sacrificial lines to
form a nanochannel and a feed channel 214, and depositing a
pinch-off layer 216
[0038] The method 200 involves a sacrificial line formation step
202, as shown on FIGS. 4A and 4B. At the sacrificial line formation
step 202, a sacrificial line 404 is deposited on an insulating
layer 403. The insulating layer 403 may include silicon dioxide
(SiO.sub.2), deposited on a wafer, such a silicon wafer. The
insulating layer may also be part of a silicon-on-insulator (SOI)
wafer, in which case the sacrificial line 404 may be formed by
etching the thin silicon layer of the wafer above the insulator,
resulting in the structures shown in FIGS. 4A and 4B.
[0039] According to one embodiment of the invention, the
sacrificial line 404 may contain sacrificial line material such as
polysilicon, amorphous silicon, single crystalline silicon, or
germanium. The dimensions of the sacrificial line 404 may be varied
by changing the thickness and the line width of the sacrificial
line materials. The sacrificial line may be formed from a thin film
of the sacrificial line material. Furthermore, the sacrificial line
404 may be patterned using a reactive ion etch (RIE) process,
conventional lithography, electron beam technology, or a sidewall
transfer process. Following patterning, the sacrificial line
material may also be partially oxidized to reduce the dimensions of
the material.
[0040] Returning to FIGS. 2A-2B, after the sacrificial line
formation step 202, the method 200 proceeds to a dielectric layer
formation step 204, as shown on FIGS. 5A and 5B. At the dielectric
layer formation step 204, the first dielectric layer 406 is formed
on the insulating layer 403 and around the sacrificial line 404.
The dielectric layer 406 may be an insulating film. It may also
contain silicon dioxide. The dielectric layer may be formed by
using plasma enhanced chemical vapor deposition (PECVD) of an
insulating material, followed by a chemical-mechanical polishing
(CMP) step in order to planarize the material. The CMP step may
stop at the top surface of the sacrificial line 404.
[0041] Returning to FIG. 2A-2B, after the dielectric layer
formation step 204, the method 200 proceeds to an electrode trench
etching step 206, as shown on FIGS. 6A and 6B. At the electrode
trench etching step 206, at least one pair of electrode trenches
408 are etched in the dielectric layer 406 on opposite sides of the
sacrificial line 404. The electrode trench etching step 206 may
also involve etching the dielectric layer at a faster etch rate
than etching the sacrificial line. A RIE process maybe used, for
example, to form the trench.
[0042] The electrode trenches 408 may be perpendicular to the
sacrificial line 404, and may be etched into the dielectric layer
406. The electrode trench etching step 206 may be accomplished with
little or no etching of the sacrificial line 404. Furthermore, the
depth of the trenches may be controlled by controlling the etch
time, or by building an etch stop in the first dielectric layer
406, or below it. The electrode trench 406 may be etched into the
insulating layer 403. Returning to FIGS. 2A-2B, after the electrode
trench etching step 206, the method 200 proceeds to an electrode
formation step 208, as shown on FIGS. 7A and 7B. At the electrode
formation step 208, at least one pair of electrodes 410 are formed
by filling the electrode trenches 408 with electrode material. CMP
may be used to planarize the electrode material. The electrodes may
include multiple layers. For example, sensing electrodes may
contain a thin palladium (Pd) layer, a titanium nitride (TiN)
diffusion barrier, followed by a copper layer. If Pd is used, an Ar
sputtering process may be used to etch exposed Pd if it is not
removed by CMP.
[0043] Returning to FIGS. 2A-2B, after the electrode formation step
208, the method 200 proceeds to a capping layer formation step 210,
as shown on FIGS. 8A and 8B. At the capping layer formation step
210, a capping layer 412 is deposited. The capping layer 412 may
cover the sacrificial line 404 and the electrodes 410. The second
dielectric layer 412 may also be a thin insulator layer.
[0044] Returning to FIGS. 2A-2B, after the capping layer formation
step 210, the method 200 proceeds to an opening etching step 212.
At the opening etching step 212, a plurality of openings or holes
414 are formed through the capping layer 412. These openings 414
may lead to the sacrificial line 404 and expose the sacrificial
line 404. Note that if the sacrificial line was partially oxidized,
the openings or holes would be etched through the oxidized layer
along with the capping layer 412 to expose the sacrificial line
404. The openings 414 are shown in FIGS. 8A and 8B.
[0045] Returning to FIGS. 2A-2B, after the opening etching step
212, the method 200 proceeds to a sacrificial line removal step
214, as shown on FIGS. 9A and 9B. At the sacrificial line removal
step 214, the sacrificial line 404 is removed in order to form a
nanochannel 416 between the electrodes 410. The sacrificial line
removal step 214 may include introducing Xenon Difluoride
(XeF.sub.2) to the sacrificial line 404 through the plurality of
openings 414. XeF.sub.2 may be introduced using a vapor phase etch
process. The sacrificial line removal step 214 may involve minimal
or no etching of components other than the sacrificial line
404.
[0046] According to one embodiment of the invention, the method 200
may also be used to form feed channels in addition to nanochannels
416. Feed channels and nanochannels 416 may form long, continuous
channels and may be formed simultaneously using the first example
method 200. Feed channels may include a bottom portion and a top
portion. The top portion of the feed channel may have a greater
width than the bottom portion. The top portion of the feed channel
may also have a smaller height than the bottom portion of the feed
channel. The overall cross-sectional area (i.e. height times width)
of the bottom portion of the feed channel may be greater than the
cross-sectional area of the top portion of the feed channel.
[0047] According to one embodiment of the invention, each pair of
electrodes 410 is self-aligned on opposite sides of the nanochannel
416. The electrodes 410 may also be electrically isolated from the
contents of nanochannel 416. The electrodes 410 may be in direct
electrical contact with the nanochannel 416, for example, in Ohmic
contact with the contents of the nanochannel 416.
[0048] After the sacrificial line removal step 214, the method 200
may proceed to a pinch-off step 216, as shown on FIGS. 10A and 10B.
At the pinch-off step, a pinch-off layer 418 is deposited on the
capping layer 412. The pinch-off layer 418 may seal or "pinch off"
the openings 414 leading to the sacrificial line 404. The pinch-off
layer 418 may be a thin non-conformal insulator layer. The
pinch-off step 216 may be a conventional microelectromechanical
systems (MEMS) fabrication step.
[0049] After the pinch-off step 216, the method 200 may proceed to
etching steps for exposing inlet reservoirs, outlet reservoirs, and
electrodes, as shown in FIGS. 11A and 11B. These etching steps may
be performed using a RIE process. Any inlets and outlets may be
connected to nanochannel. Inlets and outlets may also contain
biasing electrodes.
[0050] According to one embodiment of the invention, the plurality
of openings 414 leading to the sacrificial line may be located away
from the sites designated for inlet and outlet reservoirs. Thus,
during the sacrificial line removal step 214, removal of the
sacrificial line 404 may be limited to the portions of the
sacrificial line 404 away from the reservoirs. After initial
removal of the sacrificial line, the etching steps for exposing
inlet and outlet reservoirs may be selected to minimize etching of
the surviving portions of the sacrificial line. Finally, the
surviving portions of the sacrificial line may be removed, for
example using vapor phase XeF.sub.2, forming a completed
nanochannel. The openings 414 may also connect to sections of the
sacrificial line away from the nanochannel segments of the
sacrificial line. For example, the openings may connect to the feed
channel segments of the sacrificial line.
[0051] According to one embodiment of the invention, the completed
nanochannel sensor constructed using the first example method 200
may be used to conduct impedance spectroscopy experiments.
[0052] FIGS. 3A and 3B show a second example method 300 of aligning
electrodes to a nanochannel sensor, in accordance with another
embodiment of the invention. Many of the steps of the method 300
shown in FIGS. 3A and 3B are similar to the method shown in FIGS.
2A-2B.
[0053] The method 300 involves a sacrificial line formation step
302. At the sacrificial line formation step 302, a sacrificial line
is formed on an insulating layer. After the sacrificial line
formation step 302, the method 300 proceeds to a dielectric layer
formation step 304.
[0054] At the dielectric layer formation step 304, a dielectric
layer is formed on the substrate, around the sacrificial line, and
planarized. After the dielectric layer formation step 304, the
method 300 proceeds to an electrode trench etching step 306.
[0055] At the electrode trench etching step 306, at least one pair
of electrode trenches are etched in the dielectric layer on
opposite sides of the sacrificial line. After the electrode trench
etching step 306, the method 200 proceeds to conformal dielectric
layer deposition step 308.
[0056] At the conformal dielectric layer deposition step 308, a
conformal high-k dielectric layer is deposited between the
sacrificial line and the electrode trenches. The conformal high-k
dielectric layer may be a thin film and may contain materials such
as aluminum oxide or hafnium oxide. The conformal dielectric layer
may be selected in order to allow etching during the opening
etching step 314 but to minimize or prevent etching during the
sacrificial line removal step 316. After the conformal dielectric
layer deposition step 308, the method 300 proceeds to an electrode
formation step 310.
[0057] At the electrode formation step 310, at least one pair of
electrodes is formed by filling the electrode trenches with
electrode material. CMP may be used to planarize the electrode
material. The electrodes may include multiple layers. For example,
the electrodes may contain a titanium nitride (TiN) diffusion
barrier, followed by a copper layer. CMP may be used to planarize
the electrode material. After the electrode formation step 310, the
method 300 proceeds to a capping layer formation step 312.
[0058] At the capping layer formation step 312, a capping layer is
deposited. The capping layer may cover the conformal dielectric
layer over the sacrificial line 404, if it is not removed by the
CMP process, and the electrodes. After the capping layer formation
step 312, the method 300 proceeds to an opening etching step
314.
[0059] At the opening etching step 314, a plurality of openings are
formed through the capping layer and leading to the sacrificial
line. The openings may also be openings in the conformal dielectric
layer. After the opening etching step 314, the method 300 proceeds
to a sacrificial line removal step 316.
[0060] At the sacrificial line removal step 316, the sacrificial
line is removed in order to form a nanochannel between the
electrodes. The sacrificial line removal step may include Xenon
Difluoride etching of the sacrificial line through the plurality of
openings.
[0061] After the sacrificial line removal step 316, the method 300
may proceed to a pinch-off step 318. At the pinch-off step 318, a
pinch-off layer is deposited on the capping layer. The pinch-off
layer may seal or "pinch off" the openings leading to the
sacrificial line. The pinch-off layer may be a thin non-conformal
insulator layer. The pinch-off step may be a conventional MEMS
fabrication step.
[0062] After the pinch-off step 318, the method 300 may proceed to
etching steps for exposing electrodes contact pads. These etching
steps may be performed using a RIE process. Any inlets and outlets
may be connected to nanochannel. Inlets and outlets may also
contain biasing electrodes.
[0063] According to one embodiment of the invention, the method 300
may also be used to form feed channels in addition to nanochannels.
Feed channels and nanochannels may form long, continuous channels
and may be formed simultaneously using the second example method
300. Feed channels may include a bottom portion and a top portion.
The top portion of the feed channel may have a greater width than
the bottom portion. The top portion of the feed channel may also
have a smaller height than the bottom portion of the feed channel.
The overall cross-sectional area (i.e. height times width) of the
bottom portion of the feed channel may be greater than the
cross-sectional area of the top portion of the feed channel.
[0064] According to one embodiment of the invention, the plurality
of openings leading to the sacrificial line may be located away
from the sites designated for inlet and outlet reservoirs. Thus,
during the sacrificial line removal step 316, removal of the
sacrificial line may be limited to the portions of the sacrificial
line away from the reservoirs. After initial removal of the
sacrificial line, the etching steps for exposing inlet and outlet
reservoirs may be selected to minimize etching of the surviving
portions of the sacrificial line. Finally, the surviving portions
of the sacrificial line may be removed, for example using vapor
phase XeF.sub.2, forming a completed nanochannel. The openings may
also connect to sections of the sacrificial line away from the
nanochannel segments of the sacrificial line. For example, the
openings may connect to the feed channel segments of the
sacrificial line.
[0065] In a completed nanochannel sensor constructed according the
second example method 300, electrodes may be used to create
electric fields that have the ability to hold or move particles of
interest within the nanochannel.
[0066] FIG. 12 shows a third example method 500 for constructing a
nanochannel sensor, according to yet another embodiment of the
invention. Many of the steps of the method 500 shown in FIG. 12 are
similar to the methods shown in FIGS. 2A, 2B, 3A and 3B.
[0067] The method 500 involves constructing a nanochannel sensor
600 with a feed channel region 602 and a nanochannel region 604, as
shown in FIGS. 13A-13C.
[0068] FIG. 13A shows an integrated nanochannel sensor 600
implemented in a 40.times.40 mm CMOS chip. FIG. 13B shows a portion
of the integrated channel sensor 600, previously highlighted in
FIG. 13A. FIG. 13B shows the fluid port regions 601, feed channel
regions 602 and nanochannel regions 604 of the chip 600. FIG. 13C
shows a portion of the integrated channel sensor, highlighted in
FIG. 13B. Fluid generally flows in from one fluid port 601, through
a feed channel region 602, through a nanochannel region 604. Fluid
may flow out through a reverse path, through a second nanochannel
region 604, through a second feed channel region 602, and out
through a second fluid port 601. The feed channel region may also
include a supporting mesh, possibly constructed of silicon oxide.
The mesh may provide structural support to the feed channel region
during fluid flow. The feed channels may have a much greater cross
sectional area than the nanochannels. This may be accomplished by
using an additional thick sacrificial layer in the feed channel
region 602. To permit integration of the nanochannel sensor with
the CMOS wiring (back end of line; BEOL) layers, the sacrificial
lines maybe formed of amorphous silicon or other materials which
can be deposited at temperatures of about 400.degree. C. or less
and etched by Xenon Difluoride. In this case, the substrate would
contain the CMOS circuits and may also contain one or more of the
BEOL wiring layers.
[0069] The method 500 begins with a thick sacrificial line
formation step 502, as shown on FIGS. 14A-14C. At the thick
sacrificial line formation step 502, one or more thick sacrificial
lines 606 are formed on the feed channel region substrate 608 and
the port region substrate 607. The substrates 607, 608, and 610 may
contain an insulating layer 605 on the surface.
[0070] The thick sacrificial lines 606 may be formed from a thin
film of the sacrificial line material. Furthermore, the thick
sacrificial line 606 may be patterned using reactive ion etching
(RIE), conventional lithography, electron beam technology, or a
sidewall transfer process.
[0071] After the thick sacrificial line formation step 502, the
method 500 proceeds to a dielectric layer formation step 504, as
shown on FIGS. 15A-15C. At the dielectric layer formation step 504,
a dielectric layer 612 is formed on the port region substrate 607,
feed channel region substrate 608 and the nanochannel region
substrate 610. The dielectric layer is also formed over the thick
sacrificial line 606. Chemical-mechanical polishing (CMP) may then
be used to planarize the first dielectric layer and expose the top
surface of the thick sacrificial line 606. Those skilled in the art
would recognize that additional thick sacrificial lines of
progressively increasing width may be formed on top of the first
thick line by repeating steps 502 and 504.
[0072] After the dielectric layer formation step 504, the method
500 proceeds to a thin sacrificial line deposition step 506, as
shown in FIGS. 16A-16C. At the thin sacrificial line deposition
step 506, thin layers of sacrificial lines 614 and 616 are
deposited over the dielectric layer 612 or over the thick
sacrificial lines 606. In the nanochannel region 604, thin, narrow
sacrificial lines 616 are deposited over the first dielectric layer
612. In the port region 601 and feed channel region 602, thin, wide
sacrificial lines 614 are deposited over both the dielectric layer
612 and the thick sacrificial line 606, and extend beyond the edges
of the thick sacrificial lines 606.
[0073] The thin sacrificial lines 614 and 616 may have thinner
cross sections than the thick sacrificial lines 606. The thin, wide
sacrificial lines 614 may have a wider cross section than the thin,
narrow sacrificial lines 616. The thin, wide sacrificial lines 614
may also have a wider cross section than the thick sacrificial
lines 606 and extend beyond their edges.
[0074] According to one embodiment of the invention, the thin and
thick sacrificial lines 606, 614 and 616 may contain sacrificial
line material such as polysilicon, amorphous silicon, single
crystalline silicon, germanium, tungsten, molybdenum, tantalum or
tantalum nitride. The thin sacrificial lines 614 and 616 may be
formed from a thin film of the sacrificial line material.
Furthermore, the thin sacrificial lines 614 and 616 may be
patterned using reactive ion etching (RIE), conventional
lithography, electron beam technology, or a sidewall transfer
process. Following patterning, the thin sacrificial line material
may also be oxidized.
[0075] Returning to FIG. 12, after the thin sacrificial line
deposition step 506, the method 500 proceeds to a capping layer
formation step 508, as shown on FIGS. 17A-17C. At the second
dielectric layer formation step 508, a capping layer 618 is
deposited. The capping layer 618 may cover the thin sacrificial
lines 614 and 616 and the dielectric layer 612. The capping layer
618 may also be a thin insulator layer. CMP may be used to
planarize the surface of the second dielectric layer, possibly
without removing enough material to expose the thin sacrificial
lines.
[0076] After the capping layer formation step 508, the method 500
proceeds to an opening etching step 510. At the opening etching
step 510, a plurality of openings or holes 609 and 620 are formed
through the capping layer 618 in the feed channel region 602 and
port region 601, respectively. These openings 609 and 620 may lead
to and expose the thin, wide sacrificial lines 614, as shown on
FIGS. 17A and 17C.
[0077] Returning to FIG. 12, after the opening etching step 510,
the method 500 proceeds to a sacrificial line removal step 512, as
shown on FIGS. 18A-18C. At the sacrificial line removal step 512,
the sacrificial lines 606, 614, and 616 are removed in order to
form the port 620, feed channels 622 and nanochannels 624. Removal
of the thick sacrificial lines and the thin, wide sacrificial lines
creates feed channels 622 and removal of the thin, narrow
sacrificial lines creates nanochannels. The sacrificial line
removal step 512 may include introducing Xenon Difluoride
(XeF.sub.2) to the sacrificial lines 606, 614, and 616 through the
plurality of openings 620 and 609. XeF.sub.2 may be introduced
using a vapor phase etch process. The sacrificial line removal step
512 may involve etching minimal or no etching of components other
than the sacrificial lines 606, 614, and 616.
[0078] Returning to FIG. 12, after the sacrificial line removal
step 512, the method 500 proceeds to a pinch-off step 514, as shown
on FIGS. 19A-19C. At the pinch-off step 514, a pinch-off layer 626
is deposited on the capping layer 618. The pinch-off layer 626 may
seal or "pinch off" the openings 609 over the feed channel region
602 but not pinch off the relatively larger opening 620 over the
port region 601 leading to the sacrificial lines 606, 614, and 616.
The pinch-off layer 626 may be a thin non-conformal insulator
layer.
[0079] The descriptions of the various embodiments of the present
invention have been presented for purposes of illustration, but are
not intended to be exhaustive or limited to the embodiments
disclosed. Many modifications and variations will be apparent to
those of ordinary skill in the art without departing from the scope
and spirit of the described embodiments. The terminology used
herein was chosen to best explain the principles of the
embodiments, the practical application or technical improvement
over technologies found in the marketplace, or to enable others of
ordinary skill in the art to understand the embodiments disclosed
herein.
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