U.S. patent application number 14/276469 was filed with the patent office on 2014-09-04 for wiring board with built-in electronic component and method for manufacturing the same.
This patent application is currently assigned to IBIDEN CO., LTD.. The applicant listed for this patent is IBIDEN CO., LTD.. Invention is credited to Toshiki Furutani, Shunsuke SAKAI, Kenji Sato.
Application Number | 20140247571 14/276469 |
Document ID | / |
Family ID | 42056163 |
Filed Date | 2014-09-04 |
United States Patent
Application |
20140247571 |
Kind Code |
A1 |
SAKAI; Shunsuke ; et
al. |
September 4, 2014 |
WIRING BOARD WITH BUILT-IN ELECTRONIC COMPONENT AND METHOD FOR
MANUFACTURING THE SAME
Abstract
A wiring board with a built-in electronic component includes a
core substrate having a penetrating hole formed in the core
substrate, an electronic component accommodated in the penetrating
hole in the core substrate, a conductive pattern layer formed on a
first surface of the core substrate and including a first
conductive pattern and a second conductive pattern, and an
interlayer insulation layer formed over the conductive pattern
layer and the first surface of the core substrate. The second
conductive pattern is formed adjacent to a periphery of the
penetrating hole such that the second conductive pattern is formed
along an outline of the periphery of the penetrating hole.
Inventors: |
SAKAI; Shunsuke; (Ogaki-shi,
JP) ; Sato; Kenji; (Ogaki-shi, JP) ; Furutani;
Toshiki; (Ogaki-shi, JP) |
|
Applicant: |
Name |
City |
State |
Country |
Type |
IBIDEN CO., LTD. |
Ogaki-shi |
|
JP |
|
|
Assignee: |
IBIDEN CO., LTD.
Ogaki-shi
JP
|
Family ID: |
42056163 |
Appl. No.: |
14/276469 |
Filed: |
May 13, 2014 |
Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
|
|
13369376 |
Feb 9, 2012 |
|
|
|
14276469 |
|
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|
|
12555438 |
Sep 8, 2009 |
8466372 |
|
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13369376 |
|
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|
61101286 |
Sep 30, 2008 |
|
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Current U.S.
Class: |
361/761 ;
174/251 |
Current CPC
Class: |
H05K 2201/10674
20130101; H01L 21/568 20130101; Y02P 70/50 20151101; H05K 2203/1469
20130101; H01L 2224/45124 20130101; H01L 2924/00014 20130101; H01L
24/24 20130101; H05K 2203/049 20130101; H05K 3/4602 20130101; H01L
2224/48227 20130101; H01L 24/82 20130101; H01L 2924/3025 20130101;
H01L 24/45 20130101; H05K 1/184 20130101; H05K 2203/0156 20130101;
H01L 2224/48091 20130101; H01L 24/48 20130101; H01L 2924/18162
20130101; H05K 2201/10636 20130101; H01L 2924/14 20130101; Y02P
70/611 20151101; H01L 2924/12042 20130101; H05K 1/185 20130101;
H01L 2224/04105 20130101; H05K 2203/0191 20130101; H01L 23/5389
20130101; H01L 2224/45144 20130101; H01L 2924/19041 20130101; H05K
2201/09781 20130101; H01L 2924/014 20130101; H05K 1/0298 20130101;
H01L 2224/24227 20130101; H01L 2224/48091 20130101; H01L 2924/00014
20130101; H01L 2924/12042 20130101; H01L 2924/00 20130101; H01L
2224/45124 20130101; H01L 2924/00014 20130101; H01L 2924/00014
20130101; H01L 2224/45015 20130101; H01L 2924/207 20130101; H01L
2224/45144 20130101; H01L 2924/00014 20130101 |
Class at
Publication: |
361/761 ;
174/251 |
International
Class: |
H05K 1/02 20060101
H05K001/02; H05K 1/18 20060101 H05K001/18 |
Claims
1. A wiring board with a built-in electronic component, comprising:
a core substrate having a penetrating hole formed in the core
substrate; an electronic component accommodated in the penetrating
hole in the core substrate; a conductive pattern layer formed on a
first surface of the core substrate and including a first
conductive pattern and a second conductive pattern; and an
interlayer insulation layer formed over the conductive pattern
layer and the first surface of the core substrate, wherein the
second conductive pattern is formed adjacent to a periphery of the
penetrating hole such that the second conductive pattern is formed
along an outline of the periphery of the penetrating hole.
2. The wiring board with a built-in electronic component according
to claim 1, further comprising: an interlayer insulation layer
formed over a second surface opposite to the first surface of the
core substrate; and a conductive pattern formed over the interlayer
insulation layer formed over the second surface of the core
substrate, wherein the interlayer insulation layer formed over the
second surface of the core substrate has a via conductor such that
the via conductor electrically connects the conductive pattern over
the second surface of the core substrate and a terminal of the
electronic component.
3. The wiring board with a built-in electronic component according
to claim 1, wherein the second conductive pattern is configured
such that the second conductive pattern is framing the periphery of
the penetrating hole.
4. The wiring board with a built-in electronic component according
to claim 1, wherein the second conductive pattern comprises a
plurality of portions facing each other across the penetrating
hole.
5. The wiring board with a built-in electronic component according
to claim 1, wherein the second conductive pattern is configured
such that the second conductive pattern comprises a plurality of
portions framing the periphery of the penetrating hole.
6. The wiring board with a built-in electronic component according
to claim 1, wherein the second conductive pattern is configured
such that the second conductive pattern is framing the periphery of
the penetrating hole in a continuous line.
7. The wiring board with a built-in electronic component according
to claim 1, wherein the second conductive pattern is configured
such that the second conductive pattern is framing the periphery of
the penetrating hole in a broken line.
8. The wiring board with a built-in electronic component according
to claim 1, wherein the second conductive pattern has a side
surface which is formed on substantially the same level as an
inner-wall surface of the core substrate forming the penetrating
hole.
9. The wiring board with a built-in electronic component according
to claim 1, wherein the second conductive pattern has a portion
which is protruding into the penetrating hole.
10. The wiring board with a built-in electronic component according
to claim 1, wherein the second conductive pattern is configured
such that the second conductive pattern is maintaining a space from
the outline of the penetrating hole on the first surface of the
core substrate.
11. The wiring board with a built-in electronic component according
to claim 1, wherein the second conductive pattern has a maximum
width which is made greater than a maximum width of the first
conductive pattern.
12. The wiring board with a built-in electronic component according
to claim 1, wherein the second conductive pattern has a thickness
which is made substantially a same as a thickness of the first
conductive pattern.
13. The wiring board with a built-in electronic component according
to claim 1, wherein the core substrate has a gap between the core
substrate and the electronic component accommodated in the
penetrating hole, and the gap is filled with a resin material.
14. The wiring board with a built-in electronic component according
to claim 1, wherein the electronic component is positioned in the
penetrating hole such that the electronic component has a surface
without circuits faces the first surface of the core substrate.
15. The wiring board with a built-in electronic component according
to claim 1, further comprising: a conductive pattern layer formed
on a second surface opposite to the first surface of the core
substrate and including a first conductive pattern and a second
conductive pattern, wherein the second conductive pattern on the
second surface of the core substrate is formed adjacent to a
periphery of the penetrating hole on the second surface of the core
substrate such that the second conductive pattern on the second
surface of the core substrate is formed along an outline of the
periphery of the penetrating hole on the second surface of the core
substrate.
16. The wiring board with a built-in electronic component according
to claim 1, wherein the second conductive pattern is configured
such that the second conductive pattern has a plurality of spaces
formed adjacent to the periphery of the penetrating holes.
17. The wiring board with a built-in electronic component according
to claim 1, wherein the electronic component is a multilayered
capacitor having a plurality of electrodes on opposite end portions
of the multilayered capacitor, respectively.
18. The wiring board with a built-in electronic component according
to claim 1, wherein the second conductive pattern is a dummy
conductive pattern.
19. The wiring board with a built-in electronic component according
to claim 1, wherein the second conductive pattern forms an electric
circuit.
20. The wiring board with a built-in electronic component according
to claim 1, wherein the second conductive pattern comprises a
plurality of portions formed adjacent to the periphery of the
penetrating hole such that the plurality of portions is formed
along the outline of the periphery of the penetrating hole.
Description
CROSS-REFERENCE TO RELATED APPLICATIONS
[0001] The present application is continuation of and claims the
benefit of priority under 35 U.S.C. .sctn.120 to U.S. Ser. No.
13/369,376, filed Feb. 9, 2012, which is a division of U.S. Ser.
No. 12/555,438, filed Sep. 8, 2009, now U.S. Pat. No. 8,466,372,
issued Jun. 18, 2013, which is based on and claims the benefit of
priority to U.S. Application No. 61/101,286, filed Sep. 30, 2008.
The entire contents of these applications are incorporated herein
by reference.
BACKGROUND OF THE INVENTION
[0002] 1. Field of the Invention
[0003] The present invention is related to a wiring board with a
built-in electronic component in which an electronic component such
as a semiconductor element is accommodated.
[0004] 2. Discussion of the Background
[0005] In recent years, electronic devices have become more highly
functional and compact. Accordingly, wiring boards mounted inside
such electronic devices are further required to be highly
functional and highly integrated.
[0006] For example, in Japanese Patent Laid-Open Publication
2002-246757, a method for manufacturing a multilayer printed wiring
board is described as follows: a step to laminate a sheet such as a
UV tape on the bottom of a penetrating hole formed in a core
substrate; a step to mount a semiconductor element such as an IC
chip on the sheet in such a way that its terminals contact the
adhesive surface of the sheet; a step to fill resin in the
penetrating hole; a step to cure the filled resin; a step to remove
the sheet; and a step to form build-up layers on the top surface of
the semiconductor element.
[0007] As shown in FIG. 13A, the UV tape or the like may likely
warp. Furthermore, if the laminated UV tape or the like is warped,
sealing on the bottom side becomes incomplete. Accordingly, as
shown in FIG. 13B, filling resin may seep into the gaps between the
core substrate and the UV tape or the like. The contents of this
publication are incorporated herein by reference in their
entirety.
SUMMARY OF THE INVENTION
[0008] According to one aspect of the present invention, a wiring
board with a built-in electronic component includes a core
substrate having a penetrating hole formed in the core substrate,
an electronic component accommodated in the penetrating hole in the
core substrate, a conductive pattern layer formed on a first
surface of the core substrate and including a first conductive
pattern and a second conductive pattern, and an interlayer
insulation layer formed over the conductive pattern layer and the
first surface of the core substrate. The second conductive pattern
is formed adjacent to a periphery of the penetrating hole and
contoured to laminate a sheet for positioning the electronic
component in the penetrating hole horizontally with respect to the
first surface of the core substrate over the penetrating hole.
[0009] According to another aspect of the present invention, a
method for manufacturing a wiring board with a built-in electronic
component includes forming a penetrating hole which accommodates an
electronic component in a core substrate, forming a conductive
pattern layer having a first conductive pattern and a second
conductive pattern on one surface of the core substrate such that
the second conductive pattern is formed adjacent to a periphery of
the penetrating hole and contoured to laminate a sheet for
positioning the electronic component in the penetrating hole
horizontally with respect to the first surface of the core
substrate over the penetrating hole, laminating the adhesive tape
over the surface of the core substrate, mounting the electronic
component on the adhesive tape forming the bottom of the
penetrating hole, filling a resin material in a gap between the
electronic component and the core substrate to secure the
electronic component in the penetrating hole, and removing the
adhesive tape after the electronic component is secured.
BRIEF DESCRIPTION OF THE DRAWINGS
[0010] A more complete appreciation of the invention and many of
the attendant advantages thereof will be readily obtained as the
same becomes better understood by reference to the following
detailed description when considered in connection with the
accompanying drawings, wherein:
[0011] FIG. 1A is a cross-sectional view of a copper-clad laminate
to be used in the present embodiment;
[0012] FIG. 1B is a cross-sectional view showing a phase in which a
through-hole is formed in the substrate shown in FIG. 1A;
[0013] FIG. 1C is a cross-sectional view showing a phase after
electroless copper plating and electrolytic copper plating were
performed on the substrate shown in FIG. 1B;
[0014] FIG. 1D is a cross-sectional view showing a phase in which a
conductive pattern is formed on the core substrate;
[0015] FIG. 1E is a cross-sectional view showing a phase in which a
penetrating hole is formed in the core substrate;
[0016] FIG. 2A is a cross-sectional view showing a phase in which a
tape is laminated on the core substrate;
[0017] FIG. 2B is a cross-sectional view showing a phase in which
an electronic component is mounted;
[0018] FIG. 3A is a cross-sectional view showing a phase in which
an interlayer insulation layer is formed on the first surface of
the core substrate;
[0019] FIG. 3B is a cross-sectional view showing a phase after the
tape was removed from the substrate shown in FIG. 3A;
[0020] FIG. 3C is a cross-sectional view showing a phase in which
an interlayer insulation layer is formed on the second surface of
the core substrate;
[0021] FIG. 4A is a plan view seen from the second-surface side of
the substrate in FIG. 1D showing its essential part;
[0022] FIG. 4B is a plan view seen from the second-surface side of
the substrate in FIG. 1E showing its essential part;
[0023] FIG. 5 is a cross-sectional view of a wiring board with a
built-in electronic component according to an embodiment of the
present invention;
[0024] FIG. 6 is a cross-sectional view of a built-up multilayer
printed wiring board using the substrate with a built-in electronic
component shown in FIG. 5;
[0025] FIG. 7 is a cross-sectional view showing a phase in which a
conductive pattern is formed on a core substrate in another
embodiment;
[0026] FIGS. 8A-8C are cross-sectional views showing an example in
which an electronic component is accommodated in a face-down
position;
[0027] FIGS. 9A-9J are plan views to illustrate examples of dummy
patterns in other embodiments;
[0028] FIGS. 10A-10C are cross-sectional views showing an example
in which an accommodated electronic component is a capacitor;
[0029] FIGS. 11A and 11B are cross-sectional views showing an
example in which an electronic component is mounted through
wire-bonding;
[0030] FIGS. 12A-12C are cross-sectional views showing an example
in which an electronic component is flip-chip mounted; and
[0031] FIGS. 13A and 13B are cross-sectional views to illustrate
conventional art.
DETAILED DESCRIPTION OF THE EMBODIMENTS
[0032] The embodiments will now be described with reference to the
accompanying drawings, wherein like reference numerals designate
corresponding or identical elements throughout the various
drawings.
[0033] FIG. 5 is a cross-sectional view schematically showing
substrate 1 with a built-in electronic component manufactured
according to a manufacturing method of Embodiment 1. Substrate 1
with a built-in electronic component has core substrate 2,
electronic component 3 accommodated (built in) in core substrate 2,
conductive patterns 4, 5 formed respectively on both main surfaces
of core substrate 2, interlayer insulation layers 6, 7, conductive
patterns 8, 9 formed respectively on interlayer insulation layers
6, 7, and conductive pattern 10 formed on one main surface of core
substrate 2.
[0034] Core substrate 2 is a substrate made by impregnating
reinforcing material (base material) with resin. Its thickness is
approximately 110 .mu.m. As for a reinforcing material, glass
cloth, glass non-woven fabric, aramid non-woven fabric or the like
may be used preferably. Other than those, any insulative material
of equal strength may be used.
[0035] Also, as for the resin to be impregnated in the reinforcing
material, epoxy resin, BT (bismaleimide triazine) resin, polyimide
resin or the like may be employed.
[0036] Conductive patterns 4, 5 are made of copper or the like and
their thicknesses are each approximately 20 .mu.m. Conductive
pattern 4 is formed on one main surface (hereinafter referred to as
the first surface) of core substrate 2; and conductive pattern 5 is
formed on the other main surface (hereinafter referred to as the
second surface) of core substrate 2. Conductive pattern 4 and
conductive pattern 5 are electrically connected by means of
through-hole conductors 20.
[0037] Electronic component 3 is an IC chip in the present
embodiment, and is accommodated in penetrating hole 21 of core
substrate 2 in a so-called face-up position.
[0038] Interlayer insulation layers 6, 7 are formed with a plate
made by impregnating reinforcing material such as glass fabric,
aramid fabric or the like with resin such as epoxy resin, polyester
resin, polyimide resin, BT resin, phenol resin or the like. In the
present embodiment, all the plates are formed with prepreg.
Interlayer insulation layer 6 is formed on the first surface of
core substrate 2 and interlayer insulation layer 7 is formed on the
second surface. Their thicknesses are each approximately 60
.mu.m.
[0039] Conductive patterns 8, 9 are made of copper or the like and
their thicknesses are each approximately 20 .mu.m. Conductive
pattern 8 is formed on interlayer insulation layer 6, and is
electrically connected through via conductors 60 to conductive
pattern 4 and terminals 30 of electronic component 3. On the other
hand, conductive pattern 9 is formed on interlayer insulation layer
7 and is electrically connected through via conductors 70 to
conductive pattern 9.
[0040] Conductive pattern 10 is formed on the second surface of
core substrate 2 the same as in conductive pattern 5. Conductive
pattern 10 is made of copper or the like and its thickness is
approximately 20 .mu.m. Conductive pattern 10 is used to precisely
position electronic component 3 as described later in detail, and
it is not electrically connected to other conductive patterns.
[0041] In the following, a method for manufacturing substrate 1
with a built-in electronic component is described with reference to
FIGS. 1A-4B.
[0042] First, as shown in FIG. 1A, a copper-clad laminate is
prepared in which copper foils 101, 102 with an approximate
thickness of 12 .mu.m are laminated on both main surfaces of core
substrate 2 with an approximate thickness of 110 .mu.m.
[0043] In the following, through-holes 103 are formed in the
copper-clad laminate shown in FIG. 1A by a drilling method using a
drill or the like (see FIG. 1B). Here, through-holes 103 may be
formed using a carbon dioxide gas (CO.sub.2) laser, Nd:YAG laser,
excimer laser or the like.
[0044] In the following, a treatment (desmear treatment) is
conducted to remove smearing or the like remaining on the inner
surfaces of through-holes 103. Then, electroless copper plating and
electrolytic copper plating are performed on the copper-clad
laminate shown in FIG. 1B. Accordingly, as shown in FIG. 1C,
copper-plated films 104, 105 are formed on both main surfaces of
the copper-clad laminate shown in FIG. 1B along with through-hole
conductors 20.
[0045] Then, using a subtractive method, unnecessary portions of
copper-plated films 104, 105 are removed to form conductive
patterns 4, 5, (10a) (see FIG. 1D). Conductive pattern (10a) is an
original configuration (before drilling) of conductive pattern 10,
and as shown in FIG. 4A, it is formed to be greater than the area
of the mounting surface (namely, the area where the circuit is not
formed) of electronic component 3. In the present embodiment, the
size of conductive pattern (10a) is equal to the area in which the
outline of the surface (rectangular) of electronic component 3
where the circuit is not formed is enlarged with a predetermined
length (L) (approximately 50 .mu.m).
[0046] Next, by a drilling method using a drill or the like,
penetrating hole 21 is formed to accommodate electronic component 3
(see FIG. 1E). Here, penetrating hole 21 may be formed using a
carbon dioxide gas (CO.sub.2) laser, Nd:YAG laser, excimer laser or
the like. By drilling such a hole, conductive pattern 10 is formed.
As shown in FIG. 4B, conductive pattern 10 is configured on the
second surface of core substrate 2 to frame the end surface of
penetrating hole 21 on the second-surface side without leaving gaps
in between. The width of the frame which surrounds penetrating hole
21 is approximately 8.1 mm.
[0047] As shown in FIG. 7, conductive pattern 10 may also be formed
in advance before forming penetrating hole 21. In such a case,
conductive pattern 10 is formed in the same process of forming
conductive patterns 4, 5.
[0048] In the following, sheet or tape 201 is laminated on the
second-surface side of the substrate shown in FIG. 1E (see FIG.
2A). As for tape 201, a UV tape (such as the Adwill D series, made
by Lintec Corporation), whose adhesiveness is reduced through UV
(ultraviolet) beaming to allow easy removal of the tape, may be
used. Various adhesive tapes, for example, polyimide tapes or the
like, whose adhesiveness is not reduced by high heat of over
80.degree. C. during provisional curing, may also be used.
[0049] During that time, tape 201 may easily be laminated
substantially horizontally without causing warping, since
conductive pattern 10 exists there, which has the same thickness as
that of conductive pattern 5 and is contoured or configured to
frame the end surface of penetrating hole 21 on the second-surface
side.
[0050] After tape 201 is laminated, electronic component 3 is
mounted on its bonding (adhesive) surface in a so-called face-up
position (see FIG. 2B). Here, as described above, since tape 201 is
laminated substantially horizontally, electronic component 3 may be
positioned precisely without being shifted vertically.
[0051] In the following, on the first surface of the substrate
shown in FIG. 2B, a resin film material (prepreg in the present
embodiment) with an approximate thickness of 60 .mu.m is laminated
using a vacuum lamination method. As a result, as shown in FIG. 3A,
interlayer insulation layer 6 is formed. During such lamination,
the resin material flows into through-hole conductors 20, while
flowing into the gaps in penetrating hole 21 between electronic
component 3 and the inner walls of core substrate 2. Accordingly,
the gaps between electronic component 3 and the inner walls of core
substrate 2 are filled with the resin material.
[0052] As described above, conductive pattern 10 frames the end
surface of penetrating hole 21 on the second-surface side without
leaving gaps in between, and adheres to tape 201. Therefore, the
resin material that flowed into the gaps between electronic
component 3 and the inner walls of core substrate 2 will not flow
out onto the second surface of core substrate 2, since pattern 10
works as a wall to block such flow.
[0053] In the following, UV rays are beamed and tape 201 is removed
(see FIG. 3B). Then, a resin film material (prepreg in the present
embodiment) with an approximate thickness of 60 .mu.m is laminated
on the second surface of the substrate shown in FIG. 3B using a
vacuum lamination method. By doing so, as shown in FIG. 3C,
interlayer insulation layer 7 is formed. During such lamination,
the resin material flows into the interior of through-hole
conductors 20, thus filling the interior of through-hole conductors
20 with resin material.
[0054] As shown in FIGS. 8A-8C, electronic component 3 may also be
accommodated in a face-down position.
[0055] Next, using a carbon dioxide gas (CO.sub.2) laser, UV-YAG
laser or the like, via-holes are formed at predetermined spots of
the substrate shown in FIG. 3C, and conductive patterns 8, 9 and
via conductors 60, 70 are formed using an additive method.
Accordingly, substrate 1 with a built-in electronic component is
obtained as shown in FIG. 5.
[0056] As described, according to the manufacturing method of the
present embodiment, conductive pattern 10 having the same thickness
as conductive pattern 5 is formed on the second surface of core
substrate 2 so as to frame the end surface of penetrating hole 21
on the second-surface side. Accordingly, tape 201 may easily be
laminated substantially horizontally.
[0057] Then, since tape 201 is laminated substantially
horizontally, electronic component 3 may be mounted in a
substantially horizontal way at a predetermined position in
penetrating hole 21. By doing so, the flatness of interlayer
insulation layer 6 may be ensured. As a result, conductive pattern
8 may be formed finely on interlayer insulation layer 6 and via
conductors 60 may also be formed precisely. Therefore, connection
reliability between terminals 30 of electronic component 3 and via
conductors 60 is enhanced.
[0058] Also, since conductive pattern 10 frames the end surface of
penetrating hole 21 on the second-surface side without leaving gaps
in between and thus forms walls, the resin material will not flow
out onto the second surface of core substrate 2 during the
lamination process. Therefore, the flatness of the top surface
(where the circuit is formed) of accommodated electronic component
3 may further be ensured.
[0059] FIG. 6 shows an example of a built-up multilayer printed
wiring board obtained by further building up multiple layers on
substrate 1 with a built-in electronic component shown in FIG. 5.
In the following, a method for manufacturing such a built-up
multilayer printed wiring board is briefly described.
[0060] First, on the first and second surfaces of substrate 1 with
a built-in electronic component, interlayer insulation layers 601,
602 are formed respectively. After that, opening portions are
formed in interlayer insulation layers 601, 602 that reach
conductive patterns 8, 9 formed in substrate 1 with a built-in
electronic component.
[0061] Next, on interlayer insulation layers 601, 602, conductive
patterns 603, 604 are formed respectively. During that time, via
conductors 605, 606 are also formed respectively in the opening
portions of interlayer insulation layers 601, 602. By doing so,
conductive pattern 603 and conductive pattern 8 are electrically
connected, and conductive pattern 604 and conductive pattern 9 are
electrically connected.
[0062] In the same manner, interlayer insulation layers 607, 608,
conductive patterns 609, 610 and via conductors 611, 612 are
formed.
[0063] In the following, on both main surfaces of the substrate, a
liquid or dry-film photosensitive resist (solder resist) is either
applied or laminated. Then, a mask film with a predetermined
pattern is adhered to the surface of the photosensitive resist,
which is exposed to ultraviolet rays and developed in an alkaline
solution.
[0064] As a result, solder-resist layers 613, 614 are formed where
openings are arranged to expose portions of conductive patterns
609, 610 which are to become solder pads. Accordingly, the built-up
multilayer printed wiring board is obtained as shown in FIG. 6.
[0065] The present invention is not limited to the above
embodiment, but various modifications may be made within the scope
of the present invention.
[0066] For example, in the above embodiment, conductive pattern 10
is formed, as shown in FIG. 4B, to be made substantially flush with
the outline of the end surface of penetrating hole 21 on the
second-surface side. However, the present invention is not limited
to such. For example, as shown in FIG. 9A, conductive pattern 10
may be formed while being slightly detached from the outline. In
doing so, when forming interlayer insulation layer 6, part of the
resin material forming interlayer insulation layer 6 may likely
flow out of penetrating hole 21 and into the second surface of core
substrate 2. However, since the resin material is blocked by
conductive pattern 10, core substrate 2 will be filled with the
resin material only to the wall of conductive pattern 10.
Accordingly, the effect is to enhance adhesiveness between core
substrate 2 and interlayer insulation layer 6. However, the
distance detached from the outline is preferred to be made shorter
than the line width (namely, the frame width) of conductive pattern
10.
[0067] Alternatively, conductive pattern 10 may be formed to
protrude slightly into the interior of penetrating hole 21 as shown
in FIG. 9B. To configure conductive pattern 10 in such a way, a
slightly complex process is needed, compared with the above
embodiment. However, a process to laminate tape 201 substantially
horizontally may be carried out even more easily.
[0068] Also, in the above embodiment, the outline of the end
surface of penetrating hole 21 was rectangular and the
configuration of conductive pattern 10 was also rectangular.
However, the configuration of the end surface of penetrating hole
21 or of conductive pattern 10 is not limited to such in the above
embodiment. For example, as shown in FIG. 9C, the outline of the
end surface of penetrating hole 21 and the outline of conductive
pattern 10 may be oval.
[0069] Alternatively, the configuration of conductive pattern 10 is
not necessarily the same as the outline of the end surface of
penetrating hole 21 (see FIG. 9D). Furthermore, the line width of
conductive pattern 10 does not have to be uniform (see FIG.
9E).
[0070] Also, in the above embodiment, conductive pattern 10 is
formed to frame the end surface of penetrating hole 21 without
leaving gaps in between. However, its configuration is not limited
to such. For example, as shown in FIG. 9F, multiple fine spaces may
exist. If conductive pattern 10 has such spaces as described, when
forming interlayer insulation layer 6, there may be a risk that
part of the resin material that has flowed into the gaps between
electronic component 3 and the inner walls of core substrate 2 goes
beyond the wall of conductive pattern 10 and flows onto the second
surface of core substrate 2. However, the effect that tape 201 may
easily be laminated substantially horizontally remains the same. In
addition, by filling the spaces of conductive pattern 10 with the
resin material, another effect will be expected that adherence
between core substrate 2 and interlayer insulation layer 6
increases.
[0071] From the same view point as above, conductive pattern 10
does not necessarily have to be formed to frame the end surface of
penetrating hole 21. For example, conductive pattern 10 may be
formed in such configurations as shown in FIGS. 9G-9I. In short, as
long as conductive pattern 10 is configured in such a way as to
easily allow tape 201 to be laminated substantially horizontally,
it is sufficient.
[0072] Also, conductive pattern 10 may be formed on both main
surfaces of core substrate 2 instead of only on its one main
surface. In FIG. 9J, an example is shown where conductive patterns
10 are formed on both main surfaces of core substrate 2, and
copper-plated films 900 are formed on the side surfaces of
penetrating hole 21 to connect both conductive patterns. As shown
in FIG. 9J, if conductive patterns 10 and copper-plated films 900
are formed, a shielding effect may also be shown in addition to the
above described effect.
[0073] Moreover, in the above embodiment, conductive pattern 10 was
described as not electrically connected to other conductive
patterns (namely, a dummy conductive pattern). However, conductive
pattern 10 may be electrically connected to other conductive
patterns to function as an electric circuit. Alternatively, the
second conductive pattern may be used as a power source conductor
or ground conductor.
[0074] In addition, electronic component 3 accommodated in core
substrate 2 is not limited to semiconductor elements such as an IC
chip or the like. For example, as shown in FIGS. 10A-10C, a
capacitor may be accommodated in core substrate 2 through the same
process FIG. 2B-FIG. 3B as in the above embodiment.
[0075] Also, in the above embodiment, when forming interlayer
insulation layer 6, the gaps between electronic component 3 and the
inner walls of core substrate 2 are filled with the resin material
forming interlayer insulation layer 6 to secure electronic
component 3. However, electronic component 3 may be secured using
other methods. For example, before forming interlayer insulation
layer 6 (namely, before laminating a resin material), insulative
resin (such as a resin made of thermosetting resin and inorganic
filler) may be filled in the gaps between electronic component 3
and the inner walls of core substrate 2 to secure electronic
component 3.
[0076] Furthermore, in the above embodiment, terminals 30 of
electronic component 3 are connected through via conductors 60 to
conductive pattern 8 on interlayer insulation layer 6. However,
electronic component 3 is not limited to any mounting method; for
example, electronic component 3 may be mounted using a wire bonding
connection.
[0077] In the process of such a case, as shown in FIG. 11A,
electronic component 3 is mounted in a face-up position on the
connection (adhesive) surface of tape 201 on the substrate shown in
FIG. 2A. On the top surface (the surface where circuits are formed)
of electronic component 3, pads, not shown in the drawings, are
arranged instead of connection terminals.
[0078] Then, as shown in FIG. 11B, pads of electronic component 3
and pads on core substrate 2 (here, parts of conductive pattern 4)
are connected using wires 111 (fine wires made of gold or
aluminum).
[0079] In such a case, since the flatness features of the top
surface (where circuits are formed) of electronic component 3 are
ensured as in the above embodiment, the accuracy of wire bonding
connections is enhanced.
[0080] Also, the present invention may be applied in a case in
which electronic component 3 is flip-chip mounted. In the process
in such a case, as shown in FIG. 12A, base material 120 instead of
tape 201 is laminated on the second-surface side of the substrate
shown in FIG. 1E. Base material 120 is formed with insulative
material 121 such as prepreg or the like, pads 122 formed on
insulative material 121 and solder bumps 123 formed on pads
122.
[0081] Then, as shown in FIG. 12B, electronic component 3 is
mounted in a face-down position. Namely, electronic component 3
with bumps 31 is accommodated in penetrating hole 21 of the
substrate shown in FIG. 12A and mounted on base material 120 with
its surface where circuits are formed facing down. Bumps 31 of
electronic component 3 are connected to solder bumps 123. Then, as
shown in FIG. 12C, the gaps in penetrating hole 21 of core
substrate 2 are filled with underfill material 124. Underfill
material 124 is, for example, insulative resin containing inorganic
filler such as silica or alumina. It ensures the strength to secure
electronic component 3, while absorbing warping generated due to
the gap in thermal expansion coefficients between electronic
component 3 and core substrate 2.
[0082] As described, in a case where electronic component 3 is
flip-chip mounted, electronic component 3 may also be mounted in a
predetermined spot in penetrating hole 21 in a substantially
horizontal manner.
[0083] Here, the conductive adhesive layers (not shown in the
drawings) formed on pads 122 and bumps 31 of electronic component 3
may be electrically connected. The conductive adhesive layers are,
for example, formed through tin plating, solder plating, or alloy
plating such as tin-silver-copper plating.
[0084] A wiring board with a built-in electronic component
according to one embodiment of the present invention includes a
core substrate, an electronic component accommodated in a
penetrating hole formed in the core substrate, a first conductive
pattern formed on at least one main surface of the core substrate,
a second conductive pattern formed on the same main surface as
where the first conductive pattern is formed, and one or multiple
interlayer insulation layers and conductive-pattern layers formed
on the core substrate. Here, the second conductive pattern is
formed on at least part of the periphery of an end surface of the
penetrating hole.
[0085] A terminal of the electronic component may be electrically
connected through a via conductor formed in any of the interlayer
insulation layers to the conductive pattern formed on that
interlayer insulation layer.
[0086] Alternatively, a terminal of the electronic component may be
electrically connected to the conductive pattern formed on any of
the interlayer insulation layers by means of a conductive bump or a
conductive adhesive layer.
[0087] Alternatively, a pad of the electronic component may be
electrically connected through a wire to another conductive pattern
which is different from the first conductive pattern and the second
conductive pattern formed on either one of the main surfaces of the
core substrate.
[0088] On the periphery of an end surface of the penetrating hole,
the second conductive pattern may be formed in parts facing each
other across the penetrating hole.
[0089] The second conductive pattern may frame the periphery of an
end surface of the penetrating hole.
[0090] The second conductive pattern may be in a continuous line to
frame the periphery of an end surface of the penetrating hole.
[0091] Alternatively, the second conductive pattern may be in a
broken line to frame the periphery of an end surface of the
penetrating hole. In the parts between the discontinued lines, the
surface of the core substrate may be exposed.
[0092] A side surface of the second conductive pattern may be
formed on substantially the same level as the inner-wall surface of
the core substrate where the penetrating hole is formed.
[0093] Alternatively, part of the second conductive pattern may
protrude into the penetrating hole.
[0094] Alternatively, the second conductive pattern may maintain a
predetermined space from the outline of an end surface of the
penetrating hole.
[0095] The maximum width of the second conductive pattern may be
made greater than the maximum width of the first conductive
pattern.
[0096] The thickness of the second conductive pattern is preferred
to be made substantially the same as the thickness of the first
conductive pattern.
[0097] Resin is preferred to be filled in the gaps between the
electronic component in the penetrating hole and the inner walls of
the core substrate.
[0098] The electronic component is preferred to be accommodated in
such a way that the surface of the electronic component where
circuits are not formed faces the surface of the core substrate
where the second conductive pattern is formed.
[0099] The second conductive pattern may be formed on both main
surfaces of the core substrate.
[0100] A method for manufacturing a wiring board with a built-in
electronic component according to another embodiment of the present
invention includes the following: a step to form a penetrating hole
to accommodate an electronic component in a core substrate; a step
to form a first conductive pattern and a second conductive pattern
on at least the same main surface of the core substrate; a step to
laminate an adhesive tape on the surface of the core substrate
where the first conductive pattern and the second conductive
pattern are formed; a step to mount an electronic component on the
adhesive surface of the adhesive tape at the bottom of the
penetrating hole; a step to secure the electronic component by
filling resin material in the gaps between the mounted electronic
component and the inner walls of the core substrate; and a step to
remove the adhesive tape after the electronic component is secured.
Here, the second conductive pattern is formed on at least part of
the periphery of an end surface of the penetrating hole.
[0101] Furthermore, the following steps may be added; a step to
form an interlayer insulation layer and a conductive pattern on the
electronic component and the core substrate; and a step to form in
the insulation layer a via conductor which electrically connects a
terminal of the electronic component and the conductive
pattern.
[0102] On the periphery of an end surface of the penetrating hole,
the second conductive pattern may be formed in parts facing each
other across the penetrating hole.
[0103] The second conductive pattern may frame the periphery of an
end surface of the penetrating hole.
[0104] The second conductive pattern may be in a continuous line to
frame the periphery of an end surface of the penetrating hole.
[0105] Alternatively, the second conductive pattern may be in a
broken line to frame the periphery of an end surface of the
penetrating hole. In the parts between the discontinued lines, the
surface of the core substrate may be exposed.
[0106] A side surface of the second conductive pattern may be
formed on substantially the same level as the inner-wall surface of
the core substrate where the penetrating hole is formed.
[0107] Alternatively, part of the second conductive pattern may be
formed to protrude into the penetrating hole.
[0108] Alternatively, the second conductive pattern may maintain a
predetermined space from the outline of an end surface of the
penetrating hole.
[0109] The maximum width of the second conductive pattern may be
made greater than the maximum width of the first conductive
pattern.
[0110] Also, the adhesive tape is preferred to be a UV tape whose
adhesiveness is reduced when ultraviolet rays are beamed.
[0111] Also, the thickness of the second conductive pattern is
preferred to be made substantially the same as the thickness of the
first conductive pattern. Obviously, numerous modifications and
variations of the present invention are possible in light of the
above teachings. It is therefore to be understood that within the
scope of the appended claims, the invention may be practiced
otherwise than as specifically described herein.
* * * * *