U.S. patent application number 13/790437 was filed with the patent office on 2014-09-04 for chip on chip attach (passive ipd and pmic) flip chip bga using new cavity bga substrate.
This patent application is currently assigned to DIALOG SEMICONDUCTOR GMBH. The applicant listed for this patent is DIALOG SEMICONDUCTOR GMBH. Invention is credited to Ian Kent.
Application Number | 20140246773 13/790437 |
Document ID | / |
Family ID | 48050636 |
Filed Date | 2014-09-04 |
United States Patent
Application |
20140246773 |
Kind Code |
A1 |
Kent; Ian |
September 4, 2014 |
Chip on Chip Attach (Passive IPD and PMIC) Flip Chip BGA Using New
Cavity BGA Substrate
Abstract
An integrated passive device and power management integrated
circuit are directly connected, active surface to active surface,
resulting in a pyramid die stack. The die stack is flip-chip
attached to a laminate substrate having a cavity drilled therein
wherein the smaller die fits into the cavity. The die to die attach
is not limited to IPD and PMIC and can be used for other die types
as required.
Inventors: |
Kent; Ian; (Calne,
GB) |
|
Applicant: |
Name |
City |
State |
Country |
Type |
DIALOG SEMICONDUCTOR GMBH |
Kirchheim/Teck-Nabern |
|
DE |
|
|
Assignee: |
DIALOG SEMICONDUCTOR GMBH
Kirchheim/Teck-Nabern
DE
|
Family ID: |
48050636 |
Appl. No.: |
13/790437 |
Filed: |
March 8, 2013 |
Current U.S.
Class: |
257/738 ;
438/108 |
Current CPC
Class: |
H01L 2924/15153
20130101; H01L 2924/15311 20130101; H01L 2924/19042 20130101; H01L
23/293 20130101; H01L 2924/181 20130101; H01L 2924/19104 20130101;
H01L 2924/15159 20130101; H01L 23/49894 20130101; H01L 2224/16145
20130101; H01L 2924/19103 20130101; H01L 24/32 20130101; H01L
2924/15313 20130101; H01L 25/0657 20130101; H01L 2924/12042
20130101; H01L 24/81 20130101; H01L 2224/16225 20130101; H01L
2224/32225 20130101; H01L 2924/18161 20130101; H01L 25/50 20130101;
H01L 2224/16227 20130101; H01L 24/17 20130101; H01L 23/49816
20130101; H01L 2924/15311 20130101; H01L 2224/1703 20130101; H01L
2224/13147 20130101; H01L 2924/12042 20130101; H01L 2924/1579
20130101; H01L 2924/35121 20130101; H01L 24/73 20130101; H01L
21/565 20130101; H01L 23/49866 20130101; H01L 2924/15156 20130101;
H01L 2924/19041 20130101; H01L 2224/16265 20130101; H01L 23/13
20130101; H01L 2924/19043 20130101; H01L 2224/73204 20130101; H01L
2224/32225 20130101; H01L 2924/00 20130101; H01L 2924/00 20130101;
H01L 2224/16225 20130101; H01L 2224/32225 20130101; H01L 2924/00
20130101; H01L 2924/00 20130101; H01L 2224/16225 20130101; H01L
2224/1403 20130101; H01L 2225/06513 20130101; H01L 2224/73204
20130101; H01L 25/16 20130101; H01L 2924/181 20130101; H01L
2225/06517 20130101; H01L 2924/19011 20130101; H01L 2924/19051
20130101; H01L 21/563 20130101; H01L 23/3128 20130101; H01L 24/13
20130101; H01L 24/16 20130101; H01L 2224/73204 20130101; H01L
2225/06568 20130101 |
Class at
Publication: |
257/738 ;
438/108 |
International
Class: |
H01L 23/00 20060101
H01L023/00 |
Foreign Application Data
Date |
Code |
Application Number |
Mar 4, 2013 |
EP |
13368005.8 |
Claims
1. A method of fabricating a mother and daughter integrated circuit
device comprising: providing a mother die having an active surface;
providing a daughter die having an active surface wherein said
daughter die is smaller than said mother die in all dimensions;
directly connecting said active surface of said daughter die to
said active surface of said mother die resulting in a pyramid die
stack; providing a substrate having a cavity drilled therein
wherein said cavity corresponds to a size and position of said
daughter die in relation to said mother die; and attaching said
pyramid die stack to said substrate using a flip chip method
wherein said daughter die fits into said cavity.
2. The method according to claim 1 wherein said mother die is a
power management circuit chip.
3. The method according to claim 1 wherein said daughter die is an
integrated passive device containing at least one passive
device.
4. The method according to claim 3 wherein said at least one
passive device is chosen from the group containing a capacitor, a
resistor, an inductor, a balun, and a filter.
5. The method according to claim 1 wherein said directly connecting
said active surface of said daughter die to said active surface of
said mother die comprises micro bumps.
6. The method according to claim 1 wherein said cavity is drilled
by a mechanical drilling process or a laser drilling process.
7. The method according to claim 1 wherein said substrate is a ball
grid array or a land grid array substrate.
8. The method according to claim 1 wherein said attaching said
pyramid die stack to said substrate comprises copper pillar
interconnects.
9. A method of fabricating an integrated passive device comprising:
providing a first die containing at least one power management
device; providing a second die containing at least one passive
device wherein said second die is smaller than said first die;
directly connecting an active surface of said second die to an
active surface of said first die resulting in a die stack;
providing a substrate having a cavity drilled therein wherein said
cavity corresponds to a size and position of said second die in
relation to said first die; and attaching said die stack to said
substrate using a flip chip method wherein said second die fits
into said cavity.
10. The method according to claim 9 wherein said at least one
passive device is chosen from the group containing a capacitor, a
resistor, an inductor, a balun, and a filter.
11. The method according to claim 9 wherein said directly
connecting said active surface of said second die to said active
surface of said first die comprises micro bumps.
12. The method according to claim 9 wherein said cavity is drilled
by a mechanical drilling process or by a laser drilling
process.
13. The method according to claim 9 wherein said substrate is a
ball grid array or a land grid array substrate.
14. The method according to claim 9 wherein said attaching said die
stack to said substrate comprises copper pillar interconnects.
15. A mother and daughter integrated circuit comprising: a mother
die having an active surface; a daughter die having an active
surface wherein said daughter die is smaller than said mother die
and wherein an active surface of said daughter die is directly
connected to an active surface of said mother die resulting in a
pyramid die stack; and a substrate having a cavity drilled therein
wherein said pyramid die stack is flip-chip attached to said
substrate wherein said daughter die fits into said cavity.
16. The device according to claim 15 wherein said mother die is a
power management circuit chip.
17. The device according to claim 15 wherein said daughter die is
an integrated passive device containing at least one passive
device.
18. The device according to claim 17 wherein said at least one
passive device is chosen from the group containing a capacitor, a
resistor, an inductor, a balun, and a filter.
19. The device according to claim 15 wherein said substrate is
laminate substrate.
20. The device according to claim 15 wherein said substrate is a
ball grid array or a land grid array substrate.
Description
TECHNICAL FIELD
[0001] This disclosure is related to flip chip attachment of Mother
die and Daughter Integrated Passive Device die, and more
particularly, to methods of flip chip attachment of Mother die and
Daughter Integrated Passive Device die in an inverted pyramid die
stack, using a laser drilled cavity laminate Ball Grid Array/Land
Grid Array substrate to accommodate the protruding Daughter
die.
BACKGROUND
[0002] Passive device integration is typically done by: [0003] 1)
Back side on active side die stacking with wire bond
interconnection, [0004] 2) Surface Mount of the passive to the top
layer of a laminate substrate, or [0005] 3) Embedding large passive
components into a printed circuit board.
[0006] The limitations of these methods prevent direct electrical
connection between mother and daughter die, followed by the flip
chip attach of the resulting inverted die stack onto a Ball Grid
Array (BGA) or Land Grid Array (LGA) laminate substrate. Direct
connection would allow for better electrical performance and
printed circuit board (PCB) real estate reduction by integrating
passives off the PCB and into the package.
[0007] In the past, substrate technologies were limited with
respect to the ability to laser or mechanically drill a cavity into
a laminate substrate having a Bismaleimide Triazine (BT) core while
maintaining mechanical and reliability integrity. With the
advancements in substrate manufacturing technology, it is now
possible to manufacture substrates with mechanically drilled or
lasered cavities.
[0008] U.S. Pat. No. 7,915,084 (Hong), U.S. Pat. No. 8,222,717
(Shim et al), and U.S. Pat. No. 7,835,157 (Tilmans) discuss
integrated passive devices, but these are completely different die
stacking and die to substrate interconnection and package types
from those in the present disclosure.
SUMMARY
[0009] It is the primary objective of the present disclosure to
provide a new integration method for inverted pyramid die stack
using flip chip attachment to a BGA or LGA laminate cavity
substrate.
[0010] Yet another objective is to use a die on die attachment to
produce direct contact of a Mother die to a Daughter die.
[0011] In accordance with the objectives of the present disclosure,
a method of fabricating a mother and daughter integrated circuit is
achieved. A mother die and a daughter die, wherein the daughter die
is smaller than the mother die, are directly connected, active
surface to active surface, resulting in a die stack. The die stack
is flip-chip attached to a substrate having a cavity drilled
therein wherein the daughter die fits into the cavity.
[0012] Also in accordance with the objectives of the present
disclosure, a method of fabricating an integrated passive device is
achieved. An integrated passive device and power management
integrated circuit are directly connected, active surface to active
surface, resulting in a die stack. The die stack is flip-chip
attached to a substrate having a cavity drilled therein wherein the
smaller die fits into the cavity.
[0013] Also in accordance with the objectives of the present
disclosure, an mother and daughter integrated circuit is achieved.
A mother die and a daughter die, wherein the daughter die is
smaller than the mother die, are directly connected, active surface
to active surface, resulting in a pyramid die stack. The pyramid
die stack is flip-chip attached to a substrate having a cavity
drilled therein wherein the daughter die fits into the cavity.
BRIEF DESCRIPTION OF THE DRAWINGS
[0014] In the accompanying drawings forming a material part of this
description, there is shown:
[0015] FIG. 1 is a top view of a substrate having a cavity
therein.
[0016] FIG. 2 is a cross-sectional representation of the substrate
in FIG. 1, having the cavity therein.
[0017] FIG. 3 is a cross-sectional representation of a die stack
showing die to die interconnection.
[0018] FIG. 4 is a cross-sectional representation of a flip chip
attachment of the substrate and the die stack of FIGS. 2 and 3,
respectively.
[0019] FIG. 5 is an enlarged cross-sectional representation of a
portion of FIG. 4.
DETAILED DESCRIPTION
[0020] The present disclosure is a process integration method of
fabricating chip on chip using flip chip attachment and a cavity
substrate. For example, this method can be used for passive and
power management integrated circuit (PMIC) devices. The Daughter
die, such as an integrated passive device (IPD) chip, is attached
under the Mother die, such as a power management chip, resulting in
an inverted pyramid die stack once flipped onto the cavity
substrate. Since the daughter chip protrudes below the
interconnects of the mother chip, it needs a cavity substrate for
flip chip attachment. The die on die attach capability produces
direct contact between the mother and daughter chips.
[0021] This package technology has recently become viable due to:
[0022] 1) Availability of the IPD die, and [0023] 2) Laminate
cavity substrate as opposed to the use of standard surface mount
passives.
[0024] Higher accuracy drilling capabilities of substrate suppliers
are essential to this technology. Higher drilling accuracy
minimizes cavity sizes to prevent potential package XY dimension
increase for integration into existing products. Package XY
dimension is critical in order to reduce end printed circuit board
(PCB) space which is at a premium and very cost sensitive.
[0025] Advancements in substrate drilling systems and tools prevent
mechanical vibration resulting in mechanical damage and substrate
layer separation which can lead to package delamination and
reliability failures and permits the laser drilling of cavities in
laminate substrates.
[0026] Referring now more particularly to FIGS. 1-5, a preferred
integration method will be described.
[0027] The present disclosure provides a new process integration
for fabricating chip on chip using flip chip attachment and a
cavity substrate. For example, these may be passive and power
management integrated circuit (PMIC) devices, but the method is not
limited to only these types of devices. For illustration purposes,
the mother chip will be a power management chip and the daughter
chip will be an integrated passive device, for example.
[0028] Referring now to FIG. 3, there is shown [0029] 1) Mother
chip 10, which may be a power management chip. [0030] 2) Daughter
chip 14, which may be an IPD chip. [0031] 3) Active surface of the
IPD chip 16 being attached to the active surface of the power
management chip 12 using micro bump 33. [0032] 4) The copper pillar
interconnect 35 for the power management chip to attach the pyramid
die stack to the laminate substrate 20 (FIG. 2).
[0033] The IPD chip could be a capacitor array or other passives
such as resistors, inductors, baluns, or filters, or the like. The
direct electrical connections between the active surfaces of the
two dies 10 and 14, using micro bump 33, result in better
electrical performance than non-direct connections, such as wire
bonding or passive surface mount and connection via laminate
substrate copper trace. The die on die attach results in the flip
chip attach of the pyramid die stack as shown in FIG. 4.
[0034] The IPD die is smaller than the PMIC die in all dimensions,
i.e. length, width, and height directions. The IPD die size can
vary depending upon the number of passives required. The smaller
IPD die, when attached to the PMIC die, then results in a pyramid
die stack configuration.
[0035] FIG. 2. illustrates a laminate substrate 20 having solder
balls 30 on the underside of the substrate. Solder balls are
required for BGA packages, but this cavity substrate technology is
also applicable for LGA packages where solder balls are not
attached. The substrate 20 has been laser drilled to form cavity
25.
[0036] Advancements in substrate drilling techniques and tools
allow for the laser drilling of this small cavity 25 without
increasing the package dimension and without causing mechanical
damage or substrate layer separation.
[0037] FIG. 1 illustrates a top view of the substrate shown in
cross-section view A-A' in FIG. 2. Cavity 25 is shown.
[0038] The die on die attached chips shown in FIG. 3 are flipped
resulting in an inverted pyramid die stack 22 as shown in FIG. 4.
Now the die stack 22 is connected to the BGA substrate 20 via the
copper pillars 35 using a flip chip attach method. The passive IPD
die 14 protrudes below the interconnects 35 of the mother die 10,
but it fits into the cavity 25 drilled into the substrate 20.
[0039] This method can be applied for some existing products by
re-routing substrate metal traces in the laminate substrate to make
space available for the cavity. This is only a slight change as
compared to the standard substrate. Alternatively, the cavity can
be designed into new laminate substrates.
[0040] FIG. 5 is an enlarged portion of the cross-section of FIG.
4. There is shown: [0041] 1) Laminate substrate 20 [0042] 2) Power
management chip 10. [0043] 3) IPD chip 14. [0044] 4) Power
management to substrate interconnect via flip chip attach 35.
[0045] 5) IPD to power management interconnect micro bumps 33.
[0046] 6) Flip Chip attach underfill 32. [0047] 7) Epoxy Molding
Compound 34. [0048] 8) Substrate cavity 25. [0049] 9) BGA solder
balls 30.
[0050] Although the preferred embodiment of the present disclosure
has been illustrated, and that form has been described in detail,
it will be readily understood by those skilled in the art that
various modifications may be made therein without departing from
the spirit of the disclosure or from the scope of the appended
claims.
* * * * *