U.S. patent application number 14/228890 was filed with the patent office on 2014-08-21 for collector-up bipolar junction transistors in bicmos technology.
This patent application is currently assigned to International Business Machines Corporation. The applicant listed for this patent is International Business Machines Corporation. Invention is credited to James W. Adkisson, David L. Harame, Qizhi Liu.
Application Number | 20140231878 14/228890 |
Document ID | / |
Family ID | 51229012 |
Filed Date | 2014-08-21 |
United States Patent
Application |
20140231878 |
Kind Code |
A1 |
Adkisson; James W. ; et
al. |
August 21, 2014 |
COLLECTOR-UP BIPOLAR JUNCTION TRANSISTORS IN BICMOS TECHNOLOGY
Abstract
Fabrication methods, device structures, and design structures
for a bipolar junction transistor. An emitter is formed in a device
region defined in a substrate. An intrinsic base is formed on the
emitter. A collector is formed that is separated from the emitter
by the intrinsic base. The collector includes a semiconductor
material having an electronic bandgap greater than an electronic
bandgap of a semiconductor material of the device region.
Inventors: |
Adkisson; James W.;
(Jericho, VT) ; Harame; David L.; (Essex Junction,
VT) ; Liu; Qizhi; (Lexington, MA) |
|
Applicant: |
Name |
City |
State |
Country |
Type |
International Business Machines Corporation |
Armonk |
NY |
US |
|
|
Assignee: |
International Business Machines
Corporation
Armonk
NY
|
Family ID: |
51229012 |
Appl. No.: |
14/228890 |
Filed: |
March 28, 2014 |
Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
|
|
13769500 |
Feb 18, 2013 |
|
|
|
14228890 |
|
|
|
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Current U.S.
Class: |
257/198 |
Current CPC
Class: |
H01L 29/267 20130101;
H01L 29/0649 20130101; H01L 29/737 20130101; H01L 29/66242
20130101; H01L 29/7327 20130101; H01L 29/7378 20130101; H01L
29/7371 20130101 |
Class at
Publication: |
257/198 |
International
Class: |
H01L 29/737 20060101
H01L029/737 |
Claims
1. A device structure for a bipolar junction transistor, the device
structure comprising: a device region comprised of a first
semiconductor material having a first electronic bandgap; an
emitter in the device region; an intrinsic base on the emitter; and
a collector separated from the emitter by the intrinsic base, the
collector comprised of a second semiconductor material having a
second electronic bandgap greater than the first electronic
bandgap.
2. The device structure of claim 1 wherein the second electronic
bandgap is greater than 1.1 electron volts and less than or equal
to 6.3 electron volts.
3. The device structure of claim 2 wherein the first semiconductor
material comprises silicon, and the first electronic bandgap is
equal to 1.1 electron volts.
4. The device structure of claim 1 wherein the semiconductor
material of the collector comprises carbon-doped silicon (Si:C), a
binary III-V semiconductor, a binary II-VI semiconductor, a
tertiary III-V semiconductor, a tertiary II-VI semiconductor, or a
quaternary semiconductor.
5. The device structure of claim 1 wherein the device region has a
top surface, the emitter is beneath the top surface of the device
region, and the collector and the intrinsic base are above the top
surface of the device region.
6. The device structure of claim 1 wherein the device region has a
top surface, and further comprising: an isolation structure in the
device region, the isolation structure including a plurality of
sidewalls that are inclined at an angle relative to the top surface
of the device region and that define a boundary for the
emitter.
7. A hardware description language (HDL) design structure encoded
on a machine-readable data storage medium, the HDL design structure
comprising elements that when processed in a computer-aided design
system generates a machine-executable representation of a bipolar
junction transistor, the HDL design structure comprising: a device
region in a substrate; an emitter in the device region; an
intrinsic base on the emitter; and a collector separated from the
emitter by the intrinsic base, the collector comprised of a second
semiconductor material having a second electronic bandgap greater
than the first electronic bandgap.
8. The HDL design structure of claim 7 wherein the HDL design
structure comprises a netlist.
9. The HDL design structure of claim 7 wherein the DHL design
structure resides on storage medium as a data format used for the
exchange of layout data of integrated circuits.
10. The HDL design structure of claim 7 wherein the HDL design
structure resides in a programmable gate array.
Description
BACKGROUND
[0001] The invention relates generally to semiconductor device
fabrication and, in particular, to bipolar junction transistors,
fabrication methods for bipolar junction transistors, and design
structures for a bipolar junction transistor.
[0002] Bipolar junction transistors are typically found in
demanding types of integrated circuits, especially integrated
circuits destined for high-frequency applications. One specific
application for bipolar junction transistors is in radio frequency
integrated circuits (RICES), which are found in wireless
communications systems, power amplifiers in cellular telephones,
and other varieties of high-speed integrated circuits. Bipolar
junction transistors may also be combined with complementary
metal-oxide-semiconductor (CMOS) field effect transistors in
bipolar complementary metal-oxide-semiconductor (BiCMOS) integrated
circuits, which take advantage of the positive characteristics of
both transistor types in the construction of the integrated
circuit.
[0003] Conventional bipolar junction transistors constitute
three-terminal electronic devices constituted by three
semiconductor regions, namely an emitter, a base, and a collector.
An NPN bipolar junction transistor includes two regions of n-type
semiconductor material constituting the emitter and collector, and
a region of p-type semiconductor material sandwiched between the
two regions of n-type semiconductor material to constitute the
base. A PNP bipolar junction transistor has two regions of p-type
semiconductor material constituting the emitter and collector, and
a region of n-type semiconductor material sandwiched between two
regions of p-type semiconductor material to constitute the base.
Generally, the differing conductivity types of the emitter, base,
and collector form a pair of p-n junctions, namely a collector-base
junction and an emitter-base junction. A voltage applied across the
emitter-base junction of a bipolar junction transistor controls the
movement of charge carriers that produce charge flow between the
collector and emitters of the bipolar junction transistor.
[0004] Improved device structures, fabrication methods, and design
structures are needed that enhance the device performance of
bipolar junction transistors.
BRIEF SUMMARY
[0005] In an embodiment of the invention, a method is provided for
fabricating a bipolar junction transistor. The method includes
forming an emitter in a device region and forming an intrinsic base
layer on the emitter. After the emitter is formed, a collector is
formed that is separated from the emitter by the intrinsic base
layer. The device region is comprised of a first semiconductor
material having a first electronic bandgap, and the collector is
comprised of a second semiconductor material having a second
electronic bandgap greater than the first electronic bandgap.
[0006] In an embodiment of the invention, a device structure is
provided for a bipolar junction transistor. The device structure
includes a device region comprised of a first semiconductor
material having a first electronic bandgap, an emitter in the
device region, an intrinsic base on the emitter, and a collector
separated from the emitter by the intrinsic base. The collector is
comprised of a second semiconductor material having a second
electronic bandgap greater than the first electronic bandgap.
[0007] In an embodiment of the invention, a hardware description
language (HDL) design structure is encoded on a machine-readable
data storage medium. The HDL design structure comprises elements
that, when processed in a computer-aided design system, generates a
machine-executable representation of a device structure for a
bipolar junction transistor. The HDL design structure includes a
device region comprised of a first semiconductor material having a
first electronic bandgap, an emitter in the device region, an
intrinsic base on the emitter, and a collector separated from the
emitter by the intrinsic base. The collector is comprised of a
second semiconductor material having a second electronic bandgap
greater than the first electronic bandgap. The HDL design structure
may comprise a netlist. The HDL design structure may also reside on
storage medium as a data format used for the exchange of layout
data of integrated circuits. The HDL design structure may reside in
a programmable gate array.
BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWINGS
[0008] The accompanying drawings, which are incorporated in and
constitute a part of this specification, illustrate various
embodiments of the invention and, together with a general
description of the invention given above and the detailed
description of the embodiments given below, serve to explain the
embodiments of the invention.
[0009] FIGS. 1-8 are cross-sectional views of a portion of a
substrate at successive fabrication stages of a processing method
for fabricating a device structure in accordance with an embodiment
of the invention.
[0010] FIG. 9 is a flow diagram of a design process used in
semiconductor design, manufacture, and/or test.
DETAILED DESCRIPTION
[0011] With reference to FIG. 1 and in accordance with an
embodiment of the invention, a substrate 10 includes trench
isolation structures 12 that circumscribe and electrically isolate
a device region 14 used in the fabrication of a bipolar junction
transistor 80 (FIG. 8). The substrate 10 may be any suitable bulk
substrate comprising a semiconductor material that a person having
ordinary skill in the art would recognize as suitable for forming
an integrated circuit. For example, substrate 10 may be comprised
of a wafer of a monocrystalline silicon-containing material, such
as single crystal silicon with a (100) crystal lattice orientation.
The semiconductor material comprising substrate 10 may be lightly
doped with an impurity to alter its electrical properties and may
also include an optional epitaxial layer. The top surface of the
device region 14 is coextensive with a top surface 10a of the
substrate 10.
[0012] The trench isolation structures 12 may be isolation
structures formed by a shallow trench isolation (STI) technique
that relies on a lithography and dry etching process to define
closed-bottomed trenches in substrate 10, deposit an electrical
insulator to fill the trenches, and planarize the electrical
insulator relative to the top surface 10a of the substrate 10 using
a chemical mechanical polishing (CMP) process. The electrical
insulator may be comprised of an oxide of silicon, such as
densified tetraethylorthosilicate (TEOS) deposited by chemical
vapor deposition (CVD). The trench isolation structures 12 have a
top surface 12a that is nominally coplanar with or slightly below
the top surface 10a of the substrate 10.
[0013] The device region 14 includes an emitter 18 and a subemitter
20 formed as impurity-doped regions of the same conductivity type.
A top surface of the emitter 18 may be coextensive with the top
surface 10a of the substrate 10 and device region 14. The sidewall
13 encircles or surrounds the emitter 18 and device region 14. More
specifically, the sidewall 13 is an interior surface of the trench
isolation structures 12 that is coextensive with the device region
14. The emitter 18 is at least partially beneath the top surface
10a of the device region 14 and, preferably, is completely below
the top surface 10a.
[0014] The emitter 18 and subemitter 20 may be formed by
introducing an impurity species to supply an electrically-active
dopant. In one embodiment, the emitter 18 and the subemitter 20 may
be formed by separate ion implantations of an n-type impurity
species from Group V of the Periodic Table (e.g., phosphorus (P),
arsenic (As), or antimony (Sb)) effective to impart an n-type
conductivity and, thereafter, annealing to activate the impurity
species and alleviate implantation damage. The subemitter 20 may be
formed by a high- current ion implantation of an n-type impurity
species followed by a lengthy, high temperature thermal anneal that
dopes a thickness of the substrate 10 before the optional epitaxial
layer is formed. During stages of the process flow subsequent to
implantation, the dopant in the emitter 18 may diffuse laterally
and vertically such that substantially the entire central portion
of device region 14 becomes impurity doped and, as a result, is
structurally and electrically continuous with the subemitter
20.
[0015] An intrinsic base layer 22 is formed as a continuous
additive layer on the top surface 10a of substrate 10. The
intrinsic base layer 22 is coupled with the emitter 18. The
intrinsic base layer 22 may be comprised of a semiconductor
material, such as silicon-germanium (SiGe) including silicon (Si)
and germanium (Ge) in an alloy with the silicon content ranging
from 95 atomic percent to 50 atomic percent and the germanium
content ranging from 5 atomic percent to 50 atomic percent. The
germanium content of the intrinsic base layer 22 may be uniform or
the germanium content of intrinsic base layer 22 may be graded
and/or stepped across the thickness of intrinsic base layer 22. If
the germanium content is stepped, a thickness of the intrinsic base
layer 22, such as a thickness directly contacting the emitter 18,
may not contain any germanium and may be entirely comprised of
silicon (Si). The intrinsic base layer 22 may be doped with one or
more impurity species, such as boron and/or carbon.
[0016] Intrinsic base layer 22 may be formed using a low
temperature epitaxial (LTE) growth process, such as vapor phase
epitaxy (VPE) that may be conducted at a growth temperature ranging
from 400.degree. C. to 850.degree. C. The epitaxial growth process
may be non-selective as single crystal semiconductor material
(e.g., single crystal silicon or SiGe) is epitaxially grown or
deposited onto any exposed crystalline surface such as the exposed
top surface 10a of device region 14, and non-monocrystalline
semiconductor material (e.g., polysilicon or polycrystalline SiGe)
is deposited non-epitaxially onto the non-crystalline material of
the trench isolation structures 12. For example, the single-crystal
semiconductor material of the device region 14 serves as a
crystalline template for the growth of at least the section of
intrinsic base layer 22 that is coextensive with the device region
14.
[0017] A base dielectric layer 24 is formed on a top surface 22a of
intrinsic base layer 22 and, in the representative embodiment,
directly contacts the top surface 22a. The base dielectric layer 24
may be comprised of an electrical insulator with a dielectric
constant (e.g., a permittivity) characteristic of a dielectric
material. In one embodiment, the base dielectric layer 24 may be
comprised of a high temperature oxide (HTO) deposited using rapid
thermal process (RTP) at temperatures of 500.degree. C. or higher.
Alternatively, the base dielectric layer 24 may be comprised of
oxide formed by a different deposition process, thermal oxidation
of silicon (e.g., oxidation at high pressure with steam (HIPDX)),
or a combination of these processes.
[0018] A sacrificial layer 26 is deposited on the top surface 24a
of the base dielectric layer 24. In a representative embodiment,
the sacrificial layer 26 may be comprised of polysilicon or
amorphous silicon deposited by CVD using either silane or disilane
as a silicon source. A cap layer 28 is applied on a top surface 26a
of sacrificial layer 26 and may be comprised of a different
material type, e.g., silicon dioxide, than sacrificial layer 26 and
that is not etched by the selective etching process applied
subsequently in the process flow.
[0019] With reference to FIG. 2 in which like reference numerals
refer to like features in FIG. 1 and at a subsequent fabrication
stage of the processing method, a plurality of trenches 29, 30 and
a plurality of trenches 31, 32 are formed that extend from a top
surface of the cap layer 28 completely through the cap layer 28,
the sacrificial layer 26, the base dielectric layer 24, the
intrinsic base layer 22, and into the device region 14. Trench 29
includes sidewalls 29a joined by a bottom surface 29b, trench 30
includes sidewalls 30a joined by a bottom surface 30b, trench 31
includes sidewalls 3 la joined by a bottom surface 31b, and trench
32 includes sidewalls 32a joined by a bottom surface 32b. The
bottom surfaces 29b, 30b, 31b, 32b are at a shallower depth than
the bottom surface of the trench isolation structures 12 relative
to the top surface 10a. The sidewalls 29a-32a are oriented with a
substantially vertical and parallel alignment, and may be oriented
at respective right angles relative (i.e., perpendicular) to the
top surface 10a of substrate 10. Additional trenches like trenches
29, 30 and additional trenches like trenches 31, 32 may be provided
in each trench group.
[0020] The emitter 18 is positioned between the portions of
trenches 30, 31 in the device region 14, and is characterized by a
width w.sub.1. Sections 33a, 33b of the device region 14, which may
have the same conductivity type as the emitter 18, are disposed
between the trenches 29, 32 and the sidewall 13 of the trench
isolation structures 12. Section 33a of the device region 14 is
coextensive with the sidewall 13 and with the outer sidewall 29a of
trench 29. Section 33b of the device region 14 is coextensive with
the sidewall 13 and with the outer sidewall 32a of trench 32. The
sections 33a, 33b of the device region 14 are characterized by a
width dimension, w.sub.1. The adjacent sidewalls 29a, 30a of
trenches 29, 30 are separated by a width, w.sub.3, of the material
of device region 14. In the representative embodiment, the adjacent
sidewalls 31a, 32a of trenches 31, 32 are also separated by the
width, w.sub.3, of the material of device region 14. An overlying
interior section 16 of the intrinsic base layer 22, which directly
contacts the emitter 18 in the representative embodiment, also has
the width, w.sub.1.
[0021] In one embodiment, the trenches 29-32 may comprise linear
open volumes that are aligned parallel to each other and separated
by strips of semiconductor material of the device region 14. In
this embodiment, the trenches 29-32 do not have a closed
geometrical shape. In an alternative embodiment, trenches 29, 32
and trenches 30, 31 may join or may be joined by additional
trenches to define a closed geometrical shape that surrounds or
encircles the collector 18. The sections 33a, 33b of the device
region 14 would likewise join or be joined by additional portions
of the device region 14 so that the sections 33a, 33b surround or
encircle the trenches 29, 32.
[0022] The trenches 29-32 may be formed using a photolithography
process and a non-selective etching process. To that end, a mask
layer (not shown) may be applied on the top surface of the cap
layer 28. The mask layer may comprise a photoresist that is applied
as a layer by a spin coating process, pre-baked, exposed to a
radiation projected through a photomask, baked after exposure, and
developed with a chemical developer to form an etch mask that
includes a pattern of openings coinciding with the intended
locations of the trenches 29-32. The pattern of openings is
transferred from the mask layer to the sacrificial layer 26, the
base dielectric layer 24, the intrinsic base layer 22, and the
emitter 18 to define the trenches 29-32 by the non-selective
etching process. The non-selective etching process may comprise a
wet etching process or a dry etching process, such as reactive-ion
etching (RIE) that produces vertical sidewalls 29a-32a. The
non-selective etching process, which may be conducted in a single
etching step or multiple steps, relies on one or more etch
chemistries that remove the materials of the cap layer 28, the
sacrificial layer 26, the base dielectric layer 24, the intrinsic
base layer 22, and the emitter 18, and may comprise a timed etch.
The mask layer is removed in response to forming the trenches
29-32. If comprised of a photoresist, the mask layer may then be
removed by ashing or solvent stripping, followed by a conventional
cleaning process.
[0023] When formed, the substrate 10 may be rotationally oriented
in the lithography tool used to pattern the mask layer in the
photolithography process using a feature on the substrate, such as
a notch at a peripheral edge, as an angular reference. Alignment
marks on the substrate 10 and photomask may also be aligned in the
photolithography tool to assist in rotationally orienting the
substrate 10. The openings subsequently formed in the patterned
mask layer are aligned with a crystallographic plane or orientation
of the crystalline semiconductor material of substrate 10. For
example, the openings may be oriented parallel to the [100]
directions of a single crystal silicon substrate. The preferential
alignment is transferred by the etching process from the openings
in the mask to the portion of the trenches 29-32 in the device
region 14. In particular, the trench sidewalls 29a-32a are each
aligned with a crystallographic plane or orientation of the
crystalline semiconductor material of substrate 10.
[0024] With reference to FIG. 3 in which like reference numerals
refer to like features in FIG. 2 and at a subsequent fabrication
stage of the processing method, trenches 34, 35 are formed in the
device region 14 by modifying the sections of trenches 29-32 within
the device region 14. Specifically, trenches 29, 30 are enlarged
and merged by etching the semiconductor material of device region
14 bordering trenches 29, 30 (FIG. 2) to define trench 34, and
trenches 31, 32 are enlarged and merged by etching the
semiconductor material of device region 14 bordering trenches 31,
32 (FIG. 2) to define trench 35. Trenches 34, 35 are wider than the
residual sections of trenches 29-32 remaining in the intrinsic base
layer 22.
[0025] Trench 34 includes an exterior sidewall 36 and an interior
sidewall 37 in the device region 14 that are continuous with the
residual sections of trenches 29, 30 in the intrinsic base layer
22. Trench 35 includes an exterior sidewall 38 and an interior
sidewall 39 in the device region 14 that are continuous with the
residual sections of trenches 31, 32 in the intrinsic base layer
22. Trenches 34, 35 surround the collector 18 and, more
specifically, sidewalls 37, 39 are coextensive with (i.e., define a
boundary of) the collector 18. Sidewalls 36-39 have a
non-perpendicular (i.e., inclined) orientation relative to the top
surface 10a. In particular, each of the sidewalls 36-39 becomes
inclined at an angle, .alpha., relative to the top surface 10a of
substrate 10 and relative to the sidewalls 29a-32a of the sections
of trenches 29-32 that remain in the intrinsic base layer 22. The
depth of the trenches 34, 35 may be slightly increased relative to
the original depth of trenches 29-32 by the anisotropic etching
process. As a result, the bottom surfaces 34a, 35a of trenches 34,
35 may be slightly deeper than the bottom surfaces 29b-32b.
[0026] The trenches 34, 35 may be created with an
orientation-dependent etching process, called an anisotropic
etching process herein, that may have different etch rates for
different crystallographic directions in a semiconductor and/or
that may have different etch rates for semiconductors of different
doping or different compositions. The anisotropic etching process
etches the semiconductor material of the device region 14 bordering
the sidewalls 29a-32a of trenches 29-32 (FIG. 3) in all
crystallographic directions, but at significantly different etching
rates for different crystal directions or planes. For example,
silicon etching in TMAH is relatively slow for (111) crystal planes
compared to other directions, such as (100) planes or (110) planes.
Therefore, the etch pattern formed by the anisotropic etching
process proceeds along the crystal planes of higher etching rate
and is eventually terminated by the crystal planes of lower etching
rate. The absolute etch rates in each crystallographic direction
and the relative etch rate in different crystallographic directions
may be dependent upon factors such as solution strength (i.e.,
concentration) and solution temperature of the etchant. The etch
time for exposure to the etchant may be selected to be adequate to
produce a targeted change in sidewall geometrical shape. In one
embodiment, the anisotropic etching process may be a wet chemical
etching process that uses an etchant comprising tetramethylammonium
hydroxide (TMAH), ammonium hydroxide (NH.sub.4OH), ethylenediamine
pyrocatechol (EDP), or potassium hydroxide (KOH).
[0027] In a representative embodiment in which the substrate 10 is
single crystal silicon having a [100] surface normal and the
trenches 29-32 in the device region 14 are aligned with a [100]
direction, the sidewalls 29a-32a are aligned with
crystallographically equivalent (110) planes before the anisotropic
etching process is performed. After a given timed etch, the
sidewalls 36-39 of the trenches 34, 35 may be inclined at a nominal
angle, .alpha., of 45.degree. relative to the top surface 10a.
[0028] The anisotropic etching process removes the semiconductor
material of the device region 14 of substrate 10 at a considerably
higher rate than the semiconductor material comprising at least a
portion of the intrinsic base layer 22 and at a considerably higher
rate than the electrical insulators comprising the base dielectric
layer 24 and trench isolation structures 12. In particular, the
intrinsic base layer 22 may be comprised of silicon that may
include a varying composition with germanium of various contents
over different thicknesses in a stepped and/or graded profile. For
example, a portion of the intrinsic base layer 22 adjacent to the
emitter 18 may be comprised of silicon without germanium and
another portion of the intrinsic base layer 22 separated from the
emitter 18 by the silicon portion may be comprised of
silicon-germanium. If the silicon portion has a higher etch rate
than the silicon-germanium portion during the anisotropic etching
process of the intrinsic base layer 22 and the silicon-germanium
portion is not etched or minimally etched, then the sections 90,
92, 94, 96 may reflect removal of the silicon portion and the
non-removal or minimal removal of the silicon-germanium portion.
Because of the etch selectivity, the sidewalls 29a-32a of trenches
29-32 each extending through the intrinsic base layer 22 may
nominally retain their original separation, and remain nominally
vertical and perpendicular to the top surface 10a.
[0029] Sections 90, 92 of the intrinsic base layer 22 are undercut
by the partial removal of the device region 14 and, depending on
the composition (e.g., silicon without added germanium over a
thickness adjacent to the collector 18), the partial removal of the
intrinsic base layer 22. The undercutting reduces the distance
between the interior sidewalls 37, 39 so that a width, w.sub.4, of
the emitter 18 laterally between the interior sidewalls 37, 39 and
proximate to the intrinsic base layer 22 is reduced in comparison
with the initial width, w.sub.3. Similarly, sections 94, 96 of the
intrinsic base layer 22 are undercut by the selective etching that
supplies the inclination of the interior sidewalls 36, 38. At least
a portion of the interior section 16 of the intrinsic base layer 22
retains the width, w.sub.1, which is greater than the width,
w.sub.4. Assuming equivalent lengths for the interior section 16 of
the intrinsic base layer 22 and the collector 18, then the area of
the interior section 16 of the intrinsic base layer 22 is larger
than the confronting area of the collector 18.
[0030] With reference to FIG. 4 in which like reference numerals
refer to like features in FIG. 3 and at a subsequent fabrication
stage of the processing method, isolation structures 42, 43
comprised of an electrical insulator are formed in the trenches 34,
35. To that end, a dielectric layer 40 is applied that fills the
trenches 34, 35 respective portions of the electrical insulator.
The dielectric layer 40 also deposits on the top surface 26a of the
sacrificial layer 26. The dielectric layer 40 may comprise any
suitable organic or inorganic dielectric material, which may be an
electrical insulator characterized by an electrical resistivity at
room temperature of greater than 10.sup.10 (.OMEGA.-m). Candidate
inorganic dielectric materials for dielectric layer 40 may include,
but are not limited to, silicon dioxide (SiO.sub.2), fluorine-doped
silicon glass (FSG), and combinations of these dielectric
materials. Alternatively, dielectric layer 40 may comprise a low-k
dielectric material characterized by a relative permittivity or
dielectric constant smaller than the SiO.sub.2 dielectric constant
of approximately 3.9. Candidate low-k dielectric materials for
dielectric layer 40 include, but are not limited to, porous and
nonporous spun-on organic low-k dielectrics, such as spin-on
spun-on aromatic thermoset polymer resins like polyarylenes, porous
and nonporous inorganic low-k dielectrics, such as organosilicate
glasses, hydrogen-enriched silicon oxycarbide (SiCOH), and
carbon-doped oxides, and combinations of these and other organic
and inorganic dielectrics.
[0031] Dielectric layer 40 may be deposited by any number of
techniques including, but not limited to, sputtering, spin-on
application, or CVD. In one specific embodiment, the dielectric
layer 40 may be comprised of an oxide of silicon (e.g., SiO.sub.2)
that may be deposited by low pressure chemical vapor phase
deposition (LPCVD) using a silicon source of either silane or a
mixture of silane with nitrogen. For example, the substrate
temperature during LPCVD may range from 600.degree. C. to
650.degree. C. and the process chamber pressure during LPCVD may be
constrained in a range between 25 Pa and 150 Pa.
[0032] In the representative embodiment, isolation structures 42,
43 may include subsurface voids 86, 88 that are introduced into the
constituent dielectric material during deposition. The voids 86, 88
operate to lower the composite dielectric constant of the
dielectric material comprising isolation structures 42, 43. The
voids 86, 88 each represent one or more empty spaces devoid of
solid matter. The voids 86, 88 may have an effective dielectric
constant of approximately unity (about 1.0) and may be filled by
air at or near atmospheric pressure, filled by another gas at or
near atmospheric pressure, or contain air or gas below atmospheric
pressure (e.g., a partial vacuum) in the completed microelectronic
structure. The voids 86, 88 are preferably buried at a depth within
the isolation structures 42, 43 and beneath the top surface 40a of
the dielectric layer 40 such that the voids 86, 88 remain sealed
during subsequent processing steps.
[0033] With reference to FIG. 5 in which like reference numerals
refer to like features in FIG. 4 and at a subsequent fabrication
stage of the processing method, the dielectric layer 40 is removed
from the top surface 26a of the sacrificial layer 26, but not from
within the trenches 34, 35, by a wet etching process or a dry
etching process that may be end-pointed based upon exposure of the
sacrificial layer 26 or may alternatively be timed. If the
dielectric layer 40 is comprised of an oxide of silicon, then RIE
or an oxide etch, such as buffered hydrofluoric acid or diluted
hydrofluoric acid, may be employed to remove the dielectric layer
40 from the top surface 26a of sacrificial layer 26. The isolation
structures 42, 43 of the dielectric layer 40 inside the trenches
34, 35 may be recessed relative to the top surface 26a of the
sacrificial layer 26 but are not removed by the etching
process.
[0034] The isolation structures 42, 43 reproduce the geometrical
shape of the trenches 34, 35 within the device region 14 and are
nominally identical to each other. Isolation structure 42 has a top
surface 42a, a bottom surface 42b, and sidewalls 44a, 44b that are
inclined at angle, .alpha.. Sidewall 44a is separated by the
section 33a of the device region 14 from the interior sidewall 13
of the adjacent trench isolation structure 12. The sidewalls 44a,
44b of isolation structure 42 diverge in a direction toward the top
surface 10a such that the width of the isolation structure 42
increases in a direction away from the bottom surface 42b.
Isolation structure 43 has a top surface 43a, a bottom surface 43b,
and sidewalls 45a, 45b that are inclined at angle, .alpha..
Sidewall 45a is separated by the section 33b of the device region
14 from the interior sidewall 13 of the adjacent trench isolation
structure 12. The sidewalls 45a, 45b of isolation structure 43
diverge in a direction toward the top surface 10a such that the
width of the isolation structure 43 increases in a direction away
from the bottom surface 43b. At or slightly above the top surface
10a, the collector 18 has the width w.sub.2 because of the inclined
sidewalls 44b, 45b. The inclination of the sidewalls 44b, 45b of
the isolation structures 42, 43 relative to the top surface 10a of
the device region 14 may operate to reduce a surface area of a top
surface of the emitter 18 relative to a surface area of a
contacting surface of a subsequently-formed intrinsic base that is
in direct contact with the emitter 18.
[0035] Isolation structures 42, 43 surround the emitter 18 and,
more specifically, sidewalls 44b, 45b are coextensive with (i.e.,
define a boundary of) the emitter 18. The trench isolation
structures 12 are not coextensive with the emitter 18 and, instead,
the isolation structures 42, 43 are laterally positioned between
the trench isolation structures 12 and the emitter 18. Hence, the
trench isolation structures 12 do not define the boundaries of the
emitter 18.
[0036] In one embodiment, the isolation structures 42, 43 may
comprise lengths of electrical insulator that are aligned parallel
to each other. In this embodiment, the isolation structures 42, 43
do not define a closed geometrical shape. In an alternative
embodiment, the isolation structures 42, 43 may join or may be
joined by additional trenches so that the isolation structures 42,
43 surround or encircle the interior portion of the emitter 18 to
form a closed geometrical shape.
[0037] The shallow trench isolation structures 12 extend to a
depth, d.sub.1, measured relative to the top surface 10a of the
substrate 10 and device region 14. The isolation structures 42, 43
and the trenches 34, 35 in which the isolation structures 42, 43
are formed extend to depth, d.sub.2, measured relative to the top
surface 10a of the substrate 10 and device region 14. The depth,
d.sub.2 is shallower than the depth, d.sub.1. The depth difference
facilitates the coupling of the sections 33a, 33b by the subemitter
20 with the emitter 18 as the subemitter 20 can extend laterally
beneath the isolation structures 42, 43 to provide the
coupling.
[0038] With reference to FIG. 6 in which like reference numerals
refer to like features in FIG. 5 and at a subsequent fabrication
stage of the processing method, the sacrificial layer 26 is removed
by, for example, a wet etching process or a dry etching process. In
particular, if the sacrificial layer 26 is comprised of
polysilicon, the sacrificial layer 26 may be partially or
completely removed by an etching process, such as a dry etching
process or a wet etching process (e.g., an aqueous mixture of
nitric acid (HNO.sub.3) and hydrofluoric acid (HF)). The base
dielectric layer 24 may operate as an etch stop for the removal of
the sacrificial layer 26 if the materials comprising the
sacrificial layer 26 and base dielectric layer 24 are selected such
that the sacrificial layer 26 can be selectively etched relative to
base dielectric layer 24. The base dielectric layer 24 is exposed
in field regions surrounding the trenches 29-32.
[0039] An extrinsic base layer 46 is formed on the top surface 24a
of the base dielectric layer 24. In one embodiment, the extrinsic
base layer 46 may be comprised of polycrystalline semiconductor
material (e.g., polysilicon or polycrystalline SiGe) deposited by
CVD process. If the extrinsic base layer 46 is comprised of SiGe,
the concentration of Ge may have a graded or an abrupt profile and
may include additional layers, such as a Si cap. The extrinsic base
layer 46 may be in situ doped with a concentration of a dopant,
such as an impurity species from Group III of the Periodic Table
(e.g., boron) effective to impart p-type conductivity. As a
consequence of the deposition process and the non-crystalline
nature of base dielectric layer 24 on which extrinsic base layer 46
is formed, the entire extrinsic base layer 46 is comprised of
polycrystalline or amorphous semiconductor material.
[0040] Dielectric layers 48, 50, 52 are then formed in a stack on
the extrinsic base layer 46. Dielectric layer 48, which is formed
on a top surface 46a of extrinsic base layer 46, may directly
contact the top surface 46a. Dielectric layer 50, which is formed
on a top surface 48a of dielectric layer 48, may directly contact
the top surface 48a. Dielectric layer 52, which is formed on a top
surface 50a of dielectric layer 50, may directly contact the top
surface 50a. Dielectric layer 48 and dielectric layer 52 may be
comprised of the same electrical insulator, such as SiO.sub.2
deposited by CVD. Dielectric layer 50 may be comprised of an
electrical insulator, such as silicon nitride (Si.sub.3N.sub.4)
deposited using CVD, characterized by a different etch selectivity
than dielectric layers 48, 52.
[0041] Dielectric layers 48, 50, 52 are patterned using
photolithography and etching processes to define an opening 54
aligned with the emitter 18. To that end, a patterned etch mask
(not shown) is applied to the dielectric layer 52. In one
embodiment, the etch mask may be a photoresist layer comprised of a
sacrificial organic material applied by spin coating to the top
surface 52a of dielectric layer 52. The photolithography process
that patterns the photoresist layer exposes the photoresist to
radiation imaged through a photomask and develops the resulting
latent feature pattern in the exposed photoresist to define a
window at the intended location for the opening 54. The etching
process, which may be RIE, forms the opening 54 in the dielectric
layers 48, 50, 52 by sequentially removing regions of each of the
dielectric layers 48, 50, 52 unprotected by the etch mask. The
etching process, which may be conducted in a single etching step or
multiple steps, relies on one or more etch chemistries that remove
the individual dielectric layers 48, 50, 52 and may comprise one or
more discrete timed or end-pointed etches.
[0042] The opening 54 is extended by a controlled etching process,
such as RIE, partially extended through the thickness of the
extrinsic base layer 46. After etching, the top surface 46a of
extrinsic base layer 46 is recessed (i.e., in a different plane)
relative to a plane containing the top surface 46a of the extrinsic
base layer 46 in masked regions. After the opening 54 is formed,
the etch mask is removed. If comprised of photoresist, the etch
mask may be removed by oxygen plasma ashing or chemical
stripping.
[0043] Spacers 56, 57 are formed on the vertical sidewalls of the
layers 46, 48, 50, 52 bounding the opening 54 and extend vertically
to the base of the opening 54. The spacers 56, 57 may directly
contact the recessed top surface 46a of extrinsic base layer 46.
The spacers 56, 57 may be formed by depositing a conformal layer
comprised of an electrical insulator, such as Si.sub.3N.sub.4
deposited by CVD, and shaping the conformal layer with an
anisotropic etching process, such as RIE, that preferentially
removes the electrical insulator from horizontal surfaces.
[0044] With reference to FIG. 7 in which like reference numerals
refer to like features in FIG. 6 and at a subsequent fabrication
stage of the processing method, the opening 54, as narrowed by the
presence of the spacers 56, 57, is extended in depth completely
through the raised region of extrinsic base layer 46 using an
anisotropic etching process, such as RIE. The etching process
removes the material of extrinsic base layer 46 selectively (e.g.,
at a higher etch rate) to the materials comprising the spacers 56,
57 and the base dielectric layer 24. The etching process stops on
the base dielectric layer 24. Unetched sections 47, 49 of extrinsic
base layer 46 remain adjacent to the opening 54 and beneath the
spacers 56, 57.
[0045] The opening 54 is then extended in depth through the base
dielectric layer 24 by an isotropic etching process, such as a wet
chemical etch, that stops on the intrinsic base layer 22. If the
base dielectric layer 24 is comprised of SiO.sub.2, the wet
chemical etching process may use either dilute hydrofluoric (DHF)
or buffered hydrofluoric (BHF) as an etchant. The removal of this
region of base dielectric layer 24 exposes the top surface 22a of
intrinsic base layer 22 over a portion of the interior section 16
and defines cavities between the sections 47, 49 of extrinsic base
layer 46 and the intrinsic base layer 22. The isotropic etching
process removes the material of base dielectric layer 24
selectively to the materials comprising the spacers 56, 57, the
extrinsic base layer 46, and the intrinsic base layer 22.
[0046] A semiconductor layer 58 is formed as an additive layer on
the top surface 22a of the intrinsic base layer 22 and, in the
representative embodiment, is directly formed on the top surface
22a. The semiconductor layer 58 may be comprised of semiconductor
material deposited or grown in an epitaxial relationship with the
intrinsic base layer 22. The semiconductor material comprising the
semiconductor layer 58 may be doped during or following deposition,
or may be alternatively undoped. The semiconductor layer 58 may
have a different composition than either the intrinsic base layer
22 or the extrinsic base layer 46. During the deposition process,
the semiconductor material of semiconductor layer 58 nucleates on
the semiconductor material of the intrinsic base layer 22 and
acquires the crystalline state of the intrinsic base layer 22.
Sections of the semiconductor layer 58 occupy the cavities between
the sections 47, 49 of extrinsic base layer 46 and the intrinsic
base layer 22. These sections define a link electrically and
physically coupling the intrinsic base layer 22 and the extrinsic
base layer 46 to provide a direct connection for current flow
between the extrinsic base layer 46 and the intrinsic base layer
22. The semiconductor layer 58 may be considered to comprise a
portion of the intrinsic base layer 22.
[0047] With reference to FIG. 8 in which like reference numerals
refer to like features in FIG. 7 and at a subsequent fabrication
stage of the processing method, spacers 70, 71 and spacers 72, 73
are formed on the spacers 56, 57 with spacers 72, 73 intervening
between spacers 70, 71 and spacers 56, 57. Spacers 72, 73 may be
comprised of a dielectric material that is electrically insulating,
such as SiO.sub.2. Spacers 70, 71 may likewise be comprised of a
dielectric material that is electrically insulating, such as
Si.sub.3N.sub.4.
[0048] A collector 74 of the bipolar junction transistor 80 is
formed inside the opening 54. The collector 74 may be formed from a
layer of semiconductor material that is deposited and then
patterned using lithography and etching processes. The lithography
process may utilize photoresist and photolithography to form an
etch mask that protects only a strip of the semiconductor material
registered with the opening 54. An etching process that stops on
the material of layer 50 is selected to fashion the collector 74
from the protected strip of semiconductor material. The etch mask
is subsequently removed.
[0049] The collector 74 at least partially occupies the opening 54
and, in the representative embodiment, fully occupies the opening
54. The collector 74 is electrically and physically coupled with
the intrinsic base layer 22 by the semiconductor layer 58. The
bottom part of the collector 74, which is located inside the
opening 54, directly contacts the top surface 58a of the
semiconductor layer 58 and indirectly contacts the top surface 22a
of intrinsic base layer 22 because the semiconductor layer 58
intervenes. As such, the collector 74 is at least partially above
the top surface 10a of the device region 14 and is preferably
entirely above the top surface 10a. A head of the collector 74
protrudes out of the opening 54 and includes lateral arms that
overlap with the top surface 50a of dielectric layer 50. The
non-conductive spacers 56, 57, and 70-73 encircle or surround the
collector 74 for electrically isolating the collector 74 from the
extrinsic base layer 46.
[0050] Dielectric layers 48, 50 are patterned using the same etch
mask used to form the collector 74, and an etching process, such as
RIE, with suitable etch chemistries. The etch mask is subsequently
removed. Layers 22, 24, 46 are then patterned with photolithography
and etching processes to define an extrinsic base 82 and an
intrinsic base 84 of the bipolar junction transistor 80 from the
extrinsic base layer 46 and intrinsic base layer 22 separated by a
section of the base dielectric layer 24. An etch mask is applied
for use in a patterning process that relies on an etching process,
such as RIE, with respective etch chemistries appropriate to etch
the layers 22, 24, 46. Following the etching process, the etch mask
is removed.
[0051] The collector 74 may be comprised of one or more layers of
semiconductor material selected to provide a given electronic
bandgap. In one embodiment, the collector 74 may be formed from a
wide bandgap semiconductor material having an electronic bandgap
larger than 1.1 electron volts (eV), which is the nominal
electronic bandgap of silicon, and less than or equal to 6.3 eV,
which is the nominal electronic bandgap of aluminum phosphide
(AlP). Representative semiconductor materials for the collector 74
include, but are not limited to, carbon-doped silicon (Si:C),
binary III-V semiconductors such as gallium phosphide (GaP) or AlP,
binary II-VI semiconductors such as zinc sulfide (ZnS), tertiary
III-V semiconductors such as gallium-arsenide-phosphide (GaAsP) or
aluminum-arsenide-phosphide (AlAsP), tertiary II-VI semiconductors
such as zinc-selenium-sulfide (ZnSeS) or zinc-magnesium-sulfide
(ZnMgS), and quaternary semiconductors. The bandgap of, for
example, tertiary III-V and II-VI semiconductors may be engineered
by selecting a composition and/or layering during heteroepitaxy and
may be influenced by strain incorporated into the lattice structure
due to lattice mismatch during heteroepitaxy. If the semiconductor
materials of device region 14 and semiconductor layer 58 are single
crystal silicon, then forming the collector 74 from AlP may provide
a close lattice constant match and promote heteroepitaxy.
[0052] The semiconductor material constituting the collector 74 may
comprise one or more layers of material formed by an epitaxial
growth process, such VPE or molecular beam epitaxy (MBE), such that
the semiconductor material constituting the collector 74 has an
epitaxial relationship with the semiconductor material of the
semiconductor layer 58 and with the semiconductor material of the
intrinsic base layer 22. In an embodiment in which the
semiconductor layer 58 is absent and the collector 74 directly
contacts the intrinsic base layer 22, the intrinsic base layer 22
establishes the crystalline template for the epitaxial growth.
[0053] Forming the collector 74 after the emitter 18 and intrinsic
base 84 provides the flexibility in material selection, and
contrasts with the limited ability to tailor the material in device
structures having the collector in the device region 14. The
bipolar junction transistor 80 comprises a heterojunction bipolar
transistor in which the semiconductor materials of the emitter 18,
intrinsic base 84, and collector 74 have different values of
electronic bandgap and, in particular, the electronic bandgap for
the semiconductor material of the collector 74 is greater than the
electronic bandgap of the semiconductor material of the substrate
10 and device region 14. In one embodiment, the electronic bandgap
of the collector 74 may be greater than 1.1 electron volts (eV) and
less than or equal to 6.3 eV, and the electronic bandgap of the
substrate 10 and device region 14 may be nominally equal to 1.1 eV.
In another embodiment, the substrate 10 and device region 14 may be
comprised of single crystal silicon with a nominal bandgap equal to
1.1 eV and the collector 74 may be comprised of a semiconductor
material other than silicon with a bandgap greater than 1.1 eV and
less than or equal to 6.3 eV. The wide bandgap semiconductor
material of the collector 74 may supply an enhanced breakdown
voltage for power devices in comparison with device constructions
in which the collector is formed in the device region 14.
[0054] The collector 74 is formed as a concluding step in the
representative process flow forming the bipolar junction transistor
80. As a result, the collector 74 can incorporate a higher
concentration of defects that is tolerable to the device
functionality as compared with collectors of conventional device
constructions which are formed using the substrate.
[0055] After patterning, the bipolar junction transistor 80 has a
vertical architecture in which the intrinsic base 84 is located
between the collector 74 and the emitter 18, and the collector 74,
the intrinsic base 84, and the emitter 18 are vertically arranged.
The conductivity types of the semiconductor material constituting
the collector 74 and the semiconductor materials constituting
extrinsic base 82 and intrinsic base 84 are opposite. One p-n
junction is defined at the interface between the collector 74 and
the intrinsic base 84. Another p-n junction is defined at the
interface between the emitter 18 and the intrinsic base 84.
[0056] The collector 74 is electrically and physically coupled with
the intrinsic base 84 by the semiconductor layer 58 across a
surface area that is not impacted by the inclination of the
respective interior sidewalls 44b, 45b of isolation structures 42,
43. The surface area across which the collector 74 is indirectly
coupled with the intrinsic base 84 may vary and be optimized
independent of the surface area across which the emitter 18 is
directly coupled with the intrinsic base 84. As a result, the
emitter 18 can have a critical dimension that is less than or equal
to the critical dimension of the collector 74. In one embodiment,
the surface area of a bottom surface of the intrinsic base 84 is
smaller than the coextensive area of a top surface of the emitter
18 due to the inclination of the sidewalls 44b, 45b of the
isolation structures 42, 43 relative to the top surface of the
device region 14.
[0057] During the front-end-of-line (FEOL) portion of the
fabrication process, the device structure of the bipolar junction
transistor 80 is replicated across at least a portion of the
surface area of the substrate 10. In BiCMOS integrated circuits,
complementary metal-oxide- semiconductor (CMOS) transistors (not
shown) may be formed using other regions of the substrate 10. As a
result, both bipolar and CMOS transistors may be available on the
same substrate 10.
[0058] Standard silicidation and standard back-end-of-line (BEOL)
processing follows, which includes formation of contacts and wiring
for the local interconnect structure, and formation of dielectric
layers, via plugs, and wiring for an interconnect structure coupled
by the interconnect wiring with the bipolar junction transistor 80,
as well as other similar contacts for additional device structures
like bipolar junction transistor 80 and CMOS transistors (not
shown) included in other circuitry fabricated on the substrate 10.
Other active and passive circuit elements, such as diodes,
resistors, capacitors, varactors, and inductors, may be fabricated
on substrate 10 and available for use in the BiCMOS integrated
circuit.
[0059] A contact 60 is coupled with the emitter 18 by the
subemitter 20 and sections 33a, 33b of the device region 14. The
presence of the isolation structures 42, 43 and sections 33a, 33b
of device region 14 permits the emitter 18 to be contacted inside
the sidewall 13 (i.e., the inner perimeter) of the trench isolation
structures 12. The extrinsic base 82 is contacted by a contact 62,
and the collector 74 is contacted by a contact 64.
[0060] FIG. 9 shows a block diagram of an exemplary design flow 100
used for example, in semiconductor IC logic design, simulation,
test, layout, and manufacture. Design flow 100 includes processes,
machines and/or mechanisms for processing design structures or
devices to generate logically or otherwise functionally equivalent
representations of the design structures and/or devices described
above and shown in FIG. 8. The design structures processed and/or
generated by design flow 100 may be encoded on machine-readable
transmission or storage media to include data and/or instructions
that when executed or otherwise processed on a data processing
system generate a logically, structurally, mechanically, or
otherwise functionally equivalent representation of hardware
components, circuits, devices, or systems. Machines include, but
are not limited to, any machine used in an IC design process, such
as designing, manufacturing, or simulating a circuit, component,
device, or system. For example, machines may include: lithography
machines, machines and/or equipment for generating masks (e.g.
e-beam writers), computers or equipment for simulating design
structures, any apparatus used in the manufacturing or test
process, or any machines for programming functionally equivalent
representations of the design structures into any medium (e.g. a
machine for programming a programmable gate array).
[0061] Design flow 100 may vary depending on the type of
representation being designed. For example, a design flow 100 for
building an application specific IC (ASIC) may differ from a design
flow 100 for designing a standard component or from a design flow
100 for instantiating the design into a programmable array, for
example a programmable gate array (PGA) or a field programmable
gate array (FPGA) offered by Altera.RTM. Inc. or Xilinx.RTM.
Inc.
[0062] FIG. 9 illustrates multiple such design structures including
an input design structure 102 that is preferably processed by a
design process 104. Design structure 102 may be a logical
simulation design structure generated and processed by design
process 104 to produce a logically equivalent functional
representation of a hardware device. Design structure 102 may also
or alternatively comprise data and/or program instructions that
when processed by design process 104, generate a functional
representation of the physical structure of a hardware device.
Whether representing functional and/or structural design features,
design structure 102 may be generated using electronic
computer-aided design (ECAD) such as implemented by a core
developer/designer. When encoded on a machine- readable data
transmission, gate array, or storage medium, design structure 102
may be accessed and processed by one or more hardware and/or
software modules within design process 104 to simulate or otherwise
functionally represent an electronic component, circuit, electronic
or logic module, apparatus, device, or system such as those shown
in FIG. 8. As such, design structure 102 may comprise files or
other data structures including human and/or machine-readable
source code, compiled structures, and computer-executable code
structures that when processed by a design or simulation data
processing system, functionally simulate or otherwise represent
circuits or other levels of hardware logic design. Such data
structures may include hardware-description language (HDL) design
entities or other data structures conforming to and/or compatible
with lower-level HDL design languages such as Verilog and VHDL,
and/or higher level design languages such as C or C++.
[0063] Design process 104 preferably employs and incorporates
hardware and/or software modules for synthesizing, translating, or
otherwise processing a design/simulation functional equivalent of
the components, circuits, devices, or logic structures shown in
FIG. 8 to generate a netlist 106 which may contain design
structures such as design structure 102. Netlist 106 may comprise,
for example, compiled or otherwise processed data structures
representing a list of wires, discrete components, logic gates,
control circuits, I/O devices, models, etc. that describes the
connections to other elements and circuits in an integrated circuit
design. Netlist 106 may be synthesized using an iterative process
in which netlist 106 is resynthesized one or more times depending
on design specifications and parameters for the device. As with
other design structure types described herein, netlist 106 may be
recorded on a machine-readable data storage medium or programmed
into a programmable gate array. The medium may be a non-volatile
storage medium such as a magnetic or optical disk drive, a
programmable gate array, a compact flash, or other flash memory.
Additionally, or in the alternative, the medium may be a system or
cache memory, buffer space, or electrically or optically conductive
devices and materials on which data packets may be transmitted and
intermediately stored via the Internet, or other networking
suitable means.
[0064] Design process 104 may include hardware and software modules
for processing a variety of input data structure types including
netlist 106. Such data structure types may reside, for example,
within library elements 108 and include a set of commonly used
elements, circuits, and devices, including models, layouts, and
symbolic representations, for a given manufacturing technology
(e.g., different technology nodes, 32 nm, 45 nm, 90 nm, etc.). The
data structure types may further include design specifications 110,
characterization data 112, verification data 114, design rules 116,
and test data files 118 which may include input test patterns,
output test results, and other testing information. Design process
104 may further include, for example, standard mechanical design
processes such as stress analysis, thermal analysis, mechanical
event simulation, process simulation for operations such as
casting, molding, and die press forming, etc. One of ordinary skill
in the art of mechanical design can appreciate the extent of
possible mechanical design tools and applications used in design
process 104 without deviating from the scope and spirit of the
invention. Design process 104 may also include modules for
performing standard circuit design processes such as timing
analysis, verification, design rule checking, place and route
operations, etc.
[0065] Design process 104 employs and incorporates logic and
physical design tools such as HDL compilers and simulation model
build tools to process design structure 102 together with some or
all of the depicted supporting data structures along with any
additional mechanical design or data (if applicable), to generate a
second design structure 120. Design structure 120 resides on a
storage medium or programmable gate array in a data format used for
the exchange of data of mechanical devices and structures (e.g.
information stored in an IGES, DXF, Parasolid XT, JT, DRG, or any
other suitable format for storing or rendering such mechanical
design structures). Similar to design structure 102, design
structure 120 preferably comprises one or more files, data
structures, or other computer-encoded data or instructions that
reside on transmission or data storage media and that when
processed by an ECAD system generate a logically or otherwise
functionally equivalent form of one or more of the embodiments of
the invention shown in FIG. 8. In one embodiment, design structure
120 may comprise a compiled, executable HDL simulation model that
functionally simulates the devices shown in FIG. 8.
[0066] Design structure 120 may also employ a data format used for
the exchange of layout data of integrated circuits and/or symbolic
data format (e.g. information stored in a GDSII (GDS2), GL1, OASIS,
map files, or any other suitable format for storing such design
data structures). Design structure 120 may comprise information
such as, for example, symbolic data, map files, test data files,
design content files, manufacturing data, layout parameters, wires,
levels of metal, vias, shapes, data for routing through the
manufacturing line, and any other data required by a manufacturer
or other designer/developer to produce a device or structure as
described above and shown in FIG. 8. Design structure 120 may then
proceed to a stage 122 where, for example, design structure 120:
proceeds to tape-out, is released to manufacturing, is released to
a mask house, is sent to another design house, is sent back to the
customer, etc.
[0067] The method as described above is used in the fabrication of
integrated circuit chips. The resulting integrated circuit chips
can be distributed by the fabricator in raw wafer form (that is, as
a single wafer that has multiple unpackaged chips), as a bare die,
or in a packaged form. In the latter case, the chip is mounted in a
single chip package (such as a plastic carrier, with leads that are
affixed to a motherboard or other higher level carrier) or in a
multichip package (such as a ceramic carrier that has either or
both surface interconnections or buried interconnections). In any
case the chip is then integrated with other chips, discrete circuit
elements, and/or other signal processing devices as part of either
(a) an intermediate product, such as a motherboard, or (b) an end
product. The end product can be any product that includes
integrated circuit chips, ranging from toys and other low-end
applications to advanced computer products having a display, a
keyboard or other input device, and a central processor.
[0068] It will be understood that when an element is described as
being "connected" or "coupled" to or with another element, it can
be directly connected or coupled to the other element or, instead,
one or more intervening elements may be present. In contrast, when
an element is described as being "directly connected" or "directly
coupled" to another element, there are no intervening elements
present. When an element is described as being "indirectly
connected" or "indirectly coupled" to another element, there is at
least one intervening element present.
[0069] The terminology used herein is for the purpose of describing
particular embodiments only and is not intended to be limiting of
the invention. As used herein, the singular forms "a", "an" and
"the" are intended to include the plural forms as well, unless the
context clearly indicates otherwise. It will be further understood
that the terms "comprises" and/or "comprising," when used in this
specification, specify the presence of stated features, integers,
steps, operations, elements, and/or components, but do not preclude
the presence or addition of one or more other features, integers,
steps, operations, elements, components, and/or groups thereof.
[0070] The descriptions of the various embodiments of the present
invention have been presented for purposes of illustration, but are
not intended to be exhaustive or limited to the embodiments
disclosed. Many modifications and variations will be apparent to
those of ordinary skill in the art without departing from the scope
and spirit of the described embodiments. The terminology used
herein was chosen to best explain the principles of the
embodiments, the practical application or technical improvement
over technologies found in the marketplace, or to enable others of
ordinary skill in the art to understand the embodiments disclosed
herein.
* * * * *