U.S. patent application number 14/221431 was filed with the patent office on 2014-07-24 for printed wiring board having metal layers producing eutectic reaction.
This patent application is currently assigned to FUJITSU LIMITED. The applicant listed for this patent is FUJITSU LIMITED. Invention is credited to Taiji Sakai, Seiki Sakuyama.
Application Number | 20140202739 14/221431 |
Document ID | / |
Family ID | 41254854 |
Filed Date | 2014-07-24 |
United States Patent
Application |
20140202739 |
Kind Code |
A1 |
Sakai; Taiji ; et
al. |
July 24, 2014 |
PRINTED WIRING BOARD HAVING METAL LAYERS PRODUCING EUTECTIC
REACTION
Abstract
A printed wiring board includes a Cu wiring pattern formed on a
substrate. A first metal layer is formed on the Cu wiring pattern.
A second metal layer is formed on the first metal layer. The first
metal layer has a less reactivity with Cu than the second metal
layer. The first metal layer and the second metal layer together
cause an eutectic reaction.
Inventors: |
Sakai; Taiji; (Kawasaki-shi,
JP) ; Sakuyama; Seiki; (Kawasaki-shi, JP) |
|
Applicant: |
Name |
City |
State |
Country |
Type |
FUJITSU LIMITED |
Kawasaki-shi |
|
JP |
|
|
Assignee: |
FUJITSU LIMITED
Kawasaki-shi
JP
|
Family ID: |
41254854 |
Appl. No.: |
14/221431 |
Filed: |
March 21, 2014 |
Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
|
|
12908404 |
Oct 20, 2010 |
8713792 |
|
|
14221431 |
|
|
|
|
PCT/JP2008/058427 |
May 2, 2008 |
|
|
|
12908404 |
|
|
|
|
Current U.S.
Class: |
174/251 ;
228/180.21 |
Current CPC
Class: |
H01L 24/81 20130101;
H01L 2924/01082 20130101; H05K 2203/072 20130101; H01L 2924/01029
20130101; H01L 2924/01074 20130101; H01L 2924/01047 20130101; Y10T
29/49117 20150115; Y10T 29/49124 20150115; H01L 2924/014 20130101;
H05K 3/3436 20130101; H01L 23/49866 20130101; H01L 2924/30105
20130101; H01L 24/16 20130101; H01L 2924/01079 20130101; H01L
2924/01004 20130101; H01L 2924/01322 20130101; H05K 1/0298
20130101; Y10T 29/49128 20150115; H01L 2224/81815 20130101; H01L
2924/01049 20130101; H01L 2924/01006 20130101; H01L 2924/01027
20130101; H01L 2924/01005 20130101; Y10T 29/49139 20150115; H01L
2924/01019 20130101; H01L 2924/01033 20130101; H05K 13/0465
20130101; H05K 3/3473 20130101; H01L 23/49822 20130101; Y10T
29/49149 20150115; H05K 2201/10674 20130101; H01L 2224/81097
20130101; H01L 2224/13099 20130101; H01L 2924/01055 20130101; H01L
2924/0105 20130101; Y10T 29/49155 20150115; H01L 2924/01327
20130101; H01L 2924/01078 20130101 |
Class at
Publication: |
174/251 ;
228/180.21 |
International
Class: |
H05K 1/02 20060101
H05K001/02; H05K 13/04 20060101 H05K013/04 |
Claims
1. A printed wiring board comprising: a substrate; a Cu wiring
pattern formed over said substrate; a first metal layer formed on
said Cu wiring pattern; a second metal layer formed on said first
metal layer, wherein said first metal layer has a less reactivity
with Cu than said second metal layer, and said first metal layer
and said second metal layer together cause an eutectic
reaction.
2. The printed wiring board according to claim 1, wherein said
second metal layer forms an intermetallic compound with Cu, and
said first metal layer does not form an intermetallic compound with
Cu.
3. The printed wiring board according to claim 1, wherein said
eutectic reaction is produced in a temperature range from
139.degree. C. to 150.degree. C.
4. The printed wiring board according to claim 1, wherein said
first metal layer is made of a metal element selected from a group
consisting of bismuth, lead, indium and silver or an alloy
containing one of bismuth, lead, indium and silver as a major
component, and said second metal layer is made of a metal element
selected from a group consisting of tin and gold or an alloy
containing one of tin and gold as a major component.
5. The printed wiring board according to claim 1, wherein said Cu
wiring pattern includes a first interface area along an interface
between said first metal layer and said Cu wiring layer, the first
interface area containing the metal element forming said second
metal layer; and said second metal layer includes a second
interface area along an interface between said first metal layer
and said second metal layer, the second interface area containing
Cu.
6. A manufacturing method of an electronic device, comprising:
placing said electronic device on a printed wiring board according
to claim 1 so that terminals of said electronic device are brought
into contact with said second metal layer; and reflowing said first
and second metal layers to join said terminals of said electronic
device to said Cu wiring pattern.
Description
CROSS-REFERENCE TO RELATED APPLICATIONS
[0001] This is a divisional of U.S. application Ser. No. 12/908,404
filed Oct. 20, 2010 which is a U.S. continuation application, filed
under 35 USC 111(a) and claiming the benefit under 35 USC 120 and
365(c), of PCT application JP2008/058427 filed May 2, 2008. The
foregoing application is hereby incorporated herein by
reference.
FIELD
[0002] The embodiment discussed herein is directed to a printed
wiring board used in electronic equipments and a manufacturing
method of such a printed wiring board.
BACKGROUND
[0003] In recent electronic equipments including a cellular phone,
a digital camera, etc., a severe demand is placed in speeding up an
operation. In order to satisfy such a demand, it is required to use
a so-called low-K material such as a porous silica for an
interlayer insulating material of a semiconductor chip in order to
reduce a parasitic capacitance generated between wiring
patterns.
[0004] However, a low-K material is generally a mechanically
brittle material, and tends to receive a damage due to a thermal
strain generated during a joining process of a semiconductor chip.
For example, a porous silica has a modulus of elasticity of 4 GPa
to 8 GPa and, thereby, a mechanical strength of the porous silica
is smaller than that of conventionally used interlayer insulating
materials.
[0005] For this reason, a joining process to join a semiconductor
chip using such a low-K material is performed at a low temperature
in order to reduce a thermal strain generated in a substrate during
the joining process. However, because a conventionally used
lead-free solder requires a joining temperature of 217.degree. C.
or higher, it has been difficult to mount a semiconductor chip, in
which a low-K material is used, on a printed wiring board.
[0006] In view of such a situation, Japanese Laid-Open Patent
Application No. 2001-274201 suggests a technique to form a solder
layer on a Cu wiring pattern on a printed wiring board, the solder
layer having a lamination structure in which a tin (Sn) layer and a
bismuth (Bi) layer are stacked sequentially. According to such a
technique, it is considered that the solder layer fuses at a
temperature of 139.degree. C. according to an eutectic reaction of
Sn and Bi, which enables joining a device such as a semiconductor
chip or the like to connection electrodes at a low temperature.
[0007] Japanese Laid-Open Patent Application No. 2003-174252 also
discloses a technique similar to the technique suggested in
Japanese Laid-Open Patent application No. 2001-274201.
[0008] In the printed wiring board having an Sn layer directly
formed on a Cu layer, Sn atoms in the Sn layer move into the Cu
layer due to diffusion during a plated film producing process to
form the Sn layer, which may cause a problem in that an
intermetallic compound Cu.sub.6Sn.sub.5 is formed in a Cu electrode
pad. As a result of formation of such an intermetallic compound,
the Sn layer, which is formed on the Cu electrode pad, is consumed.
Thus, even if a Bi layer is formed on the Cu electrode pad, the
desired eutectic reaction cannot be produced.
[0009] In order to eliminate such a problem, according to the
technique suggested in the above-mentioned patent document, it is
required to set the film thickness of the Sn layer formed on the Cu
layer large enough so that a depletion of Sn atoms does not occur
and the Sn layer remains on the Cu electrode pad even if a large
amount of Sn atoms are moved into the Cu electrode pad. However,
according to such a structure, the film thickness of the Sn layer
must be increased, which may cause a problem in that
short-circuiting occurs between adjacent electrode pads through a
thick solder layer when forming minute patterns with fine
pitches.
SUMMARY
[0010] According to an aspect of the invention, a printed wiring
board includes: a substrate; a Cu wiring pattern formed over the
substrate; a first metal layer formed on the Cu wiring pattern; a
second metal layer formed on the first metal layer, wherein the
first metal layer has a less reactivity with Cu than the second
metal layer, and the first metal layer and the second metal layer
together cause an eutectic reaction.
[0011] According to another aspect of the invention, a
manufacturing method of an electronic device, includes: placing the
electronic device on the above-mentioned printed wiring board so
that terminals of the electronic device are brought into contact
with the second metal layer; and reflowing the first and second
metal layers to join the terminals of the electronic device to the
Cu wiring pattern.
[0012] According to a further aspect of the invention, a
manufacturing method of a printed wiring board includes: forming a
first metal layer on a Cu wiring pattern formed on a substrate;
forming a second metal layer on the first metal layer, the second
metal layer producing an eutectic reaction with the first metal
layer; and reflowing the first and second metal layers to produce
the eutectic reaction between the first and second metal layers,
wherein the first metal layer has a less reactivity with Cu than
the second metal layer.
[0013] The object and advantages of the embodiment will be realized
and attained by means of the elements and combinations particularly
pointed out in the appended claims.
[0014] It is to be understood that both the foregoing general
description and the following detailed description are exemplary
explanatory only and are not restrictive of the invention, as
claimed.
BRIEF DESCRIPTION OF DRAWINGS
[0015] FIG. 1 is a cross-sectional view of a part of a printed
wiring board according to a first embodiment;
[0016] FIG. 2A is a cross-sectional view for explaining a
manufacturing process of the printed wiring board illustrated in
FIG. 1;
[0017] FIG. 2B is a cross-sectional view for explaining a
manufacturing process of the printed wiring board illustrated in
FIG. 1;
[0018] FIG. 2C is a cross-sectional view for explaining a
manufacturing process of the printed wiring board illustrated in
FIG. 1;
[0019] FIG. 3 is an enlarged cross-sectional view of a part of FIG.
2B;
[0020] FIG. 4 is an enlarged cross-sectional view of a part of FIG.
2C;
[0021] FIG. 5A is an illustration illustrating a Sn--Bi eutectic
solder formed on a Cu pattern;
[0022] FIG. 5B is an illustration illustrating a Sn--Bi eutectic
solder formed on a Cu pattern;
[0023] FIG. 5C is an illustration illustrating a Sn--Bi eutectic
solder formed on a Cu pattern;
[0024] FIG. 6A is a cross-sectional view for explaining a process
of mounting a semiconductor chip to the printed wiring board
illustrated in FIG. 2C;
[0025] FIG. 6B is a cross-sectional view for explaining a process
of mounting a semiconductor chip to the printed wiring board
illustrated in FIG. 2C;
[0026] FIG. 7 is a graph indicating a temperature change curve used
in the first embodiment;
[0027] FIG. 8 is a cross-sectional view of a part of a printed
wiring board according to a variation of the first embodiment;
[0028] FIG. 9A is a cross-sectional view for explaining a first
process of manufacturing a printed wiring board according to a
second embodiment;
[0029] FIG. 9B is a cross-sectional view for explaining a second
process of manufacturing the printed wiring board according to the
second embodiment;
[0030] FIG. 9C is a cross-sectional view for explaining a third
process of manufacturing the printed wiring board according to the
second embodiment;
[0031] FIG. 9D is a cross-sectional view for explaining a fourth
process of manufacturing the printed wiring board according to the
second embodiment;
[0032] FIG. 9E is a cross-sectional view for explaining a fifth
process of manufacturing the printed wiring board according to the
second embodiment;
[0033] FIG. 9F is a cross-sectional view for explaining a sixth
process of manufacturing the printed wiring board according to the
second embodiment;
[0034] FIG. 10A is a cross-sectional view for explaining a first
process of manufacturing a printed wiring board according to a
third embodiment;
[0035] FIG. 10B is a cross-sectional view for explaining a second
process of manufacturing the printed wiring board according to the
third embodiment;
[0036] FIG. 10C is a cross-sectional view for explaining a third
process of manufacturing the printed wiring board according to the
third embodiment;
[0037] FIG. 10D is a cross-sectional view for explaining a fourth
process of manufacturing the printed wiring board according to the
third embodiment;
[0038] FIG. 10E is a cross-sectional view for explaining a fifth
process of manufacturing the printed wiring board according to the
third embodiment;
[0039] FIG. 10F is a cross-sectional view for explaining a sixth
process of manufacturing the printed wiring board according to the
third embodiment;
[0040] FIG. 10G is a plan view for explaining a seventh process of
manufacturing the printed wiring board according to the third
embodiment;
[0041] FIG. 10H is a cross-sectional view taken along a line A-B of
FIG. 10G;
[0042] FIG. 10I is a cross-sectional view taken along a line C-D of
FIG. 10G;
[0043] FIG. 10J is a plan view for explaining an eighth process of
manufacturing the printed wiring board according to the third
embodiment;
[0044] FIG. 10K is a cross-sectional view taken along a line A-B of
FIG. 10J; and
[0045] FIG. 10L is a cross-sectional view taken along a line C-D of
FIG. 10J.
DESCRIPTION OF EMBODIMENT(S)
[0046] Embodiments of the present invention will be explained with
reference to the accompanying drawings.
[0047] FIG. 1 illustrates a printed wiring board according to a
first embodiment. The printed wiring board 10 illustrated in FIG. 1
includes a substrate 11 formed of an epoxy resin material. Cu
wiring patterns 11A and 11B are formed on the substrate 11.
[0048] Each of the Cu wiring patterns forms an electrode pad.
Hereinafter, the Cu wiring patterns 11A and 11B may be referred to
as Cu electrode pads 11A and 11B, respectively. Solder layers 12A
and 12B are formed on the Cu electrode pads 11A and 11B,
respectively. Each of the solder layers 12A and 12B has a Sn/Bi
lamination structure in which a bismuth (Bi) layer 12 and a tin
(Sn) layer 13 are stacked in that order.
[0049] In the above-mentioned structure, the Bi layer 12 directly
contacts with the Cu electrode pads 11A or 11B. Because bismuth
(Bi) does not form an intermetallic compound with copper (Cu), an
amount of Bi atoms diffused into the Cu electrode pads 11A and 11B
is negligibly small. Thus, there is no situation happens in that
the Bi layer 12 is depleted. Thus, when the Sn layer 13 is formed
on the Bi layer 12, the Bi layer 12 and the Sn layer 13 surely
produce an eutectic reaction due to heat applied in a reflowing
process, and, thereby, the solder layers 12A and 12B can fuse
surely at a temperature below 200.degree. C.
[0050] In the present embodiment, as illustrated in FIG. 2A, the Cu
wiring layers forming the Cu electrode pads 11A and 11B are formed
on the substrate 11 with a pitch of 25 .mu.m according to an
electroless plating method or an electrolytic plating method using
a resist pattern. A width of each of the Cu electrode pads 11A and
11B is set to 20 .mu.m. As a result, an interval G between the Cu
electrode pads 11A and 11B is 5 .mu.m.
[0051] In the process illustrated in FIG. 2A, the Cu electrode pads
11A and 11B formed on the substrate 11 are washed with a 10%
sulfuric acid solution for 30 seconds, and, then, washed with pure
water for 30 seconds, and, thereafter, dried in a dry nitrogen
atmosphere.
[0052] Then, the thus-obtained electrode structure is subjected to
a Bi plating process using Bi electroless plating in order to form
the Bi layer 12 having an average film thickness of about 1 .mu.m
on surfaces of each of the Cu electrode pads 11A and 11B as
illustrated in FIG. 2B. Hereinafter, the Bi layer 12 may be
referred as a Bi-plated layer 12.
[0053] However, in the process illustrated in FIG. 2B, a
substitution reaction in the electroless plating does not occur at
a high rate on the surfaces of the Cu electrode pads 11A and 11B.
For this reason, the Bi-plated layer 12 is not deposited uniformly
on the surfaces of the Cu electrode pads 11A and 11B, and the
Bi-plated layer 12 is deposited in an islet form as illustrated in
FIG. 3. The thus-deposited Bi-plating layer 12 includes islands
each having a size of 2 .mu.m to 5 .mu.m. It should be noted that
FIG. 3 is an enlarged illustration of a part of the surface of the
Cu electrode pads 11A or 11B illustrated in FIG. 2B.
[0054] In the Bi electroless plating process illustrated in FIG.
2B, the Bi-plated layer 12 is formed by electroless plating at
70.degree. C. for 5 minutes using an electroless plating solution,
which contains 1 to 10 g/L of bismuth nitrate, 5 to 60 g/L of
thiocarbonic acid and 5 to 10 g/L of nitric acid. According to the
above-mentioned plating condition, the Bi-plated layer 12 can be
formed to cover about 60% of the surface area of each of the Cu
electrode pads 11A and 11B.
[0055] Subsequent to the electroless plating process of the
Bi-plated layer 12, the electrode structure illustrated in FIG. 2B
is washed with pure water for 30 seconds. Then, the surfaces of the
Cu electrode pads 11A and 11B are washed with a 10% sulfuric acid
solution for 20 seconds, and, then, washed with pure water for 30
seconds.
[0056] Subsequently, in the process of FIG. 2C, the Sn layer 13
(hereinafter, may be referred to as Sn-plated layer 13) is formed
with a film thickness of about 1 .mu.m on the thus-washed electrode
structure by an Sn electroless plating, which results in formation
of the printed wiring board 10 having the laminated solder layers
12A and 12B as illustrated in FIG. 1. For example, in the process
of FIG. 2C, the Sn-plated layer 13 is formed by electroless plating
at 70.degree. C. for 10 minutes using an electroless plating
solution, which contains 20 g/L of SnCl.sub.2, 70 g/L of
CS(NH.sub.2).sub.2, 50 g/L of hydrochloric acid, 15 g/L of
NaHPO.sub.2.2H.sub.2O, and 0.5 g/L of surfactant.
[0057] Consequently, as illustrated in FIG. 4, the Sn-plated layer
13 is formed on the Cu electrode pads 11A and 11B to cover the
island-formed Bi-plated layer 12. In the present embodiment, the
Sn-plated layer 13 is formed with the same film thickness as the
Bi-plated layer 12 in consideration of the eutectic composition
(Sn42 wt %-Bi58 wt %).
[0058] Although the thus-formed Sn-plated layer 13 is partly in
contact with the Cu electrode pad 11A or 11B as illustrated in FIG.
4, the area of the contact part is relatively small. Thus, when the
laminated solder layers 12A and 12B in the electrode structure
illustrated in FIG. 2C are subject to a reflowing process, it is
possible to cause an effective eutectic reaction to be produced
between the Bi-plated layer 12 and the Sn-plated layer 13.
[0059] FIGS. 5A through 5C illustrates results of experiments of
reflowing by applying heat to a sample containing a solder layer in
which a Bi-plated layer and a Sn-plated layer are laminated as the
same as the printed wiring board 10 of FIG. 1. In the sample
illustrated in FIGS. 5A through 5C, the Bi-plated layer and the
Sn-plated layer were formed on a circular Cu pattern by the process
of FIGS. 2A through 2C.
[0060] In the experiments, the Bi-plated layer was directly formed
on the Cu pattern with an average film thickness of about 1.0
.mu.m, and the Sn-plated layer was formed on the Bi-plated layer
with an average film thickness of about 0.7 .mu.m. In the
experiments, a flux of an RMA-type flux was applied to the surface
of the sample and the sample was heated at a heating rate of
2.degree. C./min.
[0061] Although FIG. 5A illustrates the state of the sample surface
at a time when the sample temperature reached 130.degree. C., there
was no change in the state of the sample surface from a time of
start heating.
[0062] On the other hand, FIG. 5B illustrates the state of the
sample surface at a time when the sample temperature reached
140.degree. C., which slightly exceeds the Sn--Bi eutectic
temperature of 139.degree. C. Referring to FIG. 5B, it is
appreciated that melting occurred in the solder layer covering the
surface, which results in bright white portions appearing in the
sample surface.
[0063] FIG. 5C illustrates the state of the sample surface at the
time when the sample temperature was raised up to 150.degree. C. It
is appreciated that the melting of the solder layer had been
continuously occurred.
[0064] According to the above-mentioned experiments, it was found
that melting occurs in the solder layers 12A and 12B of the
Bi-plated layer 12 and the Sn-plated layer 13 at the temperature of
140.degree. C. Thus, it was confirmed that Sn atoms are effectively
prevented from being diffused into the Cu electrode pad 11A or 11B
in a large part of the Sn-plated layer 13 and the melting occurs
near the eutectic temperature of 139.degree. C. even if a part of
the Sn-plated layer 13 is in direct contact with the Cu electrode
pads 11A or 11B as illustrated in FIGS. 3 and 4. It is considered
that this is an effect of the Bi-plated layer 12 being interposed
between the Sn-plated layer 13 and the Cu electrode pad 11A or
11B.
[0065] The following Table 1 indicates results of comparison
between the sample according to the structure of FIG. 1 of the
present embodiment and comparison samples. The samples No. 1
through No. 3 are comparison samples corresponding to a
conventional structure in which the order of the Bi-plated layer 12
and the Sn-plated layer 13 are changed. The sample No. 4
corresponds to the structure illustrated in FIG. 1 according to the
present embodiment. The samples No. 5 and No. 6 are comparison
samples in which the thicknesses of the Bi-plated layer 12 and the
Sn-plated layer 13 are varied. In the samples No. 1 through No. 6,
the Cu electrode pads 11A and 11B having a width W of 20 .mu.m are
arranged at an interval of 5 .mu.m. Indicated in the Table 1 are
whether a SnCu diffusion such as an intermetallic compound
Cu.sub.6Sn.sub.5 is formed in a state immediately after the
formation of the Sn-plated layer 13, whether the solder layers 12A
and 12B are fused in a state after a reflowing process at
180.degree. C. is carried out, and whether short-circuiting occurs
between the adjacent Cu electrode pads 11A and 11B.
TABLE-US-00001 TABLE 1 SHORT- CIRCUIT FIRST METAL SECOND METAL SnCu
BETWEEN KIND OF FILM KIND OF FILM DIFFUSION SnBi ADJACENT METAL
THICKNESS METAL THICKNESS LAYER FUSION ELECTRODES 1 Sn 1 .mu.m Bi 1
.mu.m 1 .mu.m X NO 2 Sn 2 .mu.m Bi 1 .mu.m 1.5 .mu.m .DELTA. YES 3
Sn 3 .mu.m Bi 1 .mu.m 1.5 .mu.m .largecircle. YES 4 Bi 1 .mu.m Sn 1
.mu.m 0 .mu.m .largecircle. NO 5 Bi 2 .mu.m Sn 1 .mu.m 0 .mu.m
.largecircle. YES 6 Bi 3 .mu.m Sn 1 .mu.m 0 .mu.m .largecircle.
YES
[0066] With reference to Table 1, in the reference sample No. 1, Sn
atoms are spread into a range of about 1 .mu.m thickness from the
front surface of the Cu electrode pads 11A and 11B simultaneously
with the electroless plating film deposition, which results in
formation of the intermetallic compound Cu.sub.6Sn.sub.5.
Accordingly, the Sn layer is depleted on the surfaces of the Cu
electrode pads 11A and 11B. As a result, if a reflowing process is
performed after forming a Bi layer, the solder layers on the Cu
electrode pads 11A and 11B cannot be meted.
[0067] On the other hand, if the film thickness of the Sn-plated
layer is increased such as in the reference samples No. 2 and No.
3, the Sn layer remains and the solder layer can be melted.
However, because the film thickness of the Sn-plated layer is
increased, short-circuiting occurs between the adjacent Cu
electrode pads 11A and 11B. In Table 1, "x" indicates that melting
did not occur in the solder layer, ".DELTA." indicates an
incomplete melting occurred, and ".largecircle." indicates that a
complete melting occurred.
[0068] On the other hand, the formation of an intermetallic
compound after the electroless plating process is not recognized in
the structure of the present embodiment in which the Bi-plated
layer and the Sn-plated layer are formed on the Cu electrode pads
11A and 11B. Thus, it is appreciated that the solder layers on the
Cu electrode pads 11A and 11B are surely melted.
[0069] However, if the film thickness of the Sn-plated layer 13 is
increased, short-circuiting occurs between the adjacent Cu
electrode pads 11A and 11B. Thus, it is desirable to set the film
thickness of the Sn-plated layer 13 to about 1 .mu.m.
[0070] It should be noted that the electroless plating process to
form the Bi-plated layer 12 illustrated in FIG. 2B may be performed
by electroless plating at 40.degree. C. using an electroless
plating solution containing 30 g/L of BiCl.sub.3, 100 g/L of
C.sub.5H.sub.5O.sub.7Na.sub.3.2H.sub.2O, 30 g/L of
C.sub.10H.sub.14Na.sub.2O.sub.3.2H.sub.2O, 40 g/L of
N(CH.sub.2COOH).sub.3 and 5 g/L of SnCl.sub.2.2H.sub.2O.
[0071] Furthermore, according to the present embodiment, by
flip-chip mounting the semiconductor chip 31, as illustrated in
FIG. 6A, on the printed wiring board 10 of FIG. 1 and performing a
reflowing process according to a temperature change curve
illustrated in FIG. 7, melting of the solder layers 12A and 12B is
induced at a temperature below 200.degree. C. in order to
manufacture the electronic device 30 in which the semiconductor
chip 31 is mounted as illustrated in FIG. 6B. In FIG. 6B, as a
result of the reflowing process, the solder layers 12A and 12B are
changed into a Sn--Bi alloy solder layer 12Eu of an eutectic
composition or a composition close to the eutectic composition. As
a result, the electrode pads 31A and 31B on the bottom surface of
the semiconductor chip 31 can be joined to the Cu electrode pads
11A and 11B, respectively, at a temperature below 200.degree.
C.
[0072] According to the temperature change curve illustrated in
FIG. 7, the maximum temperature is below 200.degree. C. Thus, a
semiconductor chip is prevented from being damaged even if a porous
low-dielectric constant material is used as an interlayer
insulating material of the semiconductor chip. Additionally,
according to the temperature change curve illustrated in FIG. 7,
the maximum temperature is higher than 139.degree. C., which is an
eutectic temperature of an Sn--Bi alloy. Thereby, the solder layer
can be surely melted even if an amount ratio of the Bi-plated layer
12 and the Sn-plated layer 13 is slightly shifted from that of the
eutectic composition.
[0073] Moreover, as illustrated in FIG. 8, it is possible to form a
printed wiring board 10A in which the solder layers 12A and 12B are
changed into the Sn--Bi alloy solder layer 12Eu in the printed
wiring board 10 of FIG. 1.
[0074] A description will be given below of a second
embodiment.
[0075] FIGS. 9A through 9F are cross-sectional views for explaining
a manufacturing process of a printed wiring board according to a
second embodiment. In FIGS. 9A through 9F, parts that are the same
as the parts explained before are given the same reference
numerals, and descriptions thereof are omitted.
[0076] Referring to FIG. 9A, similar to the structure illustrated
in FIG. 2A, the Cu electrode pads 11A and 11B are formed on the
substrate 11 of the printed wiring board 20. However, in the
present embodiment, a Sn sacrifice layer 13S having a film
thickness of, for example, about 1 .mu.m is formed on each of the
Cu electrode pads 11A and 11B by an electroless plating method.
[0077] For example, in the structure illustrated in FIG. 9A,
similar to the above-mentioned first embodiment, the film
deposition of the Sn sacrifice layer 13A is performed after washing
the Cu electrode pads 11A and 11B with a 10% sulfuric acid solution
and drying it in a nitrogen gas atmosphere.
[0078] Furthermore, in the process of FIG. 9B, the structure of
FIG. 9A is immersed into an electroless plating solution, which
contains 25 g/L of SnCl.sub.2, 70 g/L of CS(NH.sub.2).sub.2, 50 g/L
of HCl, 15 g/L of NaHPO.sub.2.2H.sub.2O and 0.5 g/L of surfactant,
at 70.degree. C. for 3 minutes in order to form the Sn sacrifice
layer 13S. Here, a part of Sn atoms of the Sn sacrifice layer 13A
spreads into the Cu electrode pad 11A or 11B during the film
depositing process, which forms the intermetallic compound
Cu.sub.6Sn.sub.5 mentioned before. However, because the film
depositing process time is short, a large part of the Sn sacrifice
layer 13A remains on the Cu electrode pad 11A or 11B in the state
illustrated in FIG. 9B.
[0079] Then, after washing the structure illustrated in FIG. 9B
with pure water for 30 seconds in the process of FIG. 9C, the
structure of FIG. 9B is immersed into an electroless plating
solution, which contains 1-10 g/L of bismuth nitrate, 5-60 g/L of
thiourea and 5-10 g/L of nitric acid, at 50.degree. C. for 10
minutes. Thereby, the Bi-plated layer 12 is formed on each of the
Cu electrode pads 11A and 11B as illustrated in FIG. 9C with a film
thickness of about 1 .mu.m. During the formation of the Bi-plated
layer 12, Sn atoms forming the Sn sacrifice layer 13A spread into
the Cu electrode pad 11A or 11B. As a result, an interface area 11S
containing the intermetallic compound Cu.sub.6Sn.sub.5 is formed
along the Cu electrode pad 11A or 11B. However, in the state
illustrated in FIG. 9C, because the film thickness of the Sn
sacrifice layer 13A is as small as 1 .mu.m, the interface area 11S
is limited in a range of about 0.2 .mu.m of the surface of the Cu
electrode pad 11A or 11B. Additionally, the Sn sacrifice layer 13S
does not remain on the surface of the Cu electrode pad 11A or 11B.
That is, there is no Sn layer existing between the Bi-plated layer
and the Cu electrode pad 11A or 11B.
[0080] Then, the structure illustrated in FIG. 9C is washed with
pure water for 30 seconds. Thereafter, in the process of FIG. 9D,
the structure of FIG. 9C is immersed into a Cu electroless plating
solution at 40.degree. C. for 5 minutes. As for the Cu electroless
plating solution, "throucup PRX" manufactured by Uemura Kogyo
Company Limited may be used. Thereby, a Cu sacrifice layer 11T
having a thickness of about 0.5 .mu.m is formed on the outer side
of the Bi-plated layer 12 as illustrated in FIG. 9D.
[0081] Then, the structure illustrated in FIG. 9D is immersed into
an electroless plating solution, which contains 25 g/L of
SnCl.sub.2, 70 g/L of CS(NH.sub.2).sub.2, 50 g/L of HCl, 15 g/L of
NaHPO.sub.2.2H.sub.2O and 0.5 g/L of surfactant, at 70.degree. C.
for 3 minutes in order to form the Sn sacrifice layer 13S as
illustrated in FIG. 9E. At this time, Sn atoms spread into the
previously formed Cu sacrifice layer 11T. Thus, the Cu sacrifice
layer 11T is changed into a Sn layer interface area 13U containing
Cu atoms.
[0082] In the present embodiment, because the formation of the
Bi-plated layer 12 is performed on the Sn sacrifice layer 13A,
which has an affinity to the Bi layer, when forming the Bi-plated
layer 12, the Bi-plated layer 12 is made flat and there is no
island-form growth such as in the above-mentioned embodiment. Thus,
when forming the Sn-plated layer 13, Sn atoms are prevented from
spreading from the Sn-plated layer 13 into the Cu electrode pad 11A
or 11B more efficiently than the case of the above-mentioned
embodiment, thereby more accurately controlling the composition of
the solder layers 12A ad 12B including the thus-formed Sn/Bi
lamination structure to be close to the eutectic composition.
[0083] A description will be given below, with reference to FIGS.
10A through 10L, of a third embodiment.
[0084] Referring to FIG. 10A, through vias 61A and 61B, which are
Cu plugs, are formed in a core substrate 61. Cu wiring patterns 61a
and 61b are formed on a top surface of the core substrate 61. Cu
wiring patterns 61c and 61d are formed on a bottom surface of the
core substrate 61.
[0085] As illustrated in FIG. 10B, a low-dielectric resin film 62A
is formed on the top surface of the core substrate 61 to cover the
Cu wiring patterns 61a and 61b, and a low-dielectric resin film 62B
such as NCS is formed on the bottom surface of the core substrate
61 to cover the Cu wiring patterns 61c and 61d.
[0086] Then, as illustrated in FIG. 10C, opening parts 62a and 62b
are formed in the low-dielectric resin film 62A to expose the Cu
wiring patterns 61a and 61b, respectively, and opening parts 62c
and 62d are formed in the low-dielectric resin film 62B to expose
the Cu wiring patterns 61c and 61d, respectively.
[0087] Then, as illustrated in FIG. 10D, a Cu seed layer 63A is
formed on the low-dielectric resin film 62A by electroless plating
to cover the opening parts 62a and 62b, and, simultaneously, a Cu
seed layer 63B is formed on the low-dielectric resin film 62B by
electroless plating to cover the opening parts 62c and 62d.
[0088] Further, as illustrated in n FIG. 10E, a resist pattern R1,
which has opening parts corresponding to wiring patterns to be
formed, is formed on the Cu seed layer 63A, and, similarly, a
resist pattern R2, which has opening parts corresponding to wiring
patterns to be formed, is formed on the Cu seed layer 63B.
[0089] Then, in the process illustrated in FIG. 10E, Cu wiring
patters 64A through 64H are formed in the openings of the resist
patterns R1 and R2 by electrolytic plating using the Cu seed layers
63A and 63B as electrodes.
[0090] Thereafter, as illustrated in FIG. 10F, the resist patterns
R1 and R2 are removed. Then, portions of the Cu seed layers 63A and
63B, which are exposed by sputtering, are removed, and the
thus-formed Cu wiring patterns 64A through 64H are separated from
each other.
[0091] Then, as illustrated in FIGS. 10G through 10I, a solder
resist film R3 is formed on the top surface of the thus-formed
printed wiring board so that pad electrode forming portions 65A
through 65C are exposed from among the Cu wiring patterns formed on
the top surface of the printed wiring board including the wiring
patterns 64A through 64D. FIG. 10G is a plan view of the top
surface of the printing wiring board on which the solder resist
film R3 is formed. FIG. 10H is a cross-sectional view taken along a
line A-B of FIG. 10G. FIG. 10I is a cross-sectional view taken
along a line C-D of FIG. 10G.
[0092] Then, as illustrated in FIGS. 10J through 10L, electroless
plating is performed using the solder resist film R3 as a mask to
form a Bi-plated layer 66 corresponding to the Bi-plated layer 12
in the above-mentioned first embodiment and to form a Sn-plated
layer 67 corresponding to the Sn-plated layer 13 in the
above-mentioned first embodiment. Each of the Bi-plated layer 66
and the Sn-plated layer 67 has a film thickness of about 1
.mu.m.
[0093] As explained before, the Bi-plated layer 66 and the
Sn-plated layer 67 together form an eutectic solder layer having a
Sn--Bi lamination structure. However, as mentioned above, the
Bi-plated layer 66 is formed on portions in contact with the pad
electrode forming portions (Cu electrode pads) 65A through 65C.
Thus, unlike an eutectic solder layer having a conventional
lamination structure in which a Sn-plated layer is directly in
contact with a Cu electrode pad, Sn atoms are not depleted. Thus,
when it is subject to a reflowing process, a Sn--Bi eutectic solder
having a low melting temperature is formed without increasing the
thickness of the Sn-plated layer, thereby enabling mounting an
electronic device on the thus-formed printed wiring board at a
joining temperature below 200.degree. C.
[0094] According to the above-mentioned embodiments, there is no
short-circuiting occurs even in a structure in which Cu electrode
pads are arranged at very small intervals because the film
thickness of the solder layers formed on the Cu electrode pads can
be reduced.
[0095] In the embodiments explained above, instead of the Bi-plated
layer 12 or 66, other metal elements may be used, which have a
small reactivity with Cu and do not form an intermetallic compound
with Cu. For example, lead (Pb), indium (In), silver (Ag) or an
alloy containing Bi, Pb, In or Ag as a major component may be used
instead of Bi.
[0096] Moreover, instead of the Sn-plated layer 13 or 67, other
metals forming an eutectic solder with the Bi-plated layer 12 or
66, such as, for example, gold (Au) or an alloy containing Sn or Au
as a major component, may be used.
[0097] All examples and conditional language recited herein are
intended for pedagogical purposes to aid the reader in
understanding the principles of the invention and the concepts
contributed by the inventor to furthering the art, and are to be
construed a being without limitation to such specifically recited
examples and conditions, nor does the organization of such examples
in the specification relates to a showing of the superiority and
inferiority of the invention. Although the embodiment(s) of the
present invention (s) has(have) been described in detail, it should
be understood that the various changes, substitutions, and
alterations could be made hereto without departing from the spirit
and scope of the invention.
* * * * *