U.S. patent application number 14/233596 was filed with the patent office on 2014-07-10 for low-k chip packaging structure.
This patent application is currently assigned to JIANGYIN CHANGDIAN ADVANCED PACKAGING CO., LTD.. The applicant listed for this patent is Dong Chen, Jinhui Chen, Zhiming Lai, Li Zhang. Invention is credited to Dong Chen, Jinhui Chen, Zhiming Lai, Li Zhang.
Application Number | 20140191379 14/233596 |
Document ID | / |
Family ID | 44962025 |
Filed Date | 2014-07-10 |
United States Patent
Application |
20140191379 |
Kind Code |
A1 |
Zhang; Li ; et al. |
July 10, 2014 |
LOW-K CHIP PACKAGING STRUCTURE
Abstract
A low-k chip packaging structure comprising chip body I (2-1), a
chip electrode (2-2), and a chip surface passivation layer (2-3).
Chip body I (2-1) has coated thereon thin film layer I (2-3). Thin
film layer I (2-3) has arranged on a rear face thereof a support
wafer (2-5). A chip electrode (2-2) is transferred to thin film
layer I (2-4) around the exterior of the chip via a rewired metal
wiring (2-6). The rewired metal wiring (2-6) has arranged at an end
thereof a metal column (2-7). The metal column (2-7) has coated
thereon thin film layer II (2-8). The top of the metal column
protrudes thin film layer II (2-8). The protruding top of the metal
column (2-7) has arranged thereon a metal layer (2-9). The metal
layer (2-9) has arranged thereon soldering balls (2-10). The low-k
chip packaging structure solves the problem of invalid low-k chip
due to concentration of stress during chip packaging process and
allows for reduced packaging costs and great product
reliability.
Inventors: |
Zhang; Li; (Jiangyin,
CN) ; Lai; Zhiming; (Jiangyin, CN) ; Chen;
Dong; (Jiangyin, CN) ; Chen; Jinhui;
(Jiangyin, CN) |
|
Applicant: |
Name |
City |
State |
Country |
Type |
Zhang; Li
Lai; Zhiming
Chen; Dong
Chen; Jinhui |
Jiangyin
Jiangyin
Jiangyin
Jiangyin |
|
CN
CN
CN
CN |
|
|
Assignee: |
JIANGYIN CHANGDIAN ADVANCED
PACKAGING CO., LTD.
Jiangyin, Jiangsu
CN
|
Family ID: |
44962025 |
Appl. No.: |
14/233596 |
Filed: |
October 21, 2011 |
PCT Filed: |
October 21, 2011 |
PCT NO: |
PCT/CN2011/081113 |
371 Date: |
February 21, 2014 |
Current U.S.
Class: |
257/669 |
Current CPC
Class: |
H01L 2224/0401 20130101;
H01L 2224/05541 20130101; H01L 2224/13023 20130101; H01L 2224/16225
20130101; H01L 2224/131 20130101; H01L 2224/94 20130101; H01L
23/49582 20130101; H01L 24/03 20130101; H01L 2224/05541 20130101;
H01L 24/13 20130101; H01L 2924/12042 20130101; H01L 2224/05572
20130101; H01L 2224/0391 20130101; H01L 2924/00014 20130101; H01L
2924/0002 20130101; H01L 2224/73204 20130101; H01L 2224/12105
20130101; H01L 21/561 20130101; H01L 2224/81191 20130101; H01L
24/11 20130101; H01L 24/95 20130101; H01L 2224/0382 20130101; H01L
2224/04105 20130101; H01L 2224/81815 20130101; H01L 2224/81815
20130101; H01L 2924/00012 20130101; H01L 2924/00012 20130101; H01L
2224/05552 20130101; H01L 2224/05552 20130101; H01L 2924/00
20130101; H01L 2924/00014 20130101; H01L 2224/03 20130101; H01L
2924/00 20130101; H01L 2224/16225 20130101; H01L 2924/00014
20130101; H01L 2224/32225 20130101; H01L 2924/00 20130101; H01L
2224/83192 20130101; H01L 2224/11 20130101; H01L 2924/15311
20130101; H01L 24/96 20130101; H01L 23/3107 20130101; H01L 21/568
20130101; H01L 2924/0002 20130101; H01L 2224/73204 20130101; H01L
2924/15788 20130101; H01L 2924/00014 20130101; H01L 2224/05572
20130101; H01L 2224/02379 20130101; H01L 2924/15788 20130101; H01L
2224/32225 20130101; H01L 2924/014 20130101; H01L 2224/03334
20130101; H01L 2224/94 20130101; H01L 2224/05558 20130101; H01L
2224/13006 20130101; H01L 2924/12042 20130101; H01L 2224/05569
20130101; H01L 2224/0382 20130101; H01L 2224/94 20130101; H01L
2224/131 20130101; H01L 2224/05005 20130101; H01L 24/05
20130101 |
Class at
Publication: |
257/669 |
International
Class: |
H01L 23/495 20060101
H01L023/495 |
Foreign Application Data
Date |
Code |
Application Number |
Jul 18, 2011 |
CN |
201110200212.0 |
Claims
1. A low-k chip packaging structure, comprising a chip body I
(2-1), chip electrodes (2-2) and a chip surface passivation layer
(2-3), wherein, the chip body (2-1) is wrapped with a film layer I
(2-4), the back of the film layer I (2-4) is bonded with a
supporting wafer (2-5), the chip electrodes (2-2) are led to the
film layer I (2-4) in the peripheral area around the chip via metal
redistribution wires (2-6), metal posts (2-7) are arranged at the
terminals of the metal redistribution wires (2-6), and the metal
posts (2-7) are wrapped with a film layer II (2-8), with the top of
the metal posts (2-7) exposed out of the film layer II (2-8); a
metal layer (2-9), with a solder bump (2-10) on it, is arranged on
the exposed top of the metal posts (2-7).
2. The low-k chip packaging structure according to claim 1,
wherein, the metal posts (2-7) are made of electrical-conductive
metal materials such as Cu or Cu/Ni, etc., and the height of the
metal posts(2-7) is within the range of 50 .mu.m-100 .mu.m.
3. The low-k chip packaging structure according to claim 1,
wherein, the metal layer (2-9) adopts multilayer metal, has a Ni/Au
or Ni/Pd/Au structure, and the thickness of the metal layer (2-9)
is not greater than 5 .mu.m.
4. The low-k chip packaging structure according to claim 1,
wherein, a chip body II (2-1 1) is embedded in the film layer I
(2-4).
5. The low-k chip packaging structure according to claim 1,
wherein, the metal redistribution wires (2-6) are formed by metal
wiring layer I (2-6-1) and metal wiring layer II (2-6-2).
6. The low-k chip packaging structure according to claim 1,
wherein, both the film layer I (2-4) and the film layer II (2-8)
are made of non-photo-sensitive materials.
7. The low-k chip packaging structure according to claim 1,
wherein, the supporting wafer (2-5) is a silicon wafer or a metal
wafer.
8. The low-k chip packaging structure according to claim 1,
wherein, the bearer wafer adopts a silicon substrate or a glass
substrate.
9. The low-k chip packaging structure according to claim 2,
wherein, the metal layer (2-9) adopts multilayer metal, has a Ni/Au
or Ni/Pd/Au structure, and the thickness of the metal layer (2-9)
is not greater than 5 .mu.m.
10. The low-k chip packaging structure according to claim 2,
wherein, a chip body II (2-11) is embedded in the film layer I
(2-4).
11. The low-k chip packaging structure according to claim 2,
wherein, the metal redistribution wires (2-6) are formed by metal
Wiring layer I (2-6-1) and metal wiring layer II (2-6-2).
12. The low-k chip packaging structure according to claim 2,
wherein, both the film Layer II (2-4) and the film layer II (2-8)
are made of non-photo-sensitive materials.
13. The low-k chip packaging structure according to claim 2,
wherein, the supporting wafer (2-5) is a silicon wafer or a metal
wafer.
14. The low-k chip packaging structure according to claim 2,
wherein, the bearer wafer adopts a silicon substrate or a glass
substrate.
Description
FIELD OF THE INVENTION
[0001] The present invention relates to a low-k chip packaging
structure, and belongs to the technical field of chip
packaging.
BACKGROUND ART
[0002] In the semiconductor manufacturing industry, the Moore's Law
was always the power that pushed the industry to develop
continuously, and Intel made great contributions in that aspect.
The line width nodes of chips have mainly underwent the following
several stages: 0.18 .mu.m stage--the initial stage of
semiconductor process technology, in which MOS tubes became
popularized and chips were manufactured in relatively large sizes;
0.13 .mu.m stage--in that stage, people were faith confident in
semiconductor process technology and hoped to reduce chip area and
cost by decreasing the feature size; those two stages were usually
referred to as micrometer process technology stages. With the
developed of nanometer technology, people's vision was no longer
hunted to micrometer technology but turned to nano-scale
semiconductor process technology. 90 nm process technology emerged
first, and as the quantity of tube cores on unit area increased
exponentially following the Moore's Law, 65 nm, 45 nm, 32 nm, and
current 22 nm process technology emerged successively. However, the
sharp reduction of feature size led to a pursuit for low dielectric
loss constant (usually referred to as Low-k) of dielectric
materials, for the purpose of reducing parasitic resistance,
capacitance and inductance in circuits while ensuring favorable
insulating performance of the circuits. Porous materials are
usually selected as low-k materials, as a result, the low-k
materials are relatively brittle and may be easily fractured under
external stress, causing line failures.
[0003] Owing to the brittleness of low-k materials, the chip
packaging process and the chip structure have to be improved
appropriately to adapt to the requirement for product application.
Up to now, the packaging of low-k products still employs
conventional flip-chip bonding or wire bonding, which results in
severe loss of packaging yield. The result of failure analysis
indicates that the failure is mainly resulted from fracture of the
dielectric layer under bonding electrodes (wire bonding and
flip-chip bonding). At present, the general solution is to replace
wire bonding packaging with flip-chip bonding packaging, and mange
non-flow underfill on the substrate before flip-chip bonding. The
packaging structure is shown in FIG. 1. The underfill has features
of ordinary underfill and features of fellow flux, therefore, the
solder balls and the bonding pad on the substrate can wet each
other. The advantage of this method is that injuries to the
dielectric layer in the chip caused by the stress of soldered balls
during reflow in the conventional flip-chip packaging process can
be alleviated, that is to say, the stress is redistributed via the
non-flow underfill dining reflow, and thereby the dielectric layer
in the chip will not be injured owing to stress concentration.
However, the biggest disadvantage of this method is that, owing to
the existence of the underfill, the flux wetting effect is not
enough to ensure that every soldered ball is bonded well to the
bonding pad; in addition, cavities may occur in the underfill
during the curing process owing to the existence of flux and the
application of reflow.
[0004] In summary, there are mainly two drawbacks in the low-k chip
packaging process at present: [0005] 1. With wire bonding and
conventional flip-chip technology, stress concentration may occur
at the chip electrodes because of stress produced in the
technological process, resulting in fracture of the low-k
dielectric layer and chip failure; [0006] 2. With non-flow
underfill, the flip-chip packaging process may generate poor
bonding and cavities in the underfill after curing, causing
degraded product reliability.
DISCLOSURE OF THE INVENTION
Technical Problem
[0007] To overcome the above-mentioned drawbacks, the present
invention provides a low-k chip packaging structure and a method
for low-k chip packaging, which can prevent low-k chip failures
resulted from stress concentration in the chip packaging process
and provide a low-cost packaging solution for low-k chips.
Technical Solution
[0008] The objects of the present invention are attained as
follows: a low-V chip packaging .structure comprising a chip body
I. chip electrodes, and a chip. surface passivation layer, wherein,
the chip body I is Wrapped With a film layer I, a supporting wafer
is arranged on the back of the film layer I, the chip electrodes
are led via metal redistribution wires to the film layer I in the
peripheral area. around the chip, metal posts are arranged at the
terminals of the metal redistribution wires, and the metal posts
are wrapped with a film layer II, and the top of the metal posts is
exposed out of the film layer II; a metal layer, with a solder bump
on it, is arranged on the exposed top of each metal post.
[0009] The metal posts are made of electrical-conductive metals
such as copper or nickel, etc . . . and the metal posts are in
height within the range of 50 .mu.m-100 .mu.m.
[0010] The metal layer consists of a plurality of metal, and has a
Ni/Au or Ni/Pd/Au structure, and the thickness of the metal layer
is not greater than 5 .mu.m.
[0011] A chip body II is embedded in the film layer I.
[0012] The metal redistribution wires are formed by metal wiring
layer I and metal wiring layer II.
[0013] Both the film layer I and the film layer II are made of a
non-photo-sensitive materials.
[0014] The supporting wafer is a silicon wafer or a metal
wafer.
[0015] The bearer wafer adopts a silicon substrate or a glass
substrate.
Beneficial Effects
[0016] Compared to the prior art, the present invention has the
following advantages: [0017] 1. Since the chips are mounted onto
the bearer wafer by direct flip-chip mounting, without experiencing
reflow or stress concentration, therefore. Chip failures resulted
from stress concentration in the flip-chip process of BGA packaging
for low-k chips in the prior art can be prevented;
[0018] 2. The chip electrodes are extended to the non-chip area by
wire redistribution through a wafer-level process; therefore, the
stress generated in attachment process of BGA structure is
transferred, then the chip area is no longer in stressed state:
[0019] 3. Metal post technique and structure are utilized to
implement high power current carrying and uniform current
distribution; in addition, the height of the copper posts is
utilized to buffer the stress from BGA bumps, so that the stress
will not be transferred to the redistribution layer;
[0020] 4. With wafer-level packaging technique and metal post
technique, the packaging cost can be reduced while the low-k chips
are packed with high
[0021] 5. The existing encapsulation technique in the prior art is
replaced with a film attachment technique; therefore, the
requirement for equipment in the packaging process is
decreased;
[0022] 6. Bumping technique, flip-chip technique and substrate
technique are integrated to implement a BGA packaged wafer
manufacturing process.
BRIEF DESCRIPTION OF THE DRAWINGS
[0023] FIG. 1 is a schematic diagram of the low-k chip packaging
structure in the prior art;
[0024] FIG. 2 is a schematic diagram of the low-k chip packaging
structure disclosed in embodiment 1 of the present invention;
[0025] FIG. 3 is a schematic diagram of the low-k chip packaging
structure disclosed in embodiment 2 of the present invention;
[0026] FIG. 4 is a schematic diagram of the low-k chip packaging
structure disclosed in embodiment 3 of the present invention.
AMONG THE FIGURES
[0027] 1-1: chip body [0028] 1-2: chip electrode [0029] 1-3 surface
passivation layer [0030] 1-4: metal layer under bumps [0031] 1-5:
solder bump [0032] 1-6: substrate [0033] 1-7: bonding pad on
substrate I [0034] 1-8: underfill [0035] 1-9: bonding pad on
substrate II [0036] 1-10: BGA bump [0037] 2-1: chip body I [0038]
2-2: chip electrode [0039] 2-3: chip surface passivation layer
[0040] 2-4: film layer I [0041] 2-5: supporting wafer [0042] 2-6:
metal redistribution wire [0043] 2-7: metal post [0044] 2-8: film
layer II [0045] 2-9: metal layer [0046] 2-10: solder bump [0047]
2-11: chip body II [0048] 2-12: dielectric layer [0049] 2-6-1:
metal wiring layer I [0050] 2-6-2: metal wiring layer II
DETAILED DESCRIPTION OF THE EMBODIMENTS
[0051] As shown in FIGS. 2, the present invention provides a low-k
chip packaging structure, comprising chip body I 2-1, chip
electrodes 2-2, and chip surface passivation layer 2-3, wherein,
the chip body I 2-1 is wrapped with a film layer I 2-4, the back of
the film layer I 2-4 is bonded with a supporting wafer 2-5, the
chip electrodes 2-2 are led to the film layer I 2-4 in the
peripheral area. around the chip via the metal redistribution wires
2-6, metal posts 2-7 are arranged at the terminals of the metal
redistribution wires 2-6, and the metal posts 2-7 are wrapped with
a film layer II 2-8, with the top of the metal posts 2-7 exposed
out of the film layer II 2-8; a metal layer 2-9, with a solder bump
2-10 on it, is arranged on the exposed top of the metal posts
2-7.
[0052] As shown in FIG. 3, a chip body II 2-11 is embedded in the
film layer I 2-4.
[0053] As shown in FIG. 4, the metal redistribution wires 2-6 are
formed by metal wiring layer I 2-6-1 and metal wiring layer II
2-6-2.
[0054] The implementation procedures of the low-k chip packaging
structure provided in the present invention are as follows;
[0055] Step 1: taking a low-k wafer and cutting it into individual
chips.
[0056] Step 2: funning aligning marks by photo-lithography on a
bearer wafer to complete the pattern layout on the bearer
wafer;
[0057] The bearer wafer can be a silicon substrate or a glass
substrate. Aligning marks are formed on the bearer wafer to
facilitate the follow-up flip-chip mounting process and keep the
chips at ideal positions.
[0058] Step 3: attaching a temporary strippable film to the bearer
wafer and flip-chip mounting the chips obtained in step 1 one by
one to the bearer wafer attached with the temporary strippable
film.
[0059] The temporary strippable film is adhesive on both sides, and
can bond well with both the bearer wafer and the subsequently
flip-chip mounted chips. The strippable film is thermally
strippable or UV strippable. If the strippable film is UV
strippable, a bearer wafer should be glass substrate or quartz
substrate since LW irradiation is required for UV stripping.
Accordingly, the substrate must be transparent for UV
transmission,
[0060] Flip-chip mounting is selected for two purposes: one is to
ensure chips different in thickness can be mounted with the face
side in the same plane in the subsequent process, the other is to
prevent glue coverage on the face side of the chips on the
restructured wafer; so as to facilitate subsequent processing.
[0061] step 4: attaching a film layer I 2-4 to the bearer wafer for
encapsulation after flip-chip mounting of the chips, bonding a
supporting wafer 2-5 to the film, layer I 2-4 in the encapsulation
process, and curing the film layer I 2-4, then forming a
restructured wafer composed of the chips, film layer I 2-4 and
supporting wafer 2-5.
[0062] The supporting wafer 2-5 is a silicon wafer or a metal
wafer, and the wafer surface is kept smooth in the encapsulation
process because the film layer I 2-4 has good fluidity under
heating.
[0063] Step 5: shipping the restructured wafer from the bearer
wafer by UV irradiation or thermal stripping and cleaning the
surface of the chips on the restructured wafer to expose the chip
electrodes 2-2.
[0064] Step 6: forming single-layer or multi-layer metal
redistribution wires 2-6 on the surface of the film layer I 2-4 and
the chips by wafer-level photo-lithography, sputtering, or
electroplating, so as to lead the chip electrodes 2-2 to the
peripheral area of the chips (the area without chip) via metal
redistribution wires 2-6.
[0065] Step 7: forming metal posts 2-7 at the terminals of metal
redistribution wires 2-6 by photo-lithography or
electroplating,
[0066] The metal posts 2-7 are made of an electrical-conductive
metal material such as copper or nickel, etc.; the height of the
metal posts 2-7 can be adjusted according to the requirements of
the structure and shall not be smaller than 50 .mu.m, generally,
the height of the metal posts 2-7 is within the range of 50
.mu.m-100 .mu.m. Here, the metal posts 2-7 have two functions: one
function is to reduce crowding effect of electric current, i.e.,
with the metal posts, the electric current can be distributed
uniformly and thereby the phenomenon of electric. migration can be
reduced: the other .function is to utilize the height of the metal
posts 2-7 to buffer the stress from the bumps 2-10 and thereby
protect the low-k chips.
[0067] Step 8: attaching as film layer II 2-8 to the surface of the
restructured wafer with the metal posts 2-7 for encapsulation
curing the package, and then removing the film material on the top
of the metal posts by laser ablation, to form complete Or partial
openings on the metal posts 2-7 and expose the top of the metal
posts 2-7 out of the film layer II 2-8.
[0068] The film layer I 2-4 and film layer II 2-8 are made of
non-photo-sensitive insulating resin materials.
[0069] Step 9: coating a metal layer 2-9 on the top of the metal
posts 2-7 exposed out of the film layer II 2-8.
[0070] The metal layer 2-9 adopts single layer metal or multilayer
metal. The multilayer metal usually has a Ni/Au or Ni/Pd/Au
structure. The thickness of the metal layer 2-9 should not be
greater than 5 .mu.m. The metal layer 2-9 is used to prevent
inter-diffusion between stannum and copper in the soldering flux
and improve product reliability.
[0071] Step 10: forming BGA solder bumps 2-10 on the metal layer
2-9 by printing or bumping and finally cutting the restructured
wafer with BGA solder bumps into individual BGA packages.
* * * * *