U.S. patent application number 13/682742 was filed with the patent office on 2014-05-22 for memory cell and memory cell array using the same.
This patent application is currently assigned to United Microelectronics Corporation. The applicant listed for this patent is UNITED MICROELECTRONICS CORPORATION. Invention is credited to Hsin-Wen CHEN, Shih-Chin LIN, Chi-Chang SHUAI.
Application Number | 20140140120 13/682742 |
Document ID | / |
Family ID | 50514264 |
Filed Date | 2014-05-22 |
United States Patent
Application |
20140140120 |
Kind Code |
A1 |
CHEN; Hsin-Wen ; et
al. |
May 22, 2014 |
MEMORY CELL AND MEMORY CELL ARRAY USING THE SAME
Abstract
A memory cell includes six transistors. The first and second
P-type transistors have the sources coupled to a first voltage. The
first and second N-type transistors have the drains coupled to
drains of the first and second P-type transistors, respectively;
the sources coupled to a second voltage; and the gates coupled to
gates of the first and second P-type transistors, respectively. The
third N-type transistor has the drain coupled to a write word line;
the source coupled to drain of the first N-type transistor and gate
of the second N-type transistor; and the gate coupled to a first
write bit line. The fourth N-type transistor has the drain coupled
to the write word line; the source coupled to drain of the second
N-type transistor and gate of the first N-type transistor; and the
gate coupled to a second write bit line. A memory cell array is
also provided.
Inventors: |
CHEN; Hsin-Wen; (Kaohsiung
City, TW) ; SHUAI; Chi-Chang; (Hsinchu City, TW)
; LIN; Shih-Chin; (Hsinchu County, TW) |
|
Applicant: |
Name |
City |
State |
Country |
Type |
UNITED MICROELECTRONICS CORPORATION |
Hsinchu |
|
TW |
|
|
Assignee: |
United Microelectronics
Corporation
Hsinchu
TW
|
Family ID: |
50514264 |
Appl. No.: |
13/682742 |
Filed: |
November 21, 2012 |
Current U.S.
Class: |
365/72 |
Current CPC
Class: |
G11C 8/14 20130101; G11C
11/418 20130101; G11C 5/06 20130101 |
Class at
Publication: |
365/72 |
International
Class: |
G11C 5/06 20060101
G11C005/06 |
Claims
1. A memory cell, comprising: a first P-type transistor configured
to have the first source/drain thereof electrically coupled to a
first voltage; a second P-type transistor configured to have the
first source/drain thereof electrically coupled to the first
voltage; a first N-type transistor configured to have the first
source/drain thereof electrically coupled to the second
source/drain of the first P-type transistor, the second
source/drain thereof electrically coupled to a second voltage, and
the gate thereof electrically coupled to the gate of the first
P-type transistor; a second N-type transistor configured to have
the first source/drain thereof electrically coupled to the second
source/drain of the second P-type transistor, the second
source/drain thereof electrically coupled to the second voltage,
and the gate thereof electrically coupled to the gate of the second
P-type transistor; a third N-type transistor configured to have the
first source/drain thereof electrically coupled to a write word
line, the second source/drain thereof electrically coupled to the
first source/drain of the first N-type transistor and the gate of
the second N-type transistor, and the gate thereof electrically
coupled to a first write bit line; and a fourth N-type transistor
configured to have the first source/drain thereof electrically
coupled to the write word line, the second source/drain thereof
electrically coupled to the first source/drain of the second N-type
transistor and the gate of the first N-type transistor, and the
gate thereof electrically coupled to a second write bit line.
2. The memory cell according to claim 1, further comprising: a
fifth N-type transistor configured to have the first source/drain
thereof electrically coupled to a read bit line, and the gate
thereof electrically coupled to a read word line; and a sixth
N-type transistor configured to have the first source/drain thereof
electrically coupled to the second source/drain of the fifth N-type
transistor, the second source/drain thereof electrically coupled to
the second voltage, and the gate thereof electrically coupled to
the gate of the first N-type transistor.
3. The memory cell according to claim 1, wherein the first voltage
is configured to have a value greater than that of the second
voltage.
4. The memory cell according to claim 1, wherein the first write
bit line is configured to turn on or turn off the third N-type
transistor, the second write bit line is configured to turn on or
turn off the fourth N-type transistor.
5. The memory cell according to claim 4, wherein the third and
fourth N-type transistors are controlled to be turned on at
different times.
6. The memory cell according to claim 4, wherein the write word
line is configured to have a low voltage level thereon when the
first write bit line has a high voltage level thereon and the
second write bit line has a low voltage level thereon.
7. The memory cell according to claim 4, wherein the write word
line is configured to have a low voltage level thereon when the
first write bit line has a low voltage level thereon and the second
write bit line has a high voltage level thereon.
8. The memory cell according to claim 1, wherein each of the third
and fourth N-type transistors is replaced by a P-type
transistor.
9. A memory cell array, comprising: a plurality of write word
lines; a plurality of first write bit lines; a plurality of second
write bit lines; and a plurality of memory cells arranged in a
matrix form, each one of the memory cells being electrically
coupled to one of the write word lines, one of the first write bit
lines and one of the second write bit lines, each one of the memory
cells comprising: a first P-type transistor configured to have the
first source/drain thereof electrically coupled to a first voltage;
a second P-type transistor configured to have the first
source/drain thereof electrically coupled to the first voltage; a
first N-type transistor configured to have the first source/drain
thereof electrically coupled to the second source/drain of the
first P-type transistor, the second source/drain thereof
electrically coupled to a second voltage, and the gate thereof
electrically coupled to the gate of the first P-type transistor; a
second N-type transistor configured to have the first source/drain
thereof electrically coupled to the second source/drain of the
second P-type transistor, the second source/drain thereof
electrically coupled to the second voltage, and the gate thereof
electrically coupled to the gate of the second P-type transistor; a
third N-type transistor configured to have the first source/drain
thereof electrically coupled to one of the write word lines, the
second source/drain thereof electrically coupled to the first
source/drain of the first N-type transistor and the gate of the
second N-type transistor, and the gate thereof electrically coupled
to one of the first write bit lines; and a fourth N-type transistor
configured to have the first source/drain thereof electrically
coupled to one of the write word lines, the second source/drain
thereof electrically coupled to the first source/drain of the
second N-type transistor and the gate of the first N-type
transistor, and the gate thereof electrically coupled to one of the
second write bit lines.
10. The memory cell array according to claim 9, wherein each one of
the memory cells further comprises: a fifth N-type transistor
configured to have the first source/drain thereof electrically
coupled to one of the read bit lines, and the gate thereof
electrically coupled to one of the read word lines; and a sixth
N-type transistor configured to have the first source/drain thereof
electrically coupled to the second source/drain of the fifth N-type
transistor, the second source/drain thereof electrically coupled to
the second voltage, and the gate thereof electrically coupled to
the gate of the first N-type transistor.
11. The memory cell array according to claim 9, wherein the first
voltage is configured to have a value greater than that of the
second voltage.
12. The memory cell array according to claim 9, wherein one of the
first write bit lines is configured to turn on or turn off the
third N-type transistor, one of the second write bit lines is
configured to turn on or turn off the fourth N-type transistor.
13. The memory cell array according to claim 12, wherein the third
and fourth N-type transistors are controlled to be turned on at
different times.
14. The memory cell array according to claim 12, wherein one of the
write word lines is configured to have a low voltage level thereon
when one of the first write bit lines has a high voltage level
thereon and one of the second write bit lines has a low voltage
level thereon.
15. The memory cell array according to claim 12, wherein one of the
write word lines is configured to have a low voltage level thereon
when one of the first write bit lines has a low voltage level
thereon and one of the second write bit lines has a high voltage
level thereon.
16. The memory cell array according to claim 9, wherein each of the
third and fourth N-type transistors is replaced by a P-type
transistor.
Description
FIELD OF THE INVENTION
[0001] The present invention relates to a memory technique field,
and more particularly to a memory cell and a memory cell array
using the same.
BACKGROUND OF THE INVENTION
[0002] FIG. 1 is a schematic circuit view of a conventional memory
cell. As shown, the conventional memory cell 10 includes two P-type
transistors P1, P2, four N-type transistors N1, N2, N3 and N4, a
write word line WWL, a first write bit line WBL and a second write
bit line WBLB. In the circuit structure of the memory cell 10 shown
in FIG. 1, the N-type transistors N3, N4 both are controlled by the
write word line WWL; specifically, both of the N-type transistors
N3, N4 are controlled to be turned on by the write word line WWL
when the memory cell 10 needs to perform data access. However,
turning on the two N-type transistors N3, N4 at a same time may
lead the memory cell 10 having a relatively poor anti-noise
ability; wherein the anti-noise ability is usually
measured/illustrated by the static noise margin (SNM).
[0003] FIG. 2 is a schematic plot illustrating the static noise
margin of the memory cell 10 shown in FIG. 1; wherein the static
noise margin is defined by the squares enclosed by two
characteristic curves, and the area size of the static noise margin
is proportional to the anti-noise ability of the memory cell 10. As
shown, the area size of the static noise margin is relatively small
due to the conventional circuit structure of the memory cell 10;
thus, the conventional memory cell 10 has a relatively poor
anti-noise ability and consequently the memory cell may result in
errors while performing data access.
SUMMARY OF THE INVENTION
[0004] The object of present invention is to provide a memory cell
having higher anti-noise ability and consequently being capable of
preventing errors from occurring while performing data access.
[0005] Another object of present invention is to provide a memory
cell array using the aforementioned memory cell.
[0006] An embodiment of the present invention provides a memory
cell, which includes a first P-type transistor, a second P-type
transistor, a first N-type transistor, a second N-type transistor,
a third N-type transistor and a fourth N-type transistor. The first
P-type transistor is configured to have the first source/drain
thereof electrically coupled to a first voltage. The second P-type
transistor is configured to have the first source/drain thereof
electrically coupled to the first voltage. The first N-type
transistor is configured to have the first source/drain thereof
electrically coupled to the second source/drain of the first P-type
transistor, the second source/drain thereof electrically coupled to
a second voltage, and the gate thereof electrically coupled to the
gate of the first P-type transistor. The second N-type transistor
is configured to have the first source/drain thereof electrically
coupled to the second source/drain of the second P-type transistor,
the second source/drain thereof electrically coupled to the second
voltage, and the gate thereof electrically coupled to the gate of
the second P-type transistor. The third N-type transistor is
configured to have the first source/drain thereof electrically
coupled to a write word line, the second source/drain thereof
electrically coupled to the first source/drain of the first N-type
transistor and the gate of the second N-type transistor, and the
gate thereof electrically coupled to a first write bit line. The
fourth N-type transistor is configured to have the first
source/drain thereof electrically coupled to the write word line,
the second source/drain thereof electrically coupled to the first
source/drain of the second N-type transistor and the gate of the
first N-type transistor, and the gate thereof electrically coupled
to a second write bit line.
[0007] Another embodiment of the present invention provides a
memory cell array, which includes a plurality of write word lines,
a plurality of first write bit lines, a plurality of second write
bit lines and a plurality of memory cells. The memory cells are
arranged in a matrix form and each one of the memory cells is
electrically coupled to one of the write word lines, one of the
first write bit lines and one of the second write bit lines. Each
one of the memory cells includes a first P-type transistor, a
second P-type transistor, a first N-type transistor, a second
N-type transistor, a third N-type transistor and a fourth N-type
transistor. The first P-type transistor is configured to have the
first source/drain thereof electrically coupled to a first voltage.
The second P-type transistor is configured to have the first
source/drain thereof electrically coupled to the first voltage. The
first N-type transistor is configured to have the first
source/drain thereof electrically coupled to the second
source/drain of the first P-type transistor, the second
source/drain thereof electrically coupled to a second voltage, and
the gate thereof electrically coupled to the gate of the first
P-type transistor. The second N-type transistor is configured to
have the first source/drain thereof electrically coupled to the
second source/drain of the second P-type transistor, the second
source/drain thereof electrically coupled to the second voltage,
and the gate thereof electrically coupled to the gate of the second
P-type transistor. The third N-type transistor is configured to
have the first source/drain thereof electrically coupled to one of
the write word lines, the second source/drain thereof electrically
coupled to the first source/drain of the first N-type transistor
and the gate of the second N-type transistor, and the gate thereof
electrically coupled to one of the first write bit lines. The
fourth N-type transistor is configured to have the first
source/drain thereof electrically coupled to one of the write word
lines, the second source/drain thereof electrically coupled to the
first source/drain of the second N-type transistor and the gate of
the first N-type transistor, and the gate thereof electrically
coupled to one of the second write bit lines.
[0008] In summary, through controlling the third and fourth N-type
transistors to be turned on at different times by the first write
bit line and the second write bit line, respectively, the memory
cell as well as the memory cell array using the same of the present
invention accordingly can have higher anti-noise ability and
consequently is capable of preventing errors from occurring while
performing data access.
BRIEF DESCRIPTION OF THE DRAWINGS
[0009] The present invention will become more readily apparent to
those ordinarily skilled in the art after reviewing the following
detailed description and accompanying drawings, in which:
[0010] FIG. 1 is a schematic circuit view of a conventional memory
cell;
[0011] FIG. 2 is a schematic plot illustrating the static noise
margin of the memory cell shown in FIG. 1;
[0012] FIG. 3 is a schematic circuit view of a memory cell in
accordance with an embodiment of the present invention;
[0013] FIG. 4 is a schematic plot illustrating the static noise
margin of the memory cell shown in FIG. 3;
[0014] FIG. 5 is a time sequence of the first write bit line, the
second write bit line and the write word line; and
[0015] FIG. 6 is a schematic view of a memory cell array in
accordance with an embodiment of the present invention.
DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS
[0016] The present invention will now be described more
specifically with reference to the following embodiments. It is to
be noted that the following descriptions of preferred embodiments
of this invention are presented herein for purpose of illustration
and description only. It is not intended to be exhaustive or to be
limited to the precise form disclosed.
[0017] FIG. 3 is a schematic circuit view of a memory cell 30 in
accordance with an embodiment of the present invention; and FIG. 4
is a schematic plot illustrating the static noise margin of the
memory cell 30 shown in FIG. 3. As shown in FIG. 3, the memory cell
30 in this embodiment includes two P-type transistors P1, P2 and
six N-type transistors N1, N2, N3, N4, N5 and N6, and some
associated signal lines.
[0018] Specifically, the P-type transistors P1, P2 each are
configured to have the first source/drain thereof electrically
coupled to a first voltage VDD. The N-type transistor Ni is
configured to have the first source/drain thereof electrically
coupled to the second source/drain of the P-type transistor P1, the
second source/drain thereof electrically coupled to a second
voltage VSS, and the gate thereof electrically coupled to the gate
of the P-type transistor P1. The N-type transistor N2 is configured
to have the first source/drain thereof electrically coupled to the
second source/drain of the P-type transistor P2, the second
source/drain thereof electrically coupled to the second voltage
VSS, and the gate thereof electrically coupled to the gate of the
P-type transistor P2. The N-type transistor N3 is configured to
have the first source/drain thereof electrically coupled to a write
word line WWL, the second source/drain thereof electrically coupled
to the first source/drain of the N-type transistor Ni and the gate
of the N-type transistor N2, and the gate thereof electrically
coupled to a first write bit line WBL. The N-type transistor N4 is
configured to have the first source/drain thereof electrically
coupled to the write word line WWL, the second source/drain thereof
electrically coupled to the first source/drain of the N-type
transistor N2 and the gate of the N-type transistor N1, and the
gate thereof electrically coupled to a second write bit line WBLB.
The N-type transistor N5 is configured to have the first
source/drain thereof electrically coupled to a read bit line RBL,
and the gate thereof electrically coupled to a read word line RWL.
The N-type transistor N6 is configured to have the first
source/drain thereof electrically coupled to the second
source/drain of the N-type transistor N5, the second source/drain
thereof electrically coupled to the second voltage VSS, and the
gate thereof electrically coupled to the gate of the N-type
transistor N1. In this embodiment, the first voltage VDD is
configured to have a value greater than that of the second voltage
VSS. Additionally, in this embodiment, the transistors N3, N4 each
are exemplified by an N-type transistor; however, it is understood
that the two transistors N3, N4 each can be realized by a P-type
transistor in an alternative embodiment.
[0019] According to the circuit structure of the memory cell 30
shown in FIG. 3, the N-type transistors N3, N4 are controlled by
the first write bit line WBL and the second write bit line WBLB,
respectively; wherein the N-type transistors N3, N4 are configured
to be turned-on at different times when the memory cell 30 needs to
perform data access. Because the N-type transistors N3, N4 are not
both turned on at the same time, only either the transistors
associated with the N-type transistor N3 or the transistors
associated with the N-type transistor N4 will be affected by the
pre-charge voltage of the write bit lines WBL, WBLB or by the
external noise from the write bit lines WBL, WBLB. Thus, through
configuring the two N-type transistors N3, N4 to be turned on at
different times, the static noise margin (SNM) in this embodiment
as illustrated in FIG. 4 has an area larger than that of the static
noise margin (SNM) of a conventional memory cell as illustrated in
FIG. 2. Thus, the memory cell 30 in this embodiment can have higher
anti-noise ability and consequently is capable of preventing errors
from occurring while performing data access.
[0020] FIG. 5 is a time sequence of the first write bit line WBL,
the second write bit line WBLB and the write word line WWL. As
shown, when the first write bit line WBL has a high voltage level
thereon and the second write bit line WBLB has a low voltage level
thereon, the write word line WWL is configured to have a low
voltage level thereon and thereby writing data "0" to the memory
cell 30. Moreover, when the first write bit line WBL has a low
voltage level thereon and the second write bit line WBLB has a high
voltage level thereon, the write word line WWL is configured to
have a low voltage level thereon and thereby also writing data "0"
to the memory cell 30.
[0021] FIG. 6 is a schematic view of a memory cell array in
accordance with an embodiment of the present invention. As shown,
the memory cell array 60 in this embodiment includes a plurality of
write word lines WWL_1.about.WWL_n, a plurality of first write bit
lines WBL_1.about.WBL_n, a plurality of second write bit lines
WBLB_1.about.WBLB_n, a plurality of read bit lines
RBL_1.about.RBL_n, a plurality of read word lines RWL_1.about.RWL_n
and a plurality of memory cells 60-1; wherein, each one of the
memory cells 60-1 in this embodiment is realized by the circuit
structure of the memory cell 30 shown in FIG. 3. Specifically, the
memory cells 60-1 are arranged in a matrix form, each of the memory
cells 60-1 is electrically coupled to one of the write word lines
WWL_1.about.WWL_n, one of the first write bit lines
WBL_1.about.WBL_n, one of the second write bit lines
WBLB_1.about.WBLB_n, one of the read bit lines RBL_1.about.RBL_n
and one of the read word lines RWL_1.about.RWL_n. Each of the
memory cells 60-1 has a circuit structure and an operation same as
that of the memory cell 30 shown in FIG. 3; and no unnecessary
detail is given here.
[0022] In summary, through controlling the N-type transistors N3,
N4 to be turned on at different times by the first write bit line
WBL and the second write bit line WBLB, respectively, the memory
cell 30 as well as the memory cell array 60 using the same memory
cell of the embodiment of the present invention accordingly can
have higher anti-noise ability and consequently is capable of
preventing errors from occurring while performing data access.
[0023] While the invention has been described in terms of what is
presently considered to be the most practical and preferred
embodiments, it is to be understood that the invention needs not be
limited to the disclosed embodiment. On the contrary, it is
intended to cover various modifications and similar arrangements
included within the spirit and scope of the appended claims which
are to be accorded with the broadest interpretation so as to
encompass all such modifications and similar structures.
* * * * *