U.S. patent application number 14/164908 was filed with the patent office on 2014-05-22 for substrate for flip chip bonding and method of fabricating the same.
This patent application is currently assigned to SAMSUNG ELECTRO-MECHANICS CO., LTD.. The applicant listed for this patent is SAMSUNG ELECTRO-MECHANICS CO., LTD.. Invention is credited to Jin Won CHOI, Tae Joon CHUNG, Dong Gyu LEE, Seon Jae MUN, Hueng Jae OH.
Application Number | 20140138821 14/164908 |
Document ID | / |
Family ID | 43305438 |
Filed Date | 2014-05-22 |
United States Patent
Application |
20140138821 |
Kind Code |
A1 |
OH; Hueng Jae ; et
al. |
May 22, 2014 |
SUBSTRATE FOR FLIP CHIP BONDING AND METHOD OF FABRICATING THE
SAME
Abstract
Disclosed herein is substrate for flip chip bonding, in which a
base solder layer is formed between a pad and a metal post, thereby
increasing impact resistance and mounting reliability. A method of
fabricating the substrate for flip chip bonding is also
provided.
Inventors: |
OH; Hueng Jae; (Gyunggi-do,
KR) ; CHUNG; Tae Joon; (Gyunggi-do, KR) ; LEE;
Dong Gyu; (Gyunggi-do, KR) ; MUN; Seon Jae;
(Gyunggi-do, KR) ; CHOI; Jin Won; (Jeollabuk-do,
KR) |
|
Applicant: |
Name |
City |
State |
Country |
Type |
SAMSUNG ELECTRO-MECHANICS CO., LTD. |
GYUNGGI-DO |
|
KR |
|
|
Assignee: |
SAMSUNG ELECTRO-MECHANICS CO.,
LTD.
GYUNGGI-DO
KR
|
Family ID: |
43305438 |
Appl. No.: |
14/164908 |
Filed: |
January 27, 2014 |
Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
|
|
12554762 |
Sep 4, 2009 |
8671564 |
|
|
14164908 |
|
|
|
|
Current U.S.
Class: |
257/737 |
Current CPC
Class: |
H01L 2224/13147
20130101; H01L 24/05 20130101; H01L 2224/13083 20130101; H01L
2224/13111 20130101; H05K 3/3485 20200801; H01L 24/03 20130101;
H01L 2924/01006 20130101; H01L 24/11 20130101; H01L 2224/1146
20130101; H01L 2924/01019 20130101; H01L 2224/023 20130101; H01L
2224/13022 20130101; H01L 2924/01078 20130101; Y10T 29/49165
20150115; H05K 2201/1025 20130101; H01L 2224/11901 20130101; H01L
2924/01079 20130101; H01L 2224/16 20130101; H01L 2924/01046
20130101; H01L 2924/12042 20130101; H01L 2224/13155 20130101; H01L
2224/1308 20130101; H01L 2224/1147 20130101; H01L 2924/01029
20130101; H01L 2224/05001 20130101; H01L 2224/13144 20130101; H01L
2924/00013 20130101; H01L 2224/05644 20130101; H01L 2924/01005
20130101; H01L 2224/05026 20130101; H01L 2224/05155 20130101; H01L
2924/01033 20130101; H01L 2224/05164 20130101; H01L 2924/01047
20130101; H01L 2224/13164 20130101; H01L 23/49811 20130101; H05K
3/243 20130101; H01L 2224/05611 20130101; H01L 2224/131 20130101;
H01L 2924/01327 20130101; H01L 2224/05647 20130101; H01L 2224/05144
20130101; H01L 2224/05568 20130101; Y10T 29/49147 20150115; H01L
24/13 20130101; H01L 2224/05022 20130101; H01L 2224/05655 20130101;
H01L 2224/13084 20130101; Y02P 70/50 20151101; H05K 3/3436
20130101; H01L 2224/13144 20130101; H01L 2924/00014 20130101; H01L
2224/13147 20130101; H01L 2924/00014 20130101; H01L 2224/13111
20130101; H01L 2924/00014 20130101; H01L 2224/13155 20130101; H01L
2924/00014 20130101; H01L 2224/13164 20130101; H01L 2924/00014
20130101; H01L 2224/131 20130101; H01L 2924/014 20130101; H01L
2224/1308 20130101; H01L 2224/131 20130101; H01L 2924/014 20130101;
H01L 2924/00013 20130101; H01L 2224/13099 20130101; H01L 2924/12042
20130101; H01L 2924/00 20130101; H01L 2224/05611 20130101; H01L
2924/00014 20130101; H01L 2224/05644 20130101; H01L 2924/00014
20130101; H01L 2224/05647 20130101; H01L 2924/00014 20130101; H01L
2224/05655 20130101; H01L 2924/00014 20130101; H01L 2224/05144
20130101; H01L 2924/00014 20130101; H01L 2224/05155 20130101; H01L
2924/00014 20130101; H01L 2224/05164 20130101; H01L 2924/00014
20130101; H01L 2224/023 20130101; H01L 2924/0001 20130101 |
Class at
Publication: |
257/737 |
International
Class: |
H01L 23/498 20060101
H01L023/498 |
Foreign Application Data
Date |
Code |
Application Number |
Jun 10, 2009 |
KR |
10-2009-0051605 |
Claims
1. A substrate for flip chip bonding, comprising: a base substrate
having a pad; a solder resist layer formed on the base substrate to
expose the pad; a base solder layer formed on the pad; and a metal
post formed above the base solder layer, the metal post being
formed as a substrate contact, wherein, the base solder layer is
provided at the interface of the pad and the metal post, and in
area contact with them.
2. The substrate for flip chip bonding as set forth in claim 1,
wherein the base substrate is a semiconductor substrate.
3. The substrate for flip chip bonding as set forth in claim 1,
wherein a first surface treatment layer is formed between the base
solder layer and the metal post, the first surface treatment layer
being composed of a nickel plating layer or a nickel alloy plating
layer with or without thereon any one selected from among a
palladium plating layer, a gold plating layer and sequentially
disposed palladium plating layer and gold plating layer.
4. The substrate for flip chip bonding as set forth in claim 3,
wherein a first Ni.sub.x--Sn.sub.y-based intermetallic compound
layer is formed at an interface between the base solder layer and
the first surface treatment layer.
5. The substrate for flip chip bonding as set forth in claim 1,
wherein a solder cap is formed on the metal post.
6. The substrate for flip chip bonding as set forth in claim 5,
wherein a second surface treatment layer is formed between the
metal post and the solder cap, the second surface treatment layer
being composed of a nickel plating layer or a nickel alloy plating
layer with or without thereon any one selected from among a
palladium plating layer, a gold plating layer and sequentially
disposed palladium plating layer and gold plating layer.
7. The substrate for flip chip bonding as set forth in claim 6,
wherein a second Ni.sub.x--Sn.sub.y-based intermetallic compound
layer is formed at an interface between the second surface
treatment layer and the solder cap.
8. The substrate for flip chip bonding as set forth in claim 1,
wherein an outer surface treatment layer is formed on an outer
surface of the metal post.
Description
RELATED APPLICATION
[0001] This application is a continuation application of U.S.
patent application Ser. No. 12/554,762, filed on Sep. 4, 2009, and
claims the benefit of and priority to Korean Patent Application No.
KR 10-2009-0051605, filed on Jun. 10, 2009, all of which are
incorporated herein by reference in their entirety into this
application.
BACKGROUND
[0002] 1. Field of the Invention
[0003] The present invention relates to a substrate for flip chip
bonding and a method of fabricating the same.
[0004] 2. Description of the Related Art
[0005] With the recent advancement of the electronics industry,
there is a demand for increasing performance and functionality of
electronic components and reducing the size thereof. Accordingly,
high integration, slimness and fine circuit patterning are also
required on a substrate for surface mounting components, such as
SIP (System in Package), 3D package, etc.
[0006] In particular, in techniques for mounting electronic
components on the surface of a substrate, a wire bonding process or
a flip chip bonding process is utilized for forming an electrical
connection between a semiconductor chip and a printed circuit board
(PCB). In the case of the wire bonding process, because the
connection of the chin to the PCB is performed using a wire, the
size of a module is increased and an additional process is
required. As well, limitations are imposed on realizing a circuit
pattern having a fine pitch. So, the flip chip bonding process is
mainly employed.
[0007] The flip chip bonding process includes forming an external
connection terminal (i.e., a bump) having a size of tens of .mu.m
to hundreds of .mu.m on a semiconductor chip using a material such
as gold, solder or another metal, flipping the semiconductor chip
having the bump so that the surface thereof faces the substrate,
and mounting the semiconductor chip on the substrate, unlike the
mounting operation based on the wire bonding.
[0008] Moreover, in order to correspond to a circuit pattern having
an ultrafine pitch, the flip chip bonding process is developed to
form a new structure using a metal post. The use of such a metal
post is receiving attention as an alternative for achieving a fine
pitch, ensuring a distance between a PCB and a semiconductor chip
to thus facilitate the fabrication of a package, and improving heat
dissipation performance.
[0009] FIG. 1 is a cross-sectional view showing a semiconductor
substrate for flip chip bonding according to a conventional
technique.
[0010] As shown in FIG. 1, the semiconductor substrate 10 for flip
chip bonding according to the conventional technique includes a
silicon wafer 12 having pads 14, a solder resist layer 16 formed on
the silicon wafer 12 and having open portions for exposing the pads
14, metal posts 18 formed on the pads 14, and solder bumps 20
formed on the metal posts 18.
[0011] Although the semiconductor substrate 10 for flip chip
bonding according to the conventional technique is evaluated to be
superior in terms of height uniformity and mounting reliability, it
is not easy to relieve stress applied to the metal posts 18, and
thus the metal posts 18 suffer from necking defects and mounting
reliability is reduced.
[0012] As well, the above metal post structure employed in the
conventional semiconductor substrate has a limitation in applying
it to a package substrate on which the semiconductor substrate 10
is mounted. This is because the formation of the metal posts having
the same height is difficult when the metal posts are plated on the
package substrate which warps in the manufacturing process unlike
the silicon wafer 12.
SUMMARY
[0013] Accordingly, embodiments of the present invention has been
made keeping in mind the problems encountered in the related art
and the present invention intends to provide a substrate for flip
chip bonding, which has improved impact resistance and mounting
reliability, and a method of fabricating the same.
[0014] Embodiments of the present invention also provide a
substrate for flip chip bonding, which includes metal posts
applicable not only to a semiconductor substrate but also to a
package substrate, and a method of fabricating the same.
[0015] An embodiment of the present invention, provides a substrate
for flip chip bonding, including a base substrate having a pad, a
solder resist layer formed on the base substrate to expose the pad,
a base solder layer formed on the pad, and a metal post formed on
the base solder layer.
[0016] In accordance with an embodiment, the base substrate is a
semiconductor substrate.
[0017] In accordance with an embodiment, a first surface treatment
layer is formed between the base solder layer and the metal post,
the first surface treatment layer being composed of a nickel
plating layer or a nickel alloy plating layer with or without
thereon any one selected from among a palladium plating layer, a
gold plating layer and sequentially disposed palladium plating
layer and gold plating layer.
[0018] In accordance with an embodiment, a first
Ni.sub.x--Sn.sub.y-based intermetallic compound layer is formed at
an interface between the base solder layer and the first surface
treatment layer.
[0019] In accordance with an embodiment, a solder cap is formed on
the metal post.
[0020] In accordance with an embodiment, a second surface treatment
layer is formed between the metal post and the solder cap, the
second surface treatment layer being composed of a nickel plating
layer or a nickel alloy plating layer with or without thereon any
one selected from among a palladium plating layer, a gold plating
layer and sequentially disposed palladium plating layer and gold
plating layer.
[0021] In accordance with an embodiment, a second
Ni.sub.x--Sn.sub.y-based intermetallic compound layer is formed at
an interface between the second surface treatment layer and the
solder cap.
[0022] In accordance with an embodiment, an outer surface treatment
layer is formed on an outer surface of the metal post.
[0023] In accordance with another embodiment of the present
invention, there is provided a method of fabricating the substrate
for flip chip bonding, including (A) forming on a base substrate
having a pad a solder resist layer having an open portion for
exposing the pad, (B) applying a photosensitive resist on the
solder resist layer and the exposed pad, and forming an opening in
the photosensitive resist to expose the pad, (C) filling a part of
the opening with a solder paste, thus forming a base solder layer
connected to the pad, (D) forming a metal post connected to the
base solder layer in the opening, and (E) removing the
photosensitive resist.
[0024] In accordance with an embodiment, the base substrate is a
semiconductor substrate.
[0025] In accordance with an embodiment, a step of (C1) forming a
first surface treatment layer on the base solder layer is performed
between (C) and (D), the first surface treatment layer being
composed of a nickel plating layer or a nickel alloy plating layer
with or without thereon any one selected from among a palladium
plating layer, a gold plating layer and sequentially disposed
palladium plating layer and gold plating layer.
[0026] In accordance with an embodiment, a first
Ni.sub.x--Sn.sub.y-based intermetallic compound layer is formed at
an interface between the base solder layer and the first surface
treatment layer.
[0027] In accordance with an embodiment, a step of (D1) applying a
solder paste on the metal post thus forming a solder cap is
performed between (D) and (E).
[0028] In accordance with an embodiment, a step of (D2) forming a
second surface treatment layer on the metal post is performed
between (D) and (D1), the second surface treatment layer being
composed of a nickel plating layer or a nickel alloy plating layer
with or without thereon any one selected from among a palladium
plating layer, a gold plating layer and sequentially disposed
palladium plating layer and gold plating layer.
[0029] In accordance with an embodiment, a second
Ni.sub.x--Sn.sub.y-based intermetallic compound layer is formed at
an interface between the metal post and the second surface
treatment layer.
[0030] In accordance with an embodiment, a step of (E1) forming an
outer surface treatment layer on an outer surface of the metal post
is performed after (E).
[0031] Various objects, advantages and features of the invention
will become apparent from the following description of embodiments
with reference to the accompanying drawings.
BRIEF DESCRIPTION OF DRAWINGS
[0032] These and other features, aspects, and advantages of the
invention are better understood with regard to the following
Detailed Description, appended Claims, and accompanying Figures. It
is to be noted, however, that the Figures illustrate only various
embodiments of the invention and are therefore not to be considered
limiting of the invention's scope as it may include other effective
embodiments as well.
[0033] FIG. 1 is a cross-sectional view showing a semiconductor
substrate for flip chip bonding according to a conventional
technique.
[0034] FIG. 2 is a cross-sectional view showing a substrate for
flip chip bonding, in accordance with an embodiment of the
invention,
[0035] FIG. 3 is a cross-sectional view showing a substrate for
flip chip bonding, in accordance with an embodiment of the
invention.
[0036] FIGS. 4 to 9 are cross-sectional views sequentially showing
a process of fabricating the substrate for flip chip bonding of
FIG. 2, in accordance with an embodiment of the invention.
[0037] FIGS. 10 to 13 are cross-sectional views sequentially
showing a process of fabricating the substrate for flip chip
bonding of FIG. 3, in accordance with an embodiment of the
invention.
DETAILED DESCRIPTION
[0038] The present invention will now be described more fully
hereinafter with reference to the accompanying drawings, which
illustrate embodiments of the invention. This invention may,
however, be embodied in many different forms and should not be
construed as limited to the illustrated embodiments set forth
herein. Rather, these embodiments are provided so that this
disclosure will be thorough and complete, and will fully convey the
scope of the invention to those skilled in the art. Like numbers
refer to like elements throughout. Prime notation, if used,
indicates similar elements in alternative embodiments.
Substrate for Flip Chip Bonding
1.sup.st Embodiment
[0039] FIG. 2 is a cross-sectional view showing the substrate
having metal posts, in accordance with an embodiment of the
invention. Below, the substrate 100a having the metal posts
according to the present embodiment is described with reference to
the above drawing.
[0040] As seen in FIG. 2, the substrate 100a for flip chip bonding
according to the present embodiment includes a base substrate 102,
a solder resist layer 106, a base solder layer 114, and metal posts
116.
[0041] The base substrate 102 has pads 104 formed thereon, and the
solder resist layer 106 having open portions 108 for exposing the
pads 104 is formed on the base substrate 102. Examples of the base
substrate 102 may include a semiconductor substrate and a package
substrate.
[0042] The base solder layer 114 functions to relieve impact
applied to the metal posts 116 and improve height uniformity and
mounting reliability, and is formed on the pads 104.
[0043] The metal posts 116 enable the fine pitching of a wiring
pattern and the fast signal transfer between a substrate and a
semiconductor chip, ensure a distance between chips, and perform a
heat dissipation function. The metal posts 116 are formed to
protrude from the upper surface of the solder resist layer 106
while being connected to the base solder layer 114. The metal posts
116 may have a cylindrical shape, and may be formed of a material
such as copper (Cu), nickel (Ni), tin (Sn) or gold (Au).
[0044] Also, in order to enhance the force of adhesion between the
base solder layer 114 and the metal posts 116, a first surface
treatment layer (not shown) is thinly formed therebetween, which is
composed of a Ni plating layer or a Ni alloy plating layer with or
without thereon any one selected from among a palladium (Pd)
plating layer, an Au plating layer and sequentially disposed Pd
plating layer and Au plating layer.
[0045] The first surface treatment layer is bonded with the base
solder layer 114 made of Sn, thus forming a first
Ni.sub.x--Sn.sub.y-based intermetallic compound (IMC) layer at the
interface there between.
[0046] Furthermore, an outer surface treatment layer (not shown)
may be formed on the outer surfaces of the metal posts 116 to
prevent corrosion and oxidation thereof.
Substrate for Flip Chip Bonding
2.sup.nd Embodiment
[0047] FIG. 3 is a cross-sectional view showing a substrate for
flip chip bonding, in accordance with an embodiment of the
invention. In the description of the second embodiment, elements
which are the same as or similar to those of the first embodiment
are designated by the same reference numerals, and redundant
descriptions are omitted.
[0048] As shown in FIG. 3, the substrate 100b for flip chip bonding
according to the second embodiment is configured such that solder
caps 118 are formed on the metal posts 116 of the substrate 100a of
FIG. 2.
[0049] The solder caps 118 produce a buffering effect upon
packaging of the substrate for flip chip bonding and also assure
height uniformity.
[0050] Also, in order to enhance the force of adhesion between the
metal posts 116 and the solder caps 118, a second surface treatment
layer (not shown) is thinly formed therebetween, which is composed
of a Ni plating layer or a Ni alloy plating layer with or without
thereon any one selected from among a Pd plating layer, an Au
plating layer and sequentially disposed Pd plating layer and Au
plating layer.
[0051] The second surface treatment layer is bonded with the solder
caps 118 made of Sn, thus forming a second Ni.sub.x--Sn.sub.y-based
IMC layer at the interface therebetween.
[0052] Furthermore, an outer surface treatment layer (not shown)
may be formed on the outer surfaces of the metal posts 116 to
prevent corrosion and oxidation thereof
Method of Fabricating the Substrate for Flip Chip Bonding
1.sup.st Embodiment
[0053] FIGS. 4 to 9 are cross-sectional views sequentially showing
the process of fabricating the substrate for flip chip bonding as
shown in FIG. 2, in accordance with an embodiment of the invention.
Below, the method of fabricating the substrate 100a for flip chip
bonding according to the present embodiment is described with
reference to the above drawings.
[0054] As shown in FIG. 4, the solder resist layer 106 is formed on
the base substrate 102 having the pads 104, and the open portions
108 for exposing the pads 104 are formed in the solder resist layer
106. The open portions 108 may be formed through a mechanical
process such as LDA (Laser Direct Ablation) or through UV light
exposure and development.
[0055] Next, as shown in FIG. 5, a photosensitive resist 110 is
applied on the solder resist layer 106.
[0056] As the photosensitive resist 110, a high heat-resistant dry
film may be used so as to endure a reflow process at high
temperature of 260.degree. C. or more, and may have a thickness of
60 .mu.m or more to form post bumps having an appropriate
height.
[0057] Next, as shown in FIG. 6, openings 112 for exposing the pads
104 are formed in the photosensitive resist 110 through exposure
and development.
[0058] As such, the openings 112 are formed in a manner such that
portions of the photosensitive resist 110 other than portions
thereof applied on the pads 104 are exposed to UV light using a
predetermined mask pattern (not shown) and the unexposed portions
of the photosensitive resist 110 are removed using a developing
solution such as sodium carbonate (Na.sub.2CO.sub.3) or potassium
carbonate (K.sub.2CO.sub.3).
[0059] Next, as shown in FIG. 7, a solder paste is applied on the
pads 104 exposed by the openings 112, thus forming the base solder
layer 114.
[0060] The base solder layer 114 is formed in parts of the openings
112 through screen printing or the like.
[0061] Furthermore, the first surface treatment layer may be formed
on the base solder layer 114 in order to enhance the force of
adhesion between the metal posts 116 which are to be formed through
a subsequent plating process and the base solder layer 114.
[0062] The first surface treatment layer may be composed of a Ni
plating layer or a Ni alloy plating layer with or without thereon
any one selected from among a Pd plating layer, an Au plating layer
and sequentially disposed Pd plating layer and Au plating layer.
The first surface treatment layer is bonded with the base solder
layer 114 made of Sn, so that the first Ni.sub.x--Sn, based IMC
layer is formed at the interface therebetween.
[0063] Next, as shown in FIG. 8, the metal posts 116 are formed in
the openings 112.
[0064] The metal posts 116 are formed through Cu plating (including
electroless Cu plating and Cu electroplating), and have the same
height as that of the photosensitive resist 110.
[0065] Finally, as shown in FIG. 9, the photosensitive resist 110
is stripped, thus manufacturing the substrate 100a for flip chip
bonding as seen in FIG.
[0066] As such, the photosensitive resist 110 may be stripped using
a stripping solution such as NaOH or KOH. In the course of bonding
the Off of the stripping solution with the COOH.sup.+ of the dry
film resist, the exposed dry film resist may come off and may thus
be stripped.
[0067] Further the outer surface treatment layer may be formed on
the upper and outer surfaces of the metal posts 116 to prevent
corrosion and oxidation thereof.
Method of Fabricating the Substrate for Flip Chip Bonding
2.sup.nd Embodiment
[0068] FIGS. 10 to 13 are cross-sectional views sequentially
showing the process of fabricating the substrate for flip chip
bonding as shown in FIG. 3, in accordance with an embodiment of the
invention. In the description of the present embodiment, redundant
descriptions for fabrication procedures which are the same as or
corresponding to those of the prior embodiment are omitted. Below,
the method of fabricating the substrate for flip chip bonding
according to the present embodiment is described with reference to
the above drawings.
[0069] As shown in FIG. 10, a solder paste is applied on the pads
104 exposed by the openings 112 as shown in FIG. 7 so that parts of
the openings are filled therewith, thus preparing the base
substrate 102 having the base solder layer 114.
[0070] Next, as shown in FIG. 11, the metal posts 116 are formed on
the base solder layer 114 so that the parts of the openings 112 are
further filled therewith.
[0071] Also, the second surface treatment layer may be formed on
the metal posts 116 in order to enhance the force of adhesion of
the metal posts 116 to the solder caps 118.
[0072] The second surface treatment layer may be composed of a Ni
plating layer or a Ni alloy plating layer with or without thereon
any one selected from among a Pd plating layer, an Au plating layer
and sequentially disposed Pd plating layer and Au plating layer.
The second surface treatment layer is bonded with the solder caps
118 made of Sn, thus forming the second Ni.sub.x--Sn.sub.y-based
IMC layer at the interface therebetween.
[0073] Next, as shown in FIG. 12, a solder paste is printed on the
metal posts 116 exposed by the openings 112, thus forming the
solder caps 118.
[0074] Finally, as shown in FIG. 13, the photosensitive resist 110
is stripped, thus manufacturing the substrate 100b for flip chip
bonding as seen in FIG. 3.
[0075] As described hereinbefore, embodiments of the present
invention provide a substrate for flip chip bonding and a method of
fabricating the same. According to various embodiments, a base
solder layer producing a buffering effect owing to its high
softness is formed under metal posts, thus increasing impact
resistance, thereby reducing the generation of necking defects on
copper posts.
[0076] Also, according to various embodiments, the base solder
layer and/or solder caps are used, thus solving problems of height
and position non-uniformity, thereby reducing the generation of
mounting defects.
[0077] Also, according to various embodiments, the base solder
layer producing a buffering effect and/or the solder caps are used,
thus forming metal posts having improved height uniformity and
mounting reliability not only on a semiconductor substrate but also
on a package substrate.
[0078] Embodiments of the present invention may suitably comprise,
consist or consist essentially of the elements disclosed and may be
practiced in the absence of an element not disclosed. For example,
it can be recognized by those skilled in the art that certain steps
can be combined into a single step.
[0079] The terms and words used in the present specification and
claims should not be interpreted as being limited to typical
meanings or dictionary definitions, but should be interpreted as
having meanings and concepts relevant to the technical scope of the
present invention based on the rule according to which an inventor
can appropriately define the concept of the term to describe the
best method he or she knows for carrying out the invention.
[0080] The singular forms "a," "an," and "the" include plural
referents, unless the context clearly dictates otherwise.
[0081] As used herein and in the appended claims, the words
"comprise," "has," and "include" and all grammatical variations
thereof are each intended to have an open, non-limiting meaning
that does not exclude additional elements or steps.
[0082] Ranges may be expressed herein as from about one particular
value, and/or to about another particular value. When such a range
is expressed, it is to be understood that another embodiment is
from the one particular value and/or to the other particular value,
along with all combinations within said range.
[0083] Although the present invention has been described in detail,
it should be understood that various changes, substitutions, and
alterations can be made hereupon without departing from the
principle and scope of the invention. Accordingly, the scope of the
present invention should be determined by the following claims and
their appropriate legal equivalents.
* * * * *