U.S. patent application number 14/142570 was filed with the patent office on 2014-04-24 for semiconductor device having boosting circuit.
This patent application is currently assigned to Elpida Memory, Inc.. The applicant listed for this patent is Elpida Memory, Inc.. Invention is credited to Hiroki FUJISAWA, Shuichi KUBOUCHI, Hitoshi TANAKA.
Application Number | 20140111271 14/142570 |
Document ID | / |
Family ID | 44559400 |
Filed Date | 2014-04-24 |
United States Patent
Application |
20140111271 |
Kind Code |
A1 |
FUJISAWA; Hiroki ; et
al. |
April 24, 2014 |
SEMICONDUCTOR DEVICE HAVING BOOSTING CIRCUIT
Abstract
A semiconductor device includes a boosting circuit that boosts
an internal power supply voltage in a boosting range according to
an external power supply voltage, an external voltage-level
comparison circuit that compares the external power supply voltage
and a predetermined reference voltage, and a variable resistor
circuit that includes a variable resistor connected to an output
terminal of the boosting circuit. The variable resistor circuit
controls a resistance value of the variable resistor based on a
comparison result of the external voltage-level comparison
circuit.
Inventors: |
FUJISAWA; Hiroki; (Tokyo,
JP) ; KUBOUCHI; Shuichi; (Tokyo, JP) ; TANAKA;
Hitoshi; (Tokyo, JP) |
|
Applicant: |
Name |
City |
State |
Country |
Type |
Elpida Memory, Inc. |
Tokyo |
|
JP |
|
|
Assignee: |
Elpida Memory, Inc.
Tokyo
JP
|
Family ID: |
44559400 |
Appl. No.: |
14/142570 |
Filed: |
December 27, 2013 |
Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
|
|
13064237 |
Mar 11, 2011 |
8633758 |
|
|
14142570 |
|
|
|
|
Current U.S.
Class: |
327/536 |
Current CPC
Class: |
G05F 1/46 20130101; H02M
3/07 20130101; H02M 2001/0045 20130101; G11C 5/145 20130101; H02M
1/15 20130101 |
Class at
Publication: |
327/536 |
International
Class: |
G05F 1/46 20060101
G05F001/46 |
Foreign Application Data
Date |
Code |
Application Number |
Mar 12, 2010 |
JP |
2010-055606 |
Claims
1. (canceled)
2. A method of providing a voltage to an internal circuit of a
semiconductor device, said method comprising: receiving an external
voltage at a power supply terminal of said semiconductor device;
boosting said received voltage; and supplying said boosted voltage
to said internal circuit through a variable resistor circuit
serially interconnected between said internal circuit and an output
node of a circuit providing said boosting.
3. The method according to claim 2, further comprising controlling
a resistance of said variable resistor circuit based on a value of
said received external voltage.
4. The method according to claim 3, further comprising controlling
said variable resistor circuit resistance by comparing a reference
voltage with said received external voltage.
5. The method according to claim 4, wherein said variable resistor
comprises a plurality of serially-connected resistors with a
corresponding plurality of by-pass switches, said by-pass switches
being controlled by a corresponding plurality of comparators each
receiving said reference voltage and a voltage from a voltage
divider circuit supplied with said received external voltage.
6. The method according to claim 4, wherein said variable resistor
comprises a plurality of parallel-connected resistors with a
corresponding plurality of by-pass switches, each said by-pass
switch connected serially with a respective one of the
parallel-connected resistors, said by-pass switches being
controlled by a corresponding plurality of comparators each
receiving said reference voltage and a voltage from a voltage
divider circuit supplied with said received external voltage.
7. The method according to claim 6, wherein said variable resistor
further comprises a shunt resistor serially connected to said
plurality of parallel-connected resistors and a shunt resistor
by-pass switch selectively by-passing said shunt resistor, said
method further comprising: detecting an amount of current flowing
through said variable resistor; and controlling said shunt resistor
by-pass switch based on said current amount detection.
8. The method according to claim 7, further comprising controlling
an oscillator used in said boosting, by comparing an output voltage
of said variable resistor with a second reference voltage.
9. The method according to claim 4, wherein said comparing a
reference voltage with said received external voltage comprises:
dividing said external voltage into a plurality of
serially-interconnected voltages; inputting each of a divided
voltage into one of a plurality of comparators, each said
comparator thereby comparing of said divided voltages with said
reference voltage; and controlling by-pass switches of said
variable resistor based on outputs of said plurality of
comparators.
10. The method according to claim 4, wherein said variable resistor
circuit sets a first resistance value for said variable resistor
circuit when said comparing indicates a value lower than said
reference voltage and sets a second resistance value for said
variable resistor circuit when said comparing indicates a higher
value, said second resistance value being higher than said first
resistance value.
11. The method according to claim 3, further comprising
additionally controlling said variable resistor circuit resistance
based on an amount of current flowing through the variable resistor
circuit.
12. The method according to claim 4, wherein said reference voltage
is an expected standard value of said received external
voltage.
13. The method according to claim 12, further comprising smoothing
said voltage supplied to said internal circuit, using a smoothing
capacitor at an output node of said variable resistor circuit.
14. The method according to claim 13, said reference voltage being
set to said expected standard value thereby permitting a
predetermined minimal size of said smoothing capacitor to used,
based upon an amount of ripple in said smoothing capacitor in view
of said controlling said resistance of said variable resistor
circuit.
15. A method of providing a voltage to an internal circuit of a
semiconductor device with a predetermined controlled amount of
ripple, said method comprising: providing a reference voltage at
least substantially equal to a predetermined standard value of a
voltage of an external power supply voltage; receiving an external
voltage at a power supply terminal of said semiconductor device;
boosting said received voltage; supplying said boosted voltage
through a resistor circuit serially interconnected between said
internal circuit and an output node of a circuit providing said
boosting; and smoothing a voltage at an output of said resistor
circuit, wherein a resistance of said resistor circuit is
controlled based on a comparison with said reference voltage.
16. The method according to claim 15, further comprising
additionally controlling said resistor circuit resistance based on
an amount of current flowing through the resistor circuit.
17. The method according to claim 15, wherein said resistor circuit
comprises a plurality of serially-connected resistors with a
corresponding plurality of by-pass switches, said by-pass switches
being controlled by a corresponding plurality of comparators each
receiving said reference voltage and a voltage from a voltage
divider circuit supplied with said received external voltage.
18. The method according to claim 15, wherein said resistor circuit
comprises a plurality of parallel-connected resistors with a
corresponding plurality of by-pass switches, each said by-pass
switch connected serially with a respective one of the
parallel-connected resistors, said by-pass switches being
controlled by a corresponding plurality of comparators each
receiving said reference voltage and a voltage from a voltage
divider circuit supplied with said received external voltage.
19. The method according to claim 15, wherein a resistance value of
said resistor circuit is set to a first resistance value when said
comparing indicates a value lower than said reference voltage and
is set to a second resistance value for said resistor circuit when
said comparing indicates a higher value, said second resistance
value being higher than said first resistance value.
20. The method according to claim 15, further comprising
controlling an oscillator used in said boosting, by comparing an
output voltage of said resistor circuit with a second reference
voltage.
21. A method of reducing a size of a smoothing capacitor needed to
provide an expected voltage to an internal circuit of a
semiconductor device, said method comprising: receiving an external
voltage at a power supply terminal of said semiconductor device;
boosting said received voltage; supplying said boosted voltage to
said internal circuit through a resistor circuit serially
interconnected between said internal circuit and an output node of
a circuit providing said boosting; and controlling said resistor
circuit resistance by comparing a reference voltage with said
received external voltage, wherein said reference voltage is set as
at least substantially equal to an expected standard value of said
received external voltage.
Description
CROSS-REFERENCE TO RELATED APPLICATIONS
[0001] This application is a Continuation application of U.S.
patent application Ser. No. 13/064,237, filed on Mar. 11, 2011.
[0002] This application is based on and claims priority from
Japanese Patent Application No. 2010-055606 filed on Mar. 12, 2010.
The disclosure thereof is incorporated herein by reference in its
entirety.
BACKGROUND OF THE INVENTION
[0003] 1. Field of the Invention
[0004] The present invention relates to a semiconductor device,
and, more particularly relates to a semiconductor device that
prevents an internal power supply voltage from exceeding a
tolerance value.
[0005] 2. Description of Related Art
[0006] In semiconductor devices such as a DRAM (Dynamic Random
Access Memory) and a FLASH memory, a boosting circuit is used for
generating an internal power supply voltage from an external power
supply voltage (see, for example, Japanese Patent Application
Laid-open No. 2008-79493). The internal power supply voltage
generated by the boosting circuit is supplied to internal circuits
of the semiconductor device.
[0007] The boosting circuit is a circuit that performs a function
of pulling up (boosting) the internal power supply voltage at clock
cycles. A voltage level of the internal power supply voltage
gradually drops due to consumption of electric charge by the
internal circuits. However, even if the voltage level drops, it is
pulled up by the boosting circuit. Consequently, on average, a
constant voltage level is maintained.
[0008] A pull-up range (boosting range) of the internal power
supply voltage by the boosting circuit depends on the external
power supply voltage. That is, the higher the external power supply
voltage, the larger the boosting range, and the lower the external
power supply voltage, the smaller the boosting range.
SUMMARY
[0009] It has become necessary to intensify a supply capability of
the boosting circuit along with upgrading the capacity and speed of
recent semiconductor devices. Typically, a smoothing capacitor is
provided on an output side of the boosting circuit to eliminate
ripples. In case the supply capability of the boosting circuit is
intensified, the ensuing increased ripples in the internal power
supply voltage will necessitate a larger smoothing capacitor.
[0010] However, a larger capacitor requires a larger surface area.
Therefore, a technique that enables to eliminate the ripples
without having to use a larger smoothing capacitor is required. One
such technique being studied by the present inventor(s) is
insertion of a resistor on the output side of the boosting circuit.
One of the objects for eliminating the ripples is to prevent damage
to the internal circuits due to a supply of unnecessarily high
voltages. The insertion of the resistor causes a voltage drop due
to resistance, and thus there is a reduced possibility of the
internal circuits being supplied unnecessarily high voltages.
[0011] However, insertion of a resistor on the output side of the
boosting circuit leads to an overall drop in the internal power
supply voltage. Particularly when there is a drop in the external
power supply voltage, an adequate internal power supply voltage may
not be derived. Furthermore, the resistor consumes power, which is
not preferable from the point of view of reduction of power
consumption. Therefore, it is desired that, even when a resistor is
inserted on the output side of the boosting circuit, an adequate
internal power supply voltage is maintained in addition to
reduction in the power consumption by the resistor.
[0012] In one embodiment, there is provided a semiconductor device
comprising: a boosting circuit that boosts an internal power supply
voltage in a boosting range according to an external power supply
voltage; a comparison circuit that compares the external power
supply voltage and a predetermined reference voltage; and a
variable resistor circuit that includes a variable resistor
connected to an output terminal of the boosting circuit, wherein
the variable resistor circuit controls a resistance value of the
variable resistor based on a comparison result of the comparison
circuit.
[0013] According to the present invention, an adequate voltage can
be maintained as an internal power supply voltage even when there
is a decrease in an external power supply voltage; because, a
resistance value of a variable resistor is controlled based on a
comparison result of the external power supply voltage and a
reference voltage. Moreover, because the resistance value of the
variable resistor is optimized according to the external power
supply voltage, power consumption by the resistor can be
reduced.
BRIEF DESCRIPTION OF THE DRAWINGS
[0014] The above features and advantages of the present invention
will be more apparent from the following description of certain
preferred embodiments taken in conjunction with the accompanying
drawings, in which:
[0015] FIG. 1 is a schematic diagram indicating a functional block
of a semiconductor device according to a first embodiment of the
present invention;
[0016] FIG. 2A shows the circuit configuration of the OSC circuit
according to a first embodiment of the present invention;
[0017] FIG. 2B is an example of the complementary clock signals
according to a first embodiment of the present invention;
[0018] FIG. 2C shows the circuit configuration of the charge pump
circuit according to a first embodiment of the present
invention;
[0019] FIG. 3A shows an outline of a variation of the output
voltage VPR against the external power supply voltage VDD in the
first embodiment of the present invention;
[0020] FIG. 3B is a schematic diagram showing a variation in the
internal power supply voltage VCC output from the variable resistor
circuit according to a first embodiment of the present
invention;
[0021] FIG. 4 shows the circuit configurations of the variable
resistor circuit and the external voltage-level comparison circuit
according to a first embodiment of the present invention;
[0022] FIG. 5A shows a circuit configuration of the comparator
according to a first and a second embodiment of the present
invention;
[0023] FIG. 5B shows a circuit configuration of the switch element
according to a first and a second embodiment of the present
invention;
[0024] FIG. 6A is a graph showing a relation between the external
power supply voltage VDD and the output voltage V.sub.DIV (divided
voltages V.sub.1 to V.sub.3) of the voltage dividing circuit
according to a first embodiment of the present invention;
[0025] FIG. 6B is a graph showing a relation between the first to
fourth modes M1 to M4 and a resistance value SR that is realized
between the node f and the output node b due to the on/off status
of the switch elements according to a first embodiment of the
present invention;
[0026] FIG. 7 is a schematic functional block diagram of a
semiconductor device according to a second embodiment of the
present invention;
[0027] FIG. 8 shows circuit configurations of the OSC circuit and
the OSC control circuit according to a second embodiment of the
present invention;
[0028] FIG. 9 shows circuit configurations of the variable resistor
circuit and the external voltage-level comparison circuit according
to a second embodiment of the present invention;
[0029] FIG. 10A is a graph showing a relation between the external
power supply voltage VDD and output voltages V.sub.DIV of the
voltage dividing circuit (divided voltages V.sub.1 to V.sub.5)
according to a second embodiment of the present invention;
[0030] FIG. 10B is a graph showing a relation between the first to
sixth modes M1 to M6 and the resistance values SR that are realized
between the node f and the output node b due to the on/off status
of the switch elements according to a second embodiment of the
present invention; and
[0031] FIGS. 11A to 11C show an outline of the variation of the
internal power supply voltage VPP output by the variable resistor
circuit according to a second embodiment of the present
invention.
DETAILED DESCRIPTION OF THE EMBODIMENTS
[0032] Preferred embodiments of the present invention will be
explained below in detail with reference to the accompanying
drawings.
[0033] FIG. 1 is a schematic diagram indicating a functional block
of a semiconductor device 1a according to a first embodiment of the
present invention.
[0034] The semiconductor device 1a, for example, is a semiconductor
memory device such as a DRAM, a FLASH memory, and a PRAM (Phase
change Random Access Memory). As shown in FIG. 1, the semiconductor
device 1a includes a boosting circuit 10a, a variable resistor
circuit 20a, an external voltage-level comparison circuit 21a, a
capacitor 22, and an internal circuit 30. The semiconductor device
1a includes a power supply terminal 2 that serves as an external
terminal and to which an external power supply voltage VDD is
supplied. The semiconductor device 1a includes other types of
terminals such as a command terminal, an address terminal, and a
data input and output terminal; however, explanations of these
terminals will be omitted.
[0035] The boosting circuit 10a and the external voltage-level
comparison circuit 21a are connected to the power supply terminal 2
via an input node a, and each receives a supply of the external
power supply voltage VDD from outside. The external voltage-level
comparison circuit 21a additionally receives, from a not shown
constant voltage source, a supply of a reference voltage VREF1
equal to a standard value of the external power supply voltage
VDD.
[0036] The boosting circuit 10a is a circuit that uses the external
power supply voltage VDD to generate a voltage VPR. Specifically,
the boosting circuit 10a boosts an internal power supply voltage on
every clock cycle/pulse in a boosting range according to the
external power supply voltage VDD. This boosting operation is
realized by an OSC (Oscillator) circuit 11a (clock circuit) and a
charge pump circuit 12 shown in FIG. 1. Circuit configurations and
operations of the OSC circuit 11a and the charge pump circuit 12
are explained later in detail.
[0037] The variable resistor circuit 20a includes, though not shown
in FIG. 1, a variable resistor that is connected between an output
terminal of the boosting circuit 10a and an output node b, and at
least one switch element that controls a resistance value of the
variable resistor. Because the resistor connected in the circuit
causes a voltage drop, the voltage at the output node b (internal
power supply voltage VCC) will be equivalent to a value obtained by
subtracting the voltage drop due to the variable resistor from the
output voltage VPR of the boosting circuit 10a. A circuit
configuration and operations of the variable resistor circuit 20a
are explained later in detail.
[0038] The external voltage-level comparison circuit 21a is a
circuit that compares the external power supply voltage VDD and the
reference voltage VREF1, and outputs a comparison result thereof to
the variable resistor circuit 20a. The variable resistor circuit
20a controls the resistance value of the variable resistor based on
the comparison result received from the external voltage-level
comparison circuit 21a. A circuit configuration and operations of
the external voltage-level comparison circuit 21a are explained
later in detail.
[0039] The capacitor 22 is connected between the output node b and
ground wiring lines (hereinafter, "ground potential") to which a
ground potential is supplied. The capacitor 22 is a so-called
smoothing capacitor and plays the role of removing ripples from the
internal power supply voltage VCC. The capacitance of the capacitor
22 is hereinafter denoted by reference symbol C.sub.D.
[0040] The internal circuit 30 is a circuit that realizes the
principal function of the semiconductor device 1a, and operates on
an operating power supply of the internal power supply voltage VCC
supplied through the output node b. For example, if the
semiconductor device 1a were a DRAM, the internal circuit 30
corresponds to a memory cell array or a peripheral circuit
thereof.
[0041] In the first embodiment, assuming that a consumed current
I.sub.L of the internal circuit 30 is constant, the variable
resistor circuit 20a is provided to prevent unnecessarily high
voltages from being supplied to the internal circuit 30 when the
boosting circuit 10a boosts the internal power supply voltage VCC
in the boosting range according to the external power supply
voltage VDD under the assumed condition. This is explained in
detail later.
[0042] The circuit configurations and the operations of the OSC
circuit 11a, the charge pump circuit 12, the variable resistor
circuit 20a, and the external voltage-level comparison circuit 21a
are explained below in detail in this order.
[0043] FIG. 2A shows the circuit configuration of the OSC circuit
11a. As shown in FIG. 2A, the OSC circuit 11a includes a delay line
55a having an odd number (five in FIG. 2A) of inverters, a buffer
56, and an inverter 57. An output of the delay line 55a is
feedback-connected to an input of the delay line 55a as well as
being input into the buffer 56 and the inverter 57. Due to the
above configuration, complementary clock signals .PHI. and /.PHI.
are output from the buffer 56 and the inverter 57,
respectively.
[0044] FIG. 2B is an example of the complementary clock signals
.PHI. and /.PHI.. As shown in FIG. 2B, both the clock signals .PHI.
and /.PHI. are rectangular signals with repeating lows and highs at
predetermined intervals and with mutually reversed phases. Voltage
values of the clock signals .PHI. and /.PHI. are determined
according to operating power supply voltages of each of the
inverters and the buffer 56 in the OSC circuit 11a. Although not
shown in FIG. 2B, the operating power supply voltages of each of
the inverters and the buffer 56 are set to the external power
supply voltage VDD and the ground potential (which is 0).
Accordingly, the voltage values of the clock signals .PHI. and
/.PHI. are 0 at low and VDD at high.
[0045] FIG. 2C shows the circuit configuration of the charge pump
circuit 12. As shown in FIG. 2C, the charge pump circuit 12
includes a booster circuit 40, a substrate potential generating
circuit 41, and a transfer gate 42. Although not a constituent
element of the charge pump circuit 12, the capacitor 22 (smoothing
capacitor) of FIG. 1 is also shown in FIG. 2C.
[0046] The booster circuit 40 includes a capacitor 43 and a
capacitor 44. The capacitor 43 is connected between power supply
wiring lines to which the external power supply voltage VDD is
supplied (hereinafter, the power supply wiring lines are simply
referred to as "external power supply voltage VDD") and an input
terminal of the clock signal .PHI.. The capacitor 44 is connected
between the external power supply voltage VDD and an input terminal
of the clock signal /.PHI.. The capacitors 43 and 44 both have the
same capacitance of C.sub.1. N-channel MOS transistors 45 and 46
are connected in parallel between the capacitor 43 and the external
power supply voltage VDD, and N-channel MOS transistors 47 and 48
are connected in parallel between the capacitor 44 and the external
power supply voltage VDD. In the following explanations, a
connection point of the transistor 46 and the capacitor 43 is
denoted by a node c and a connection point of the transistor 47 and
the capacitor 44 is denoted by a node d. Gates of the transistors
45 and 48 are connected to the external power supply voltage VDD, a
gate of the transistor 46 is connected to a drain of the transistor
47, and a gate of the transistor 47 is connected to a drain of the
transistor 46.
[0047] The substrate potential generating circuit 41 includes
P-channel MOS transistors 49 and 50. A gate of the transistor 49 is
connected to the node d and a source of the transistor 49 is
connected to the node c. A gate of the transistor 50 is connected
to the node c and a source of the transistor 50 is connected to the
node d. A drain and a back gate of the transistor 49 and a drain
and a back gate of the transistor 50 are connected to each other,
and between a connection point thereof, which is denoted by a node
e, and the ground potential, a capacitor 51 is connected. In the
following explanations, a potential of the node e is denoted by a
substrate potential V.sub.BG. In an initial state, the substrate
potential V.sub.BG is a floating potential.
[0048] The transfer gate 42 includes P-channel MOS transistors 52
and 53. A gate of the transistor 52 is connected to the node d and
a source of the transistor 52 is connected to the node c. A gate of
the transistor 53 is connected to the node c and a source of the
transistor 53 is connected to the node d. A drain of the transistor
52 and a drain of the transistor 53 are connected to each other.
The output voltage VPR of the boosting circuit 10a is derived from
a node f, which is a connection point of the transistors 52 and 53.
The substrate voltage V.sub.BG is supplied to back gates of the
transistors 52 and 53.
[0049] Due to the above-described operations of the booster circuit
40, the substrate potential generating circuit 41, and the transfer
gate 42, the charge pump circuit 12 boosts the output voltage VPR
using the external power supply voltage VDD. The operations of the
booster circuit 40, the substrate potential generating circuit 41,
and the transfer gate 42 are explained below in detail.
[0050] Assuming that the potential of the clock signal .PHI. is 0
and that of the clock signal /.PHI. is VDD immediately upon power
activation, the potential at the node c is charged to a level of at
least VDD-Vt due to the turning on of the transistor 45. Vt is a
threshold voltage of the transistors 45 to 48. When the potentials
of the clock signals .PHI. and /.PHI. switch to VDD and 0,
respectively, the potential at the node c is boosted to a maximum
of 2VDD-Vt. Because usually 2VDD-Vt is greater than or equal to
VDD+Vt, the transistor 47 is fully turned on, and the node d of the
capacitor 44 is charged to VDD.
[0051] When the potentials of the clock signals .PHI. and /.PHI.
again switch to 0 and VDD, respectively, the potential at the node
c is charged to a maximum of 2VDD. Due to this, the transistors 45
and 46 are turned on and the transistors 47 and 48 are turned off.
The potential at the node c becomes VDD due to the turning on of
the transistor 46. Upon subsequent repetition of the operation
mentioned above, the potentials at the nodes c and d alternate
between 2VDD on a high potential side and VDD on a low potential
side. When the node c is at a high potential and the node d is at a
low potential, the transistor 49 is turned on and the transistor 50
is turned off, and the substrate potential V.sub.BG becomes equal
to the potential at the node c. At the same time, the transistor 52
is turned on and the transistor 53 is turned off, the nodes f and c
are connected, and their potentials become equal to the output
voltage VPR.
[0052] The output voltage VPR is explained below with a specific
value. The capacitor 22 (smoothing capacitor) whose capacitance is
C.sub.D, is connected to an output side (output node b) of the
charge pump circuit 12, as shown in FIG. 2C. In actuality, the
variable resistor circuit 20a is inserted between the node f and
the output node b, as shown in FIG. 1. However, its presence is
ignored here, and the function of the variable resistor circuit 20a
is explained later. It is also necessary in actuality to take into
consideration the effect of the capacitor on the internal circuit
30. However, this fact is also ignored here. In such a case, when
the potential of the clock signal .PHI. is VDD and the potential of
the clock signal /.PHI. is 0, it is as though the capacitors 43 and
22 are connected in series between the external power supply
voltage VDD and the ground potential.
[0053] Thus, the charge equivalent to VDD accumulated in the
capacitor 43 and the charge supplied from the external power supply
voltage VDD are distributed to the capacitors 22 and 43, and the
output voltage VPR is determined by the charge distributed to the
capacitors 22 and 43 and the consumed current I.sub.L.
Specifically, an average VPR (av.) of the output voltage VPR is
determined by the following Expression (1).
VPR ( av . ) = 2 VDD - T 2 C 1 I L ( 1 + C D C D + C 1 ) 1 2
.apprxeq. 2 VDD - T 2 C 1 I L ( C D >> C 1 ) ( 1 )
##EQU00001##
[0054] Thus, as is understood from the Expression (1), the output
voltage VPR increases as the external power supply voltage VDD
increases, and falls as the consumed current I.sub.L increases. The
variable resistor circuit 20a according to the first embodiment is
provided to prevent a high output voltage VPR due to an increase in
the external power supply voltage VDD from being input into the
internal circuit 30.
[0055] FIG. 3A shows an outline of a variation of the output
voltage VPR in the first embodiment. In FIG. 3A, the clock cycle is
denoted by reference symbol t.sub.c. As shown in FIG. 3A, when the
external power supply voltage VDD is equal to the reference voltage
VREF1, an average level of the node f becomes VPR1. When
VREF1<V.sub.a<VDD<V.sub.b, an average level of the node f
becomes VPR2, which is higher than VPR1. Voltages V.sub.a and
V.sub.b are explained later.
[0056] As is understood from FIG. 3A and the Expression (1), when
there is an increase in the external power supply voltage VDD due
to fluctuation, there is a corresponding increase in the average
value of the output voltage VPR. Thus, there are chances that the
internal circuit 30 may receive unnecessarily high voltages due to
an increase in the external power supply voltage VDD.
[0057] The circuit configurations and operations of the variable
resistor circuit 20a and the external voltage-level comparison
circuit 21a are explained below in detail.
[0058] FIG. 4 shows the circuit configurations of the variable
resistor circuit 20a and the external voltage-level comparison
circuit 21a. As shown in FIG. 4, the variable resistor circuit 20a
includes three resistor elements R.sub.1 to R.sub.3 that are
connected in series between the node f and the output node b shown
in FIG. 2C, and switch elements SW.sub.1 to SW.sub.3 that are
connected in parallel to the resistor elements R.sub.1 to R.sub.3,
respectively. The external voltage-level comparison circuit 21a
includes a voltage dividing circuit 60a that includes four resistor
elements R.sub.A to R.sub.D connected in series between the
external power supply voltage VDD and the ground potential, and a
comparison circuit 61a that includes three comparators P.sub.1 to
P.sub.3.
[0059] The external power supply voltage VDD is divided by the
resistor elements R.sub.A to R.sub.D in the voltage dividing
circuit 60a. Specifically, a divided voltage V.sub.1 is derived
from a connection point of the resistor elements R.sub.A and
R.sub.B, a divided voltage V.sub.2 is derived from a connection
point of the resistor elements R.sub.B and R.sub.C, and a divided
voltage V.sub.3 is derived from a connection point of the resistor
elements R.sub.C and R.sub.D. A magnitude relation between the
divided voltages V.sub.1 to V.sub.3 is
V.sub.1>V.sub.2>V.sub.3. The voltage that is output from the
voltage dividing circuit 60a (divided voltages V.sub.1 to V.sub.3)
is hereinafter collectively referred to as divided output voltage
V.sub.DIV.
[0060] The comparison circuit 61a compares the divided voltages
V.sub.1 to V.sub.3 and the reference voltage VREF1 by using the
comparators P.sub.1 to P.sub.3. Specifically, the comparator
P.sub.1 compares the divided voltage V.sub.1 and the reference
voltage VREF1, and if the divided voltage V.sub.1 is lower than the
reference voltage VREF1, makes a comparison result signal ON.sub.1
active, and if not, makes the comparison result signal ON.sub.1
inactive. Similarly, the comparator P.sub.2 compares the divided
voltage V.sub.2 and the reference voltage VREF1, and if the divided
voltage V.sub.2 is lower than the reference voltage VREF1, makes a
comparison result signal ON.sub.2 active, and if not, makes the
comparison result signal ON.sub.2 inactive. Likewise, the
comparator P.sub.3 compares the divided voltage V.sub.3 and the
reference voltage VREF1, and if the divided voltage V.sub.3 is
lower than the reference voltage VREF1, makes a comparison result
signal ON.sub.3 active, and if not, makes the comparison result
signal ON.sub.3 inactive.
[0061] FIG. 5A shows a circuit configuration of the comparator
P.sub.1. Circuit configurations of the comparators P.sub.2 and
P.sub.3 are similar to that of the comparator P.sub.1.
[0062] As shown in FIG. 5A, the comparator P.sub.1 has a three
level structure including a bias circuit, a differential input
amplifying circuit, and an output circuit.
[0063] The bias circuit includes a resistor element 62, N-channel
MOS transistors 63 and 64, and a P-channel MOS transistor 65, and
generates and outputs bias voltages V.sub.GN and V.sub.GP, which
are constant voltages. In further detail, the resistor element 62
and the transistor 63 are connected in series between the external
power supply voltage VDD and the ground potential. The transistors
65 and 64 are also connected in series between the external power
supply voltage VDD and the ground potential. The transistors 63 and
65 are diode connected, and a gate of the transistor 63 and a gate
of the transistor 64 are connected to each other. The bias voltages
V.sub.GP and V.sub.GN are derived from drains of the transistors 65
and 63, respectively. Due to the above configuration, the bias
voltages V.sub.GN and V.sub.GP, which are constant voltages, are
output from the drains of the transistors 63 and 65,
respectively.
[0064] The differential output amplifying circuit includes
P-channel MOS transistors 66 to 70 and N-channel MOS transistors 71
to 76, and performs a differential amplification of the divided
voltage V.sub.1 and the reference voltage VREF1. In further detail,
the transistors 66 and 71 are connected in series between the
external power supply voltage VDD and the ground potential. The
transistors 68 and 76 are also connected in series between the
external power supply voltage VDD and the ground potential. A
source of the transistor 67 is connected to the external power
supply voltage VDD. The transistors 69 and 72 are connected in
series between a drain of the transistor 67 and the ground
potential. The transistors 70 and 75 are also similarly connected
in series between the drain of the transistor 67 and the ground
potential. The transistor 73 is connected between a drain of the
transistor 72 and the ground potential. The transistor 74 is
connected between a drain of the transistor 75 and the ground
potential.
[0065] The transistors 72 and 75 are diode connected. A gate of the
transistor 66 and a gate of the transistor 68 are connected to each
other. Similarly, a gate of the transistor 71 and a gate of the
transistor 72 are connected to each other. Likewise, a gate of the
transistor 75 and a gate of the transistor 76 are connected to each
other. A gate of the transistor 73 is connected to a drain of the
transistor 74 and a gate of the transistor 74 is connected to a
drain of the transistor 73.
[0066] The divided voltage V.sub.1 and the reference voltage VREF1
are input into gates of the transistors 69 and 70, respectively.
The bias voltage V.sub.GP from the bias circuit is also input into
a gate of the transistor 67. An output voltage (voltage obtained as
a result of differential amplification) of the differential input
amplifying circuit is derived from a connection point of the
transistors 68 and 76.
[0067] When the divided voltage V.sub.1 is lower than the reference
voltage VREF1, the transistors 69, 72, 71, 66, and 68 are turned
on, and the transistors 70, 75, and 76 are tuned off. As a result,
the output voltage of the differential input amplifying circuit is
equal to the external power supply voltage VDD. On the other hand,
when the divided voltage V.sub.1 is higher than the reference
voltage VREF1, the transistors 70, 75, and 76 are tuned on whereas
the transistors 69, 72, 71, 66, and 68 are turned off. As a result,
the output voltage of the differential input amplifying circuit
becomes equal to the ground potential. Thus, the output voltage of
the differential input amplifying circuit becomes equal to the
external power supply voltage VDD when the divided voltage V.sub.1
is even slightly lower than the reference voltage VREF1 and becomes
equal to the ground potential when the divided voltage V.sub.1 is
even slightly higher than the reference voltage VREF1, and is in
effect, a value obtained by amplifying a difference between the
divided voltage V.sub.1 and the reference voltage VREF1. The
transistors 73 and 74 are provided for giving hysteresis to the
result of the differential amplification.
[0068] The output circuit includes P-channel MOS transistors 77 and
79 and N-channel MOS transistors 78 and 80, and generates and
outputs the comparison result signal ON.sub.1 that reflects the
result of the differential amplification. Specifically, the
transistors 77 and 78 are connected in series between the external
power supply voltage VDD and the ground potential. Similarly, the
transistors 79 and 80 are also connected in series between the
external power supply voltage VDD and the ground potential. The
output voltage from the differential input amplifying circuit is
input into agate of the transistor 77. The bias voltages V.sub.GN
and V.sub.GP from the bias circuit are input into the transistors
78 and 79, respectively. A gate of the transistor 80 is connected
to a connection point of the transistors 77 and 78, and the
comparison result signal ON.sub.1 is derived from a connection
point of the transistors 79 and 80. Due to the above configuration,
the comparison result signal ON.sub.1 has the voltage of the
external power supply voltage VDD (active state) when the divided
voltage V.sub.1 is lower than the reference voltage VREF1, and has
the potential of the ground potential (inactive state) when the
divided voltage V.sub.1 is not lower than the reference voltage
VREF1.
[0069] Referring back to FIG. 4, the comparison result signals
ON.sub.1 to ON.sub.3 are input into the switch elements SW.sub.1 to
SW.sub.3, respectively, in the variable resistor circuit 20a. The
switch elements SW.sub.1 to SW.sub.3 are turned on when the
comparison result signal being input is active and turned off when
it is not active.
[0070] FIG. 5B shows a circuit configuration of the switch element
SW.sub.3. Circuit configurations of the switch elements SW.sub.1
and SW.sub.2 are similar to that of the switch element
SW.sub.3.
[0071] As shown in FIG. 5B, the switch element SW.sub.3 includes an
inverter 81 that receives the external power supply voltage VDD and
the ground potential as operating power supply, N-channel MOS
transistors 82 and 83, P-channel MOS transistors 84 to 86, and a
wiring 87 that is arranged in parallel with a corresponding
resistor element R.sub.3.
[0072] The comparison result signal ON.sub.3 is input into the
inverter 81 and a gate of the transistor 83. An output of the
inverter 81 is input into a gate of the transistor 82. The
transistors 84 and 82 are connected in series between the wiring 87
and the ground potential. Similarly, the transistors 85 and 83 are
also connected in series between the wiring 87 and the ground
potential. A gate of the transistor 84 is connected to a drain of
the transistor 85 (a connection point of the transistors 85 and
83), and a gate of the transistor 85 is connected to a drain of the
transistor 84 (a connection point of the transistors 84 and 82).
Back gates of the transistors 84 and 85 are connected to the wiring
87. The transistor 86 is inserted in between the wiring 87, and a
gate thereof is connected to the drain of the transistor 85.
[0073] With the above configuration, when the comparison result
signal 0N.sub.3 is active, that is, when the voltage of the
comparison result signal ON.sub.3 becomes equal to the external
power supply voltage VDD, the transistors 82 and 85 are turned off,
the transistors 83 and 84 are turned on, and the ground potential
is supplied to the gate of the transistor 86. As a result, the
transistor 86 is turned on, and the wiring 87 becomes conductive.
That is, the resistor element R.sub.3 is short-circuited. On the
other hand, when the comparison result signal ON.sub.3 is not
active, that is, when the voltage of the comparison result signal
ON.sub.3 becomes equal to the ground potential, the transistors 82
and 85 are turned on, the transistors 83 and 84 are turned off, and
the output voltage VPR is supplied to the gate of the transistor
86. As a result, the transistor 86 is turned off, and the wiring 87
is disconnected.
[0074] FIG. 6A is a graph showing a relation between the external
power supply voltage VDD and the output voltage V.sub.DIV (divided
voltages V.sub.1 to V.sub.3) of the voltage dividing circuit 60a.
In FIG. 6A, a horizontal axis represents the external power supply
voltage VDD, and a vertical axis represents the output voltage
V.sub.DIV. As shown in FIG. 6A, when each of the divided voltages
V.sub.1 to V.sub.3 is equal to the reference voltage VREF1, the
external power supply voltage VDD is equal to voltages V.sub.a to
V.sub.c (V.sub.a<V.sub.b<V.sub.c). With the voltages V.sub.a
to V.sub.c, a correspondence can be established between an
activation status of the comparison result signals ON.sub.1 to
ON.sub.3 and the magnitude relation of the external power supply
voltage VDD.
[0075] That is, when the comparison result signals ON.sub.1 to
ON.sub.3 are all active (hereinafter, "first mode M1"), all the
divided voltages V.sub.1 to V.sub.3 are lower than the reference
voltage VREF1, and hence the external power supply voltage VDD will
be lower than the voltage V.sub.a. When the comparison result
signal ON.sub.1 is inactive, and the comparison result signals
ON.sub.2 and ON.sub.3 are active (hereinafter, "second mode M2"),
the value of the external power supply voltage VDD will be between
the voltages V.sub.a and V.sub.b. When the comparison result
signals ON.sub.1 and ON.sub.2 are inactive, and the comparison
result signal ON.sub.3 is active (hereinafter, "third mode M3"),
the value of the external power supply voltage VDD will be between
the voltages V.sub.b and V.sub.c. When the comparison result
signals ON.sub.1 to ON.sub.3 are all inactive (hereinafter, "fourth
mode M4"), the value of the external power supply voltage VDD will
be higher than the voltage V.sub.c.
[0076] FIG. 6B is a graph showing a relation between the first to
fourth modes M1 to M4 and a resistance value SR that is realized
between the node f and the output node b due to the on/off status
of the switch elements SW.sub.1 to SW.sub.3. In FIG. 6B, a
horizontal axis represents the external power supply voltage VDD
and a vertical logarithmic axis represents the resistance value
SR.
[0077] As shown in FIG. 6B, out of the four modes, the resistance
value SR is the lowest, that is, substantially zero, in the first
mode M1. This is compliant with all the resistor elements R.sub.1
to R.sub.3 being short-circuited due to the switch elements
SW.sub.1 to SW.sub.3 being switched on. Due to the presence of
wiring resistance or the like, the resistance value SR normally
cannot be strictly zero. The resistance value SR is the second
lowest in the second mode M2, and is substantially equal to a
resistance value R.sub.1 of the resistor element R.sub.1 (a
resistance value of a resistor element X is hereinafter denoted by
X). This is compliant with the resistor element R.sub.1 not being
short-circuited due to the switch element SW.sub.1 being turned
off, and the resistor elements R.sub.2 and R.sub.3 being
short-circuited due to the switch elements SW.sub.2 and SW.sub.3
being turned on. The resistance value SR is the third lowest in the
third mode M3, and substantially equal to the sum of the resistance
values R.sub.1 and R.sub.2 when the resistor elements R.sub.1 and
R.sub.2 are connected in series. This is compliant with the
resistor elements R.sub.1 and R.sub.2 not being short-circuited due
to the switch elements SW.sub.1 and SW.sub.2 being turned off and
the resistor element R.sub.3 being short-circuited due to the
switch element SW.sub.3 being turned on. The resistance value SR is
the highest in the fourth mode M4 and substantially equal to the
sum of the resistance values R.sub.1, R.sub.2, and R.sub.3, when
the resistor elements R.sub.1 to R.sub.3 are connected in series.
This is compliant with none of the resistor elements R.sub.1 to
R.sub.3 being short-circuited due to the switch elements SW.sub.1
to SW.sub.3 being turned off.
[0078] In this manner, the resistance value SR between the node f
and the output node b varies according to the mode of the variable
resistor circuit 20a. Furthermore, because the resistance value SR
increases as the external power supply voltage VDD increases, the
value of the internal power supply voltage VCC can be decreased as
the external power supply voltage VDD increases. As a result, the
possibility of unnecessarily high voltages being supplied to the
internal circuit 30 is reduced. Conversely, because the resistance
value SR decreases as the external power supply voltage VDD
decreases, an adequate voltage can be maintained as the internal
power supply voltage VCC even when the external power supply
voltage VDD decreases.
[0079] FIG. 3B is a schematic diagram showing a variation in the
internal power supply voltage VCC output from the variable resistor
circuit 20a. In FIG. 3B, the variation in the internal power supply
voltage VCC with the variation in the external power supply voltage
VDD under the same conditions as in FIG. 3A is shown.
[0080] As can be understood by comparing FIGS. 3A and 3B, when the
external power supply voltage VDD is equal to the reference voltage
VREF1, the internal power supply voltage VCC becomes equal to the
output voltage VPR (equal to VPR1 or VCC1). This is compliant with
the mode of the variable resistor circuit 20a being the first mode
M1, and the resistance value SR between the node f and the output
node b being substantially zero. When the external power supply
voltage VDD increases to a value between the voltages V.sub.a and
V.sub.b, the potential at the node f increases to VPR2, but the
internal power supply voltage VCC at the output node b decreases as
compared with VPR2. This is compliant with the mode of the variable
resistor circuit 20a changing to the second mode M2, and the
resistance value SR between the node f and the output node b
becoming substantially equal to the resistance value R.sub.1. That
is, the decrease in the voltage occurs by the resistance value
R.sub.1. Specifically, the potential at the output node b is less
than the potential at the node f by R.sub.1.times.I.sub.L. The
potential at the output node b can be made equal to VCC1 by
selecting an appropriate resistance value R.sub.1.
[0081] As described above, in the semiconductor device 1a according
to the first embodiment, when the external power supply voltage VDD
increases, the resistance value SR increases, and therefore the
possibility of unnecessarily high voltages being supplied to the
internal circuit 30 reduces. On the other hand, when the external
power supply voltage VDD drops, the resistance value SR reduces,
and an adequate voltage can be maintained as the internal power
supply voltage VCC. Furthermore, because an increase in the
internal power supply voltage VCC with an increase in the external
power supply voltage VDD is prevented, current consumption by the
internal circuit 30 can be reduced.
[0082] FIG. 7 is a schematic functional block diagram of a
semiconductor device 1b according to a second embodiment of the
present invention.
[0083] As shown in FIG. 7, the semiconductor device 1b according to
the second embodiment differs from the semiconductor device 1a
according to the first embodiment in that it includes a boosting
circuit 10b, a variable resistor circuit 20b, and an external
voltage-level comparison circuit 21b instead of the boosting
circuit 10a, the variable resistor circuit 20a, and the external
voltage-level comparison circuit 21a. Moreover, a voltage at the
output node b in the second embodiment is called an internal power
supply voltage VPP. The parts of the second embodiment that are
different from the first embodiment are mainly explained below.
[0084] The boosting circuit 10b differs from the boosting circuit
10a in that it includes an OSC circuit 11b instead of the OSC
circuit 11a, and in addition, also includes an OSC control circuit
13. The boosting circuit 10b stops a boosting operation when the
internal power supply voltage VPP exceeds a predetermined standard
value VPPM due to operations of the OSC control circuit 13 and the
OSC circuit 11b. As a result, even when the power consumption by
the internal circuit 30 is low, the output voltage VPR is prevented
from continuing to increase.
[0085] However, a certain amount of delay occurs from the time the
internal power supply voltage VPP exceeds the standard value VPPM
to the time the boosting operation is stopped by the charge pump
circuit 12. The occurrence of delay itself is unavoidable due to
the configuration of the boosting circuit 10b, and thus there is a
possibility that the internal power supply voltage VPP may become
too high during the delay period. The variable resistor circuit 20b
according to the second embodiment is provided with an object of
preventing the internal power supply voltage VPP from increasing
excessively due to the delay. Each of the circuits is explained
below in detail.
[0086] FIG. 8 shows circuit configurations of the OSC circuit 11b
and the OSC control circuit 13.
[0087] The OSC control circuit 13 includes resistor elements
R.sub.X and R.sub.Y, and a comparator 90. The resistor elements
R.sub.X and R.sub.Y are connected in series between the output node
b (internal power supply voltage VPP) and the ground potential. A
non-inverting input terminal of the comparator 90 is connected to a
connection point of the resistor elements R.sub.X and R.sub.Y. Due
to this configuration, a divided voltage
VPP.times.R.sub.Y/(R.sub.X+R.sub.Y) of the internal power supply
voltage VPP is input into the non-inverting input terminal of the
comparator 90. A reference voltage VREF2 that has a predetermined
voltage value is input from a not shown constant voltage source
into an inverting input terminal of the comparator 90.
[0088] The comparator 90 is a circuit that compares the divided
voltage VPP.times.R.sub.Y/(R.sub.X+R.sub.Y) of the internal power
supply voltage VPP and the reference voltage VREF2. When the
divided voltage VPP.times.R.sub.Y/(R.sub.X+R.sub.Y) of the internal
power supply voltage VPP is higher than the reference voltage
VREF2, an output of the comparator 90 is at a high level, otherwise
the output of the comparator is at a low level. The comparator
P.sub.1 shown in FIG. 5A can be used to represent a circuit
configuration of the comparator 90.
[0089] Assuming a voltage value of the reference voltage VREF2 to
be VPPM.times.R.sub.Y/(R.sub.X+R.sub.Y), the comparison result of
the internal power supply voltage VPP and the standard value VPPM
are reflected in the output of the comparator 90.
[0090] Next, the OSC circuit 11b has a configuration similar to
that of the OSC circuit 11a of FIG. 2A, except that the delay line
55a is replaced with a delay line 55b. The delay line 55b has an
odd number of inverters (five in FIG. 8) as does the delay line
55a, but differs from the delay line 55a in that it has a NAND
circuit 91 between a first level inverter and a second level
inverter.
[0091] An output of the first level inverter and an output of the
delay line 55b are input into the NAND circuit 91. Thus, when the
output of the first level inverter is at a high level, the delay
line 55b functions similar to the delay line 55a and repeatedly
outputs high level signals and low level signals. As a result, the
output of the OSC circuit 11b will be complementary clock signals
.PHI. and /.PHI. as shown in FIG. 2B. On the other hand, when the
output of the first level inverter is at a low level, the output of
the NAND circuit 91 is always at a low level. Consequently, the
output of the delay line 55b will also always be at a low level,
and the outputs of the buffer 56 and the inverter 57 will always be
at a low level and a high level, respectively. That is, the OSC
circuit 11b stops the output of the complementary clock signals
.PHI. and /.PHI..
[0092] The output of the comparator 90 is input into the first
level inverter. Thus, when the internal power supply voltage VPP is
higher than the standard value VPPM, a high level signal is input
into the first level inverter, and the OSC circuit 11b stops the
output of the complementary clock signals .PHI. and /.PHI.. In this
case, the charge pump circuit 12 stops the boosting operation, and
the internal power supply voltage VPP decreases with power
consumption by the internal circuit 30 or the like. On the other
hand, when the internal power supply voltage VPP is lower than the
standard value VPPM, a low level signal is input into the first
level inverter, and the output of the OSC circuit 11b will be the
complementary clock signals .PHI. and /.PHI. as shown in FIG. 2B.
In this case, the charge pump circuit 12 performs the boosting
operation as explained in the first embodiment.
[0093] FIG. 9 shows circuit configurations of the variable resistor
circuit 20b and the external voltage-level comparison circuit
21b.
[0094] As shown in FIG. 9, the variable resistor circuit 20b
includes resistor elements R.sub.1 to R.sub.6 and R.sub.S and
switch elements SW.sub.1 to SW.sub.6. The resistor elements R.sub.1
to R.sub.6 are connected in parallel between the node f and the
output node b, and the resistor element R.sub.S is inserted between
the resistor elements R.sub.1 to R.sub.6 and the node f. The switch
elements SW.sub.1 to SW.sub.5 are connected in series,
respectively, to the resistor elements R.sub.1 to R.sub.5, and the
switch element SW.sub.6 is connected in parallel to the resistor
element R.sub.S. The external voltage-level comparison circuit 21b
includes a voltage dividing circuit 60b that includes six resistor
elements R.sub.A to R.sub.F connected in series between the
external power supply voltage VDD and the ground potential, and a
comparison circuit 61b that includes five comparators P.sub.1 to
P.sub.5.
[0095] The external voltage-level comparison circuit 21b differs
from the external voltage-level comparison circuit 21a in that it
divides the external power supply voltage VDD five ways (into
divided voltages V.sub.1 to V.sub.5) with the six resistor elements
R.sub.A to R.sub.F, and outputs five comparison result signals
(comparison result signals ON.sub.1 to ON.sub.5) corresponding to
the divided voltages V.sub.1 to V.sub.5. The external voltage-level
comparison circuit 21b is similar to the external voltage-level
comparison circuit 21a in other respects and therefore explanations
thereof will be omitted.
[0096] The comparison result signals ON.sub.1 to ON.sub.5 are input
into the switch elements SW.sub.1 to SW.sub.5, respectively, in the
variable resistor circuit 20b. The switch elements SW.sub.1 to
SW.sub.5 are turned on when the comparison result signal being
input is active and turned off when it is not active. The switch
element SW.sub.6, on the other hand, is turned off when a load
current flowing in the output node b is lower than a predetermined
value, and turned on otherwise. When the load current is lower than
the predetermined value, it indicates that the internal circuit 30
is in a standby mode. That is, the switch element SW.sub.6 is
turned off when the internal circuit 30 is in the standby mode, and
turned on during a normal operation. The specific configurations of
each of the switch elements SW.sub.1 to SW.sub.6 are similar to
those explained in the first embodiment with reference to FIG.
5B.
[0097] FIG. 10A is a graph showing a relation between the external
power supply voltage VDD and output voltages V.sub.DIV of the
voltage dividing circuit 60b (divided voltages V.sub.1 to V.sub.5).
The vertical axis and the horizontal axis are the same as in FIG.
6A. As shown in FIG. 10A, when each of the divided voltages V.sub.1
to V.sub.5 is equal to the reference voltage VREF1, the external
power supply voltage VDD is equal to voltages V.sub.a to V.sub.e
(V.sub.a<V.sub.b<V.sub.c<V.sub.d<V.sub.e). As in the
first embodiment, the activation status of the comparison result
signals ON.sub.1 to ON.sub.5 of the variable resistor circuit 20b
changes with the voltages V.sub.a to V.sub.e as threshold values in
the second embodiment. A combination of the activation statuses of
the comparison result signals ON.sub.1 to ON.sub.5 corresponding to
the external power supply voltage VDD in an ascending order thereof
is hereinafter referred to as first mode M1 to sixth mode M6.
[0098] FIG. 10B is a graph showing a relation between the first to
sixth modes M1 to M6 and the resistance values SR that are realized
between the node f and the output node b due to the on/off status
of the switch elements SW.sub.1 to SW.sub.5. The vertical axis and
the horizontal axis are the same as in FIG. 6B.
[0099] The graphs G1 and G2 of FIG. 10B represent the instances
when the switch element SW.sub.6 is on (the internal circuit 30 is
in a normal operation) and off (the internal circuit 30 is in the
standby mode). The resistance values SR in the various modes shown
in FIG. 10B are shown in Table 1 given below. In Table 1, the
symbol // is an operator that determines a combined resistance of
the resistors connected in parallel. For example, the combined
resistance of the resistors X and Y connected in parallel becomes:
X//Y=1/(1/X+1/Y).
TABLE-US-00001 TABLE 1 Resistance value SR Resistance value SR
(when switch element SW.sub.6 (when switch element SW.sub.6 Mode is
on) is off) M1 R.sub.6//R.sub.5//R.sub.4//R.sub.3//R.sub.2//R.sub.1
R.sub.6//R.sub.5//R.sub.4//R.sub.3//R.sub.2//R.sub.1 + R.sub.S M2
R.sub.6//R.sub.5//R.sub.4//R.sub.3//R.sub.2
R.sub.6//R.sub.5//R.sub.4//R.sub.3//R.sub.2 + R.sub.S M3
R.sub.6//R.sub.5//R.sub.4//R.sub.3
R.sub.6//R.sub.5//R.sub.4//R.sub.3 + R.sub.S M4
R.sub.6//R.sub.5//R.sub.4 R.sub.6//R.sub.5//R.sub.4 + R.sub.S M5
R.sub.6//R.sub.5 R.sub.6//R.sub.5 + R.sub.S M6 R.sub.6 R.sub.6 +
R.sub.S
[0100] In this manner, also in the second embodiment, the
resistance value SR between the node f and the output node b varies
according to the mode of the variable resistor circuit 20b.
Furthermore, because the resistance value SR increases as the
external power supply voltage VDD increases, the value of the
internal power supply voltage VPP can be decreased as the external
power supply voltage VDD increases. As a result, the possibility of
unnecessarily high voltages being supplied to the internal circuit
30 is reduced. Conversely, because the resistance value SR
decreases as the external power supply voltage VDD decreases, an
adequate voltage can be maintained as the internal power supply
voltage VPP even when the external power supply voltage VDD
decreases.
[0101] The resistance value SR also varies according to an
operation status of the internal circuit 30. This reflects that in
the standby mode, the power consumption by the internal circuit 30
becomes less, and thus the internal power supply voltage VPP can
easily increase. Therefore, in the standby mode, the resistance
value SR increases so that the possibility of unnecessarily high
voltages being supplied to the internal circuit 30 is reduced.
Conversely, because the resistance value SR during a normal
operation is low, an adequate internal power supply voltage VPP can
be maintained during a normal operation.
[0102] FIGS. 11A to 11C show an outline of the variation of the
internal power supply voltage VPP output by the variable resistor
circuit 20b. In FIGS. 11A to 11C, the delay period from the time
the internal power supply voltage VPP exceeds the standard value
VPPM to the time the boosting operation is stopped by the charge
pump circuit 12 is set to 3 clocks. In each of the FIGS. 11A to
11C, VPP.sub.MAXn (where n is an integer from 1 to 7) denotes a
maximum value of the internal power supply voltage VPP in the delay
period.
[0103] A voltage VPP.sub.1 of FIG. 11A is the internal power supply
voltage VPP when the external power supply voltage VDD satisfies
the magnitude relation V.sub.b<VDD<V.sub.c and the internal
circuit 30 is in a normal operation. In this case, the mode of the
variable resistor circuit 20b becomes the third mode M3.
[0104] A voltage VPP.sub.2 is also shown in FIG. 11A for the
purpose of comparison. The voltage VPP.sub.2 is the internal power
supply voltage VPP when the mode of the variable resistor circuit
20b is the first mode M1 and the other conditions are similar to
those for the voltage VPP.sub.1. As is understood from comparing
the voltages VPP.sub.1 and VPP.sub.2, slopes of the voltages
VPP.sub.1 and VPP.sub.2 during the rise are different.
Specifically, the rising range of the voltage VPP.sub.1 is lower
than the rising range of the voltage VPP.sub.2 per clock cycle. As
a result, the maximum value VPP.sub.MAX1 of the voltage VPP.sub.1
is lower than a maximum value VPP.sub.MAX2 of the voltage
VPP.sub.2. That is, an excessive increase in the internal power
supply voltage VPP due to the delay is suppressed with the variable
resistor circuit 20b according to the second embodiment.
[0105] A voltage VPP.sub.3 of FIG. 11B is the internal power supply
voltage VPP when the external power supply voltage VDD satisfies
the magnitude relation V.sub.e<VDD and the internal circuit 30
is in a normal operation. In this case, the mode of the variable
resistor circuit 20b becomes the sixth mode M6.
[0106] A voltage VPP.sub.4 is also shown in FIG. 11B for the
purpose of comparison. The voltage VPP.sub.4 is the internal power
supply voltage VPP when the mode of the variable resistor circuit
20b is the first mode M1 and the other conditions are similar to
those for the voltage VPP.sub.3. As is understood from comparing
the voltage VPP.sub.4 with the voltage VPP.sub.2 of FIG. 11A,
maximum value VPP.sub.MAX4 of the voltage VPP.sub.4 is higher than
the maximum value VPP.sub.MAX2 of the voltage VPP.sub.2. This is
due to a higher external power supply voltage VDD. However, in
spite of a higher external power supply voltage VDD, a maximum
value VPP.sub.MAX3 of the voltage VPP.sub.3 is suppressed to the
same extent as the maximum value VPP.sub.MAX1 of the voltage
VPP.sub.1. Thus, with the variable resistor circuit 20b according
to the second embodiment, an excessive increase in the internal
power supply voltage VPP due to the delay can be appropriately
suppressed even if the external power supply voltage VDD varies
significantly.
[0107] A voltage VPP.sub.5 of FIG. 11C is the internal power supply
voltage VPP when the external power supply voltage VDD satisfies
the magnitude relation V.sub.b<VDD<V.sub.c, and the internal
circuit 30 is in the standby mode. In this case, the mode of the
variable resistor circuit 20b becomes the third mode M3. In
addition, the switch element SW.sub.6 is turned off. A slope of the
voltage VPP.sub.5 during the fall has a gentle gradient compared to
that of the voltage VPP.sub.1 of FIG. 11A. The gentle gradient of
the slope indicates that the internal circuit 30 is in the standby
mode and that its power consumption is low.
[0108] A voltage VPP.sub.6 is also shown in FIG. 11C for the
purpose of comparison. The voltage VPP.sub.6 is the internal power
supply voltage VPP when the switch element SW.sub.6 is turned on
and the other conditions are similar to those for the voltage
VPP.sub.5. Furthermore, a voltage VPP.sub.7 is also shown in FIG.
11C. The voltage VPP.sub.7 is the internal power supply voltage VPP
when the mode of the variable resistor circuit 20b is the first
mode M1 and the other conditions are similar to those for the
voltage VPP.sub.6.
[0109] The voltages VPP.sub.6 and VPP.sub.7 are equivalent to the
voltages VPP.sub.1 and VPP.sub.2 of FIG. 11A when the internal
circuit 30 is in the standby mode. As is understood from comparing
FIGS. 11A and 11C, a maximum value VPP.sub.MAX6 of the voltage
VPP.sub.6 and a maximum value VPP.sub.MAX7 of the voltage VPP.sub.7
are higher than the maximum value VPP.sub.MAX1 of the voltage
VPP.sub.1 and the maximum value VPP.sub.MAX2 of the voltage
VPP.sub.2, respectively. This is because the power consumption by
the internal circuit 30 is less than that for the example of the
voltage VPP.sub.2. Thus, an excessive increase in the internal
power supply voltage VPP cannot be adequately suppressed by
changing the mode of the variable resistor circuit 20b to the third
mode M3 alone. However, as shown in the example of the voltage
VPP.sub.5, an excessive increase in the internal power supply
voltage VPP can be adequately suppressed by turning off the switch
element SW.sub.6. Thus, when the internal circuit 30 is in the
standby mode, an excessive increase in the internal power supply
voltage VPP due to the delay can be suppressed by switching the
modes of the variable resistor circuit 20b according to the
external power supply voltage VDD along with turning off the switch
element SW.sub.6.
[0110] Thus, in the semiconductor device 1b according to the second
embodiment, the possibility of unnecessarily high voltages being
supplied to the internal circuit 30 in the period from the time the
internal power supply voltage VPP exceeds the standard value VPPM
to the time the boosting operation is stopped by the charge pump
circuit 12 is reduced. Furthermore, because the resistance value SR
is optimized according to the external power supply voltage VDD, an
adequate voltage can be maintained as the internal power supply
voltage VPP. In addition, power consumption by a variable resistor
in the variable resistor circuit 20b can be reduced. Moreover, even
when the internal circuit 30 is in the standby mode, the
possibility of unnecessarily high voltages being supplied to the
internal circuit 30 can be reduced.
[0111] It is apparent that the present invention is not limited to
the above embodiments, but may be modified and changed without
departing from the scope and spirit of the invention.
[0112] For example, in the first and second embodiments, the
numbers of modes of the variable resistor circuit are four and six,
respectively. However, the numbers of modes need not be limited to
these. For example, in the first embodiment, if n-1 (where n is
equal to or larger than 2) resistor elements are connected in
series in the variable resistor circuit 20a, n resistor elements
are used in the voltage dividing circuit 60a, and n-1 comparators
are used in the comparison circuit 61a, n modes can be obtained.
Similarly, in the second embodiment, if n resistor elements are
connected in parallel in the variable resistor circuit 20b, n
resistor elements are used in the voltage dividing circuit 60b, and
n-1 comparators are used in the comparison circuit 61a, n modes can
be obtained.
[0113] Moreover, the first embodiment can be configured with the
resistor element R.sub.S and the switch element SW.sub.6 used in
the second embodiment, and enabling variation in the resistance
value of the variable resistor according to the power consumption
by the internal circuit.
[0114] The resistor elements R.sub.1 to R.sub.3 in the variable
resistor circuit 20a are connected in series in the first
embodiment and the resistor elements R.sub.1 to R.sub.6 in the
variable resistor circuit 20b are connected in parallel in the
second embodiment. However, these are merely examples, and the
resistor elements R.sub.1 to R.sub.3 in the variable resistor
circuit 20a in the first embodiment can be connected in parallel,
and the resistor elements R.sub.1 to R.sub.6 in the variable
resistor circuit 20b in the second embodiment can be connected in
series.
[0115] Specific circuit configurations of respective circuits
described in the above embodiments are not limited to those
explained above, and various other circuit configurations can be
also employed as far as they have functions similar to those of the
circuit configurations explained above.
* * * * *