loadpatents
name:-0.037049055099487
name:-0.020771026611328
name:-0.0017399787902832
Kubouchi; Shuichi Patent Filings

Kubouchi; Shuichi

Patent Applications and Registrations

Patent applications and USPTO patent grants for Kubouchi; Shuichi.The latest application filed is for "semiconductor device having roll call circuit".

Company Profile
0.18.19
  • Kubouchi; Shuichi - Tokyo N/A JP
  • Kubouchi; Shuichi - Fussa JP
  • Kubouchi, Shuichi - Fussa-shi JP
*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.
Patent Activity
PatentDate
Semiconductor device having electrical fuse and control method thereof
Grant 9,543,037 - Kubouchi , et al. January 10, 2
2017-01-10
Semiconductor device having roll call circuit
Grant 9,230,686 - Kubouchi , et al. January 5, 2
2016-01-05
Semiconductor Device Having Roll Call Circuit
App 20140286113 - KUBOUCHI; SHUICHI ;   et al.
2014-09-25
Semiconductor Device Having Boosting Circuit
App 20140111271 - FUJISAWA; Hiroki ;   et al.
2014-04-24
Semiconductor device having nonvolatile memory elements
Grant 8,699,256 - Kubouchi , et al. April 15, 2
2014-04-15
Semiconductor device having boosting circuit
Grant 8,633,758 - Fujisawa , et al. January 21, 2
2014-01-21
Semiconductor device, relief-address-information writing device, and relief-address-information writing method
Grant 8,270,237 - Kubouchi September 18, 2
2012-09-18
Semiconductor Device Having Electrical Fuse And Control Method Thereof
App 20120120750 - KUBOUCHI; Shuichi ;   et al.
2012-05-17
Semiconductor Device Having Electrical Fuse And Control Method Thereof
App 20120120735 - KUBOUCHI; Shuichi ;   et al.
2012-05-17
Semiconductor device having boosting circuit
App 20110221513 - Fujisawa; Hiroki ;   et al.
2011-09-15
Semiconductor memory device and test method thereof
Grant 7,940,587 - Kubouchi , et al. May 10, 2
2011-05-10
Semiconductor memory device, control method therefor, and method for determining repair possibility of defective address
Grant 7,940,583 - Riho , et al. May 10, 2
2011-05-10
Sense Amplifier Circuit To Enable Speeding-up Of Readout Of Information From Memory Cells
App 20110096616 - KUBOUCHI; Shuichi ;   et al.
2011-04-28
Semiconductor device, relief-address-information writing device, and relief-address-information writing method
App 20110063933 - Kubouchi; Shuichi
2011-03-17
Semiconductor device having nonvolatile memory elements
App 20110058402 - Kubouchi; Shuichi ;   et al.
2011-03-10
Semiconductor memory device having sense amplifier
App 20100103758 - Riho; Yoshiro ;   et al.
2010-04-29
Semiconductor Memory Device And Test Method Thereof
App 20090268534 - Kubouchi; Shuichi ;   et al.
2009-10-29
Synchronous semiconductor memory device
Grant 7,580,321 - Fujisawa , et al. August 25, 2
2009-08-25
Semiconductor memory device, control method therefor, and method for determining repair possibility of defective address
App 20090201753 - Riho; Yoshiro ;   et al.
2009-08-13
Synchronous semiconductor memory device
App 20080165611 - Fujisawa; Hiroki ;   et al.
2008-07-10
Synchronous semiconductor memory device
Grant 7,345,950 - Fujisawa , et al. March 18, 2
2008-03-18
Command control circuit
App 20080040567 - Kuroki; Koji ;   et al.
2008-02-14
Synchronous semiconductor memory device
App 20070091714 - Fujisawa; Hiroki ;   et al.
2007-04-26
Semiconductor integrated circuit device
Grant 7,085,192 - Fujisawa , et al. August 1, 2
2006-08-01
Boosted potential generation circuit and control method
Grant 6,954,386 - Narui , et al. October 11, 2
2005-10-11
Semiconductor memory device having a hierarchical I/O structure
Grant 6,934,214 - Fujisawa , et al. August 23, 2
2005-08-23
Semiconductor integrated circuit device
App 20050122795 - Fujisawa, Hiroki ;   et al.
2005-06-09
Semiconductor memory device having a hierarchical I/O structure
App 20040228176 - Fujisawa, Hiroki ;   et al.
2004-11-18
Semiconductor memory device having a hierarchical I/O structure
Grant 6,765,844 - Fujisawa , et al. July 20, 2
2004-07-20
Semiconductor memory device having a hierarchical I/O structure
App 20040047229 - Fujisawa, Hiroki ;   et al.
2004-03-11
Semiconductor memory device having a hierarchial I/O strucuture
Grant 6,665,203 - Fujisawa , et al. December 16, 2
2003-12-16
Boosted potential generation circuit and control method
App 20030202390 - Narui, Seiji ;   et al.
2003-10-30
Semiconductor memory device
App 20020001215 - Fujisawa, Hiroki ;   et al.
2002-01-03
Dynamic memory
Grant 5,905,685 - Nakamura , et al. May 18, 1
1999-05-18

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