U.S. patent application number 13/630996 was filed with the patent office on 2014-04-03 for method and apparatus to improve reliability of vias.
The applicant listed for this patent is DOUGLAS M. REBER. Invention is credited to DOUGLAS M. REBER.
Application Number | 20140091475 13/630996 |
Document ID | / |
Family ID | 50384418 |
Filed Date | 2014-04-03 |
United States Patent
Application |
20140091475 |
Kind Code |
A1 |
REBER; DOUGLAS M. |
April 3, 2014 |
METHOD AND APPARATUS TO IMPROVE RELIABILITY OF VIAS
Abstract
A semiconductor device comprising a first insulating layer, a
first metal conductor layer formed over the first insulating layer,
a second insulating layer comprising a low-k insulating material
formed over the first metal conductor, a second metal conductor
layer formed over the second insulating layer, vias formed in the
second insulating layer connecting the first metal conductor layer
to the second metal conductor layer, and a plurality of metal
lines. One of the metal lines is expanded around one of the vias
compared to metal lines around other ones of the vias so that
predetermined areas around each of the vias meets a minimum metal
density.
Inventors: |
REBER; DOUGLAS M.; (Austin,
TX) |
|
Applicant: |
Name |
City |
State |
Country |
Type |
REBER; DOUGLAS M. |
Austin |
TX |
US |
|
|
Family ID: |
50384418 |
Appl. No.: |
13/630996 |
Filed: |
September 28, 2012 |
Current U.S.
Class: |
257/774 ;
257/E23.011; 716/126 |
Current CPC
Class: |
G06F 2117/06 20200101;
H01L 2924/0002 20130101; H01L 2924/0002 20130101; H01L 2924/0002
20130101; H01L 21/76814 20130101; H01L 2924/0001 20130101; H01L
2924/00 20130101; G06F 30/39 20200101; H01L 23/528 20130101 |
Class at
Publication: |
257/774 ;
716/126; 257/E23.011 |
International
Class: |
G06F 17/50 20060101
G06F017/50; H01L 23/48 20060101 H01L023/48 |
Claims
1. A method for expanding metal lines for selected vias in a
semiconductor device having a plurality of vias, the method
comprising: generating a layout database for the semiconductor
device; creating zones around the plurality of vias by upsizinq the
plurality of vias; measuring density of covering metal in each
zone; selecting a low density zone as being a zone that has a metal
density less than a threshold metal density; and expanding at least
one metal line on a metal layer above the plurality of vias in the
low density zone so that metal density of the low density zone
increases to at least the same as the threshold metal density, the
at least one metal line is connected to at least one of the
plurality of vias.
2. (canceled)
3. The method of claim 1, wherein expanding the at least one metal
line on the metal layer, further comprises the metal layer being an
inlaid metal layer.
4. The method of claim 1, wherein the creating zones comprises
upsizing the vias a predetermined amount based on an original size
of the vias.
5. The method of claim 1, wherein creating zones comprises defining
the zones to have a dimension no larger than an order of magnitude
of twice a minimum metal feature size for the semiconductor
device.
6. The method of claim 1, wherein expanding the at least one metal
line further comprises expanding the at least one metal line to
obtain a metal coverage of no less than 30 percent of surface area
within the zone.
7. The method of claim 1, wherein the method is performed for
interlevel dielectric layers of the semiconductor device comprising
a low-k oxide.
8. The method of claim 1, wherein creating the zones around the
vias further comprises upsizing the vias by 0.9 micron per
side.
9. A method for increasing metal density for selected vias in a
semiconductor device having a plurality of vias, the method
comprising: generating a layout database for the semiconductor
device; creating a plurality of zones by upsizing the plurality of
vias; selecting zones of the plurality of zones that include at
least one metal line and have less than a threshold metal density
as being low density zones; and expanding the at least one metal
line in each of the low density zones.
10. The method of claim 9 wherein creating the plurality of zones
further comprises defining the zones as being no larger than an
order of magnitude of twice the minimum metal feature size for the
semiconductor device.
11. The method of claim 9, wherein expanding a metal layer within a
space enclosed by each of the low density zones achieves a target
metal density of at least 10 percent within the space.
12. The method of claim 9, wherein creating the plurality of zones
further comprises sizing the zones to be no greater than twelve
times a minimum pitch between metal lines for the semiconductor
device.
13. The method of claim 9, wherein expanding the at least one metal
line further comprises expanding the at least one metal line to
obtain a metal coverage of no less than five percent of surface
area within the low density zones.
14. The method of claim 9, wherein the method is performed for
interlevel dielectric layers of the semiconductor device comprising
a low-k oxide.
15-20. (canceled)
Description
BACKGROUND
[0001] 1. Field
[0002] This disclosure relates generally to semiconductor
processing, and more particularly, to improving reliability of
vias.
[0003] 2. Related Art
[0004] Integrated circuits are formed with metal layers stacked on
top of one another and dielectric layers between the metal layers
to insulate the metal layers from each other. Normally, each metal
layer has an electrical contact to at least one other metal layer.
Electrical contact can be formed by etching a hole (i.e., a via) in
the interlayer dielectric that separates the metal layers, and
filling the resulting via with a metal to create an interconnect. A
"via" normally refers to any recessed feature such as a hole, line
or other similar feature formed within a dielectric layer that,
when filled with a conductive material, provides an electrical
connection through the dielectric layer to a conductive layer
underlying the dielectric layer.
[0005] With the number of transistors that are now present on
integrated circuits, the number of vias can exceed a billion and
there can be ten or more different conductive layers. Even if each
via is highly reliable, there are so many vias that it is likely
for there to be at least one via failure. Low-k BEOL (Back-End of
Line) interlayer dielectrics commonly used in advanced technology
integrated circuit manufacturing can have trapped moisture and
hydroxyl ions. These trapped water species pose a risk of oxidizing
via barrier material if not sufficiently out-gassed. Vias with
oxidized tantalum barriers exhibit excessive via resistance that
has been shown to cause timing delays in semiconductor devices. A
barrier material is used to contain the migration of a copper used
for a metal layer through the insulating material.
[0006] Barrier materials typically used today are a combination of
tantalum and tantalum nitride, or just tantalum. Tantalum nitride
has good adhesion properties to the oxide dielectric. However,
other materials can be used. One problem which is specifically
worse for tantalum is that tantalum oxidizes to form tantalum
pentoxide and expands to a volume which is several times larger
than just the tantalum. Also, the tantalum pentoxide is an
insulator and has very high resistance.
[0007] Accordingly, it is desirable to provide a technique for
improving the reliability of vias and uniformity of via
resistance.
BRIEF DESCRIPTION OF THE DRAWINGS
[0008] The present disclosure is illustrated by way of example and
is not limited by the accompanying figures, in which like
references indicate similar elements. Elements in the figures are
illustrated for simplicity and clarity and have not necessarily
been drawn to scale.
[0009] FIG. 1 is a flow diagram of an embodiment of a process for
determining where to add metal tiles around one or more vias to
improve reliability of a semiconductor device.
[0010] FIG. 2 is a top view of an embodiment of a partial layout of
a semiconductor device during a first stage of design.
[0011] FIG. 3 is a top view of the semiconductor device of FIG. 2
during a subsequent stage of design.
[0012] FIG. 4 is a top view of the semiconductor device of FIG. 3
during a subsequent stage of design.
[0013] FIG. 5 is a top view of the semiconductor device of FIG. 4
during a subsequent stage of design.
[0014] FIG. 6 is a top view of an embodiment of a semiconductor
device.
[0015] FIG. 7 is a cross-section view of the semiconductor device
of FIG. 6.
DETAILED DESCRIPTION
[0016] Embodiments of methods and semiconductor devices are
disclosed herein that improve reliability of vias and/or improve
uniformity of via resistance by expanding and/or adding metal
around the isolated vias to improve moisture dissipation during
out-gassing processes. In one embodiment, vias located in zones
which have a covering metal density of less than a predetermined
density are identified, and metal features are expanded around
these identified vias. This is better understood by reference to
the following description and the drawings.
[0017] FIG. 1 is a flow diagram of an embodiment of process 100 for
determining where to expand metal around one or more vias to
improve reliability of a semiconductor device or integrated
circuit. Process 102 includes generating a layout database for the
semiconductor device that includes the type, size, location and
interconnections between features or components such as metal
layers, dielectric layers, and vias connecting the conductive
layers in the semiconductor device. Any suitable type of integrated
circuit design tool can be used in process 102. One example of a
commercially available tool that can be used is the IC Station
design system by Mentor Graphics, Inc. of Wilsonville, Oreg. An
additional tool called Calibre by Mentor Graphics can be used to
manipulate a database for an IC designed using IC Station.
[0018] With reference with FIGS. 1 and 2, FIG. 2 is a top view of
an embodiment of a partial layout of semiconductor device 200 at a
first stage of design. Semiconductor device 200 includes a
plurality of vias 202a, 202b, 202c, 202d, 202e (collectively, "vias
202"), and metal lines 204 coupled to the vias 202. Metal lines 204
may be referred to as covering metal because they are located over
vias 202. That is, vias 202 are coupled between covering metal,
such as metal lines 204, and landing metal, located below vias 202.
Note that the covering metal may correspond to the last metal layer
of semiconductor device 200. Using the database generated in
process 102, process 104 includes creating or determining zones
206a, 206b, 206c (collectively, "zones 206") around vias 202 within
a predetermined distance around vias 202. Note that there may be a
plurality of isolated vias 202c in semiconductor device 200.
[0019] In the example shown, zone 206a is a polygon shape around
vias 202a, 202b; zone 206b is a polygon shape around via 202c; and
zone 206c is a polygon around vias 202d, 202e. Although zones 206
are shown as polygons, zones 206 can be any suitable shape.
[0020] Vias 202 are typically created with approximately the same
shape, shown as a square in FIG. 2. In some implementations, zones
206 can be determined by upsizing the original size of vias 202 by
a suitable distance. The particular upsize distance to determine
zones 206 can be based on the size of the components of the
semiconductor device 200. Semiconductor processing technology is
often referred to based on the drawn transistor minimum gate
length. For example, the term 90 nm technology refers to a silicon
technology with a drawn transistor minimum gate length of 90-100
nm. As a further example, vias 202 in a 90 mm technology
semiconductor device 200 can be 0.13 micron per side and the upsize
distance can be 0.9 micron per side to form polygons that are 1.93
microns per side. Other suitable via sizes and shapes, and upsize
distances for forming zones 206 can be used. Other techniques for
creating zones 206 around vias 202 can also be used instead of
temporarily upsizing vias 206.
[0021] Zones 206 that overlap or touch one another can be combined
into one zone. For example, larger zones 206a, 206c were formed by
combining individual zones (not shown) around respective vias
202a/202b and 202d/202e because the individual zones around vias
202a/202b and 202d/202e overlapped or touched one another.
[0022] Process 106 includes measuring or determining the density of
covering metal in each zone 206. For example, for zone 206a, the
portion of metal line 204 within zone 206a is used to determine the
covering metal density. For zone 206b, the portion of metal line
204 within zone 206b is used to determine the covering metal
density. For zone 206c, the portions of metal lines 204 within zone
206c is used to determine the covering metal density. Zones that
have metal density greater than or equal to a predetermined
threshold density are discarded, while zones that have metal
density less than the predetermined threshold density are
candidates for increased metal density. In one embodiment, the
predetermined density threshold may be 80%, such that any zone 202
having a density less than 80% is selected. Alternatively, the
predetermined density threshold may be 70%, 60%, 50%, 40%, 30%,
20%, 15%, 10%, or 5%. In the embodiments herein, it will be assumed
that the predetermined density threshold is 30% such that any zone
202 having a density of covering metal less than 30% is selected by
process 108.
[0023] Referring back to FIG. 1, process 108 includes selecting
zones which have a density less than the predetermined density
threshold. Referring to FIG. 3, a top view of semiconductor device
200 of FIG. 2 is shown after a subsequent stage of design including
process 108, in which zone 206b is selected. In the illustrated
example, zone 206b has a covering metal density of less than 30%
while each of zones 206a and 206b have a covering metal density of
greater than 30%. Process 108 can also include showing selected and
unselected vias 202 to the user of the design system via display
device. In one embodiment, process 108 may highlight those zones
which are selected. Selection of zone 206b can be performed in
logic instructions executed by a computer processor and therefore
may not otherwise be visible to a user. Process 108 can also
interactively allow a user to select and deselect vias manually,
however, given the large number of vias that may be included in a
semiconductor device, manual selection is generally not
performed.
[0024] Referring to FIGS. 1 and 4, FIG. 4 is a top view of
semiconductor device 200 of FIG. 3 after a subsequent stage of
design including process 110 in which zone 402 is created around
via 202c selected in process 108. In some implementations, selected
via 202c can be temporarily upsized based on the original via size
to form zone 402. For example, in a 90 mm technology, a rectangular
via 202c that is 0.13 microns per side can be upsized by 0.9
microns per side to form zone 402 that is 1.93 microns per
side.
[0025] Alternatively, zones 402 around each of selected isolated
vias 202 can be defined to have a dimension no larger than an order
of magnitude of a minimum metal feature size for the semiconductor
device. In the semiconductor industry, the term minimum metal
feature size refers to the smallest feature size allowed to be used
by a designer.
[0026] Other suitable via sizes and shapes, and upsize distances
for forming zone 402 in process 110 can be used. Additionally,
other techniques for creating zones 402 around selected vias 202c
can also be used instead of temporarily upsizing vias 206.
[0027] Process 110 can further include presenting an image of zones
402 on semiconductor device 200 to the user of the design system
via a display device. Process 110 can also interactively allow a
user to add, delete, and/or resize zones 402 manually, if
desired.
[0028] Referring to FIGS. 1 and 5, FIG. 5 is a top view of
semiconductor device 200 of FIG. 4 after a subsequent stage of
design including process 112 in which metal is added around via
202c to metal line 204 (FIG. 4) to form expanded metal line 502 in
a dielectric layer above that in which selected isolated via(s)
202c are formed and within zone 402 (FIG. 4). Oxygen sources within
the layers of the semiconductor device 200 can cause delamination
and high via resistance. The expanded metal line 502 allows out
gassing of more oxygen source than would be possible without the
increased or expanded metal. Further, since metal features are
typically formed between dielectric layers to form interconnects
with vias 202 between metal layers, no extra processing steps or
time are required to increase expanded metal line 502.
[0029] Any suitable technique or criteria can be used to determine
the size and shape of expanded metal line 502. For example,
expanded metal line 502 may be configured to obtain metal coverage
no less than ten percent of surface area within zone 402 (FIG. 4).
The size and shape of expanded metal line 502 may be selected based
on the minimum metal spacing requirements used to manufacture
semiconductor device 200.
[0030] An example for 90 mm technology can include increasing a
portion of metal line 204 around via 202c in increments of 0.01 um
with a minimum combined dimension of 0.14 um to form expanded metal
line 502 around via 202c. The expanded metal line 502 can be
increased in accordance with the design rules governing the allowed
spacing to other features in the design such as metal
interconnects, tiles, and other restricted areas.
[0031] Process 112 can include adding metal 502 on a metal layer
above selected vias 202c and within zones 402 around selected vias
202c. In some embodiments process 112 can include increasing metal
density within a space 402 enclosed by the upsized selected vias
202c. Expanding or increasing the metal density on a metal layer
above selected vias 202c and within space 402 enclosed by
temporarily upsized selected vias 202c can include defining the
space 402 enclosed by the upsized selected vias 202c as being no
larger than an order of magnitude of a minimum metal feature size
for semiconductor device 200.
[0032] For example, process 112 can include adding and
incrementally increasing metal density to obtain a metal coverage
of no less than twenty percent of surface area within the space 402
(FIG. 4) enclosed by the upsized selected vias 202c. As a more
specific example, process 112 can include selecting dimensions of
expanded metal line 502 that are capable of fitting into an
existing layout and to meet a density goal of greater than twenty
percent in space 402 enclosed by temporarily upsized selected vias
202c. Other suitable percentages for the density goal can be used,
however.
[0033] Process 112 includes forming expanded metal line 502 to meet
global and local metal density required for uniformity of
semiconductor device processing such as photo lithography and
chemical mechanical surface polishing. The expanded metal line 502
is formed in the dielectric at the same time and in a like manner
as other metal features such as trenches. As an example, expanded
metal line 502 is part of a circuit design trace needed to carry
current or distribute voltages throughout semiconductor device
200.
[0034] Referring to FIGS. 6 and 7, FIG. 6 is a top view of an
embodiment of a portion of a semiconductor device 600 including
lower dielectric layer 602, a plurality of vias 604, lower level
metal lines 606, tiling features 608, and upper level expanded
metal lines 502. FIG. 7 is a cross-section view of semiconductor
device 600 of FIG. 6 that shows lower dielectric layer 602, a
plurality of vias 604, lower level metal lines 606, tiling features
608 in dielectric layer 602, upper dielectric layer 702, etch stop
layer 704, and anti-reflective layer 710. The portion of
semiconductor device 600 may be built on an insulating layer formed
on a semiconductor substrate (not shown). Expanded metal lines 502
are shown around vias 604 that were found to be isolated. Expanded
metal lines 502 are formed as part of metal lines 606.
[0035] As an example, metal lines 502 and 606 may be formed of
copper or other suitable conductive material. Etch stop layer 704
may be formed of silicon carbon nitride (SiCN) having a thickness
ranging from 200-600 Angstroms. Dielectric layer 602 may be formed
of SiCOH with a thickness ranging from 4000 to 6000 Angstroms.
Dielectric layer 702 may be formed of tetra-ethoxy-silane (TEOS)
having a thickness ranging from 700-1300 Angstroms. Anti-reflective
layer 710 may be formed of silicon rich silicon nitride (SRN)
having a thickness ranging from 400 to 700 Angstroms, or silicon
rich silicon oxynitride (SRON) having a thickness ranging from 250
to 500 Angstroms. Other suitable thicknesses and materials may be
used, however.
[0036] Interconnect delay is a major limiting factor in the effort
to improve the speed and performance of integrated circuits (ICs).
One way to minimize interconnect delay is to reduce interconnect
capacitance by using low-k materials during production of the ICs.
Such low-k materials have also proven useful for low temperature
processing. Low-k materials have been developed to replace
relatively high dielectric constant insulating materials, such as
silicon dioxide. In particular, low-k films are being utilized for
inter-level and intra-level dielectric layers between metal layers
of semiconductor devices. Additionally, in order to further reduce
the dielectric constant of insulating materials, material films are
formed with pores, i.e., porous low-k materials.
[0037] Accordingly, dielectric layer 602 can, for example, contain
SiCOH, which is a low-k dielectric material. Low-k dielectric
materials have a nominal dielectric constant less than the
dielectric constant of SiO2, which is approximately 4 (e.g., the
dielectric constant for thermally grown silicon dioxide can range
from 3.8 to 3.9). High-k materials have a nominal dielectric
constant greater than the dielectric constant of SiO2. Low-k
dielectric materials may have a dielectric constant of less than
3.7, or a dielectric constant ranging from 1.6 to 3.7. Low-k
dielectric materials can include fluorinated silicon glass (FSG),
carbon doped oxide, a polymer, a SiCOH-containing low-k material, a
non-porous low-k material, a porous low-k material, a spin-on
dielectric (SOD) low-k material, or any other suitable dielectric
material.
[0038] Examples of two materials found suitable for low-k
dielectrics are PECVD SiCOH dielectrics formed with either TMCTS
(or OMCTS precursors). A precursor is a material which contains the
SiCOH molecules in a larger carrier molecule which flows in a
plasma chemical vapor deposition system for depositing the
dielectric film. These films have many desirable characteristics
but, as deposited, have residual OH (hydroxyl), and H2O (water)
which require out-gassing. Out-gassing is a process during which
semiconductor device 600 is heated at a specified temperature for a
specified duration of time to allow the moisture in low-k
dielectric layer 602 to dissipate.
[0039] Dielectric layer 702 may also provide a waterproof barrier
that prevents moisture from seeping into as well as out of
dielectric layer 602. If dielectric layer 702 is formed before
substantially all of the moisture is outgassed from dielectric
layer 602, residual oxygen sources could react with metal in vias
604 and lines 502, 606 to form oxides that causes delamination
between metal lines 502, 606 and dielectric layers 602, 702, as
well as create high via resistance. Areas with higher via density
provide more exposed surface area of dielectric layer 602 through
which moisture can evaporate. Moisture can be trapped in areas with
low via density however. Accordingly, expanding the metal
area/volume around isolated vias 604 allows greater dissipation of
residual oxygen (e.g., OH (hydroxyl) and H2O (water)) in dielectric
layer 602 during out-gassing process steps prior to metal forming
steps as semiconductor device 600 is manufactured.
[0040] By now it should be appreciated that there has been provided
a semiconductor device having improved via reliability. Therefore,
by identifying zones around vias in which the density of the
covering metal is less than a predetermined density threshold,
metal can be expanded in these identified zones in order to
increase the density of the covering metal. In this manner,
moisture dissipation during out-gassing processes may be
increased.
[0041] In some embodiments, a method for expanding metal lines for
selected vias in a semiconductor device having a plurality of vias
can include generating a layout database for the semiconductor
device, creating zones around the plurality of vias, measuring
density of covering metal in each zone, selecting a low density
zone as being a zone that has a metal density less than a threshold
metal density, and expanding at least one metal line on a metal
layer above the plurality of vias in the low density zone so that
metal density of the low density zone increases to at least the
same as the threshold metal density.
[0042] In another aspect, identifying low density zones can further
comprise creating the zones by upsizing the plurality of vias.
[0043] In another aspect, expanding the at least one metal line on
the metal layer can further comprise the metal layer being an
inlaid metal layer.
[0044] In another aspect, the creating zones can comprise upsizing
the vias a predetermined amount based on an original size of the
vias.
[0045] In another aspect, creating zones can comprise defining the
zones to have a dimension no larger than an order of magnitude of
twice the minimum metal feature size for the semiconductor
device.
[0046] In another aspect, expanding the at least one metal line can
further comprise expanding the at least one metal line to obtain a
metal coverage of no less than 30 percent of surface area within
the zone.
[0047] In another aspect, the method can be performed for
interlevel dielectric layers of the semiconductor device comprising
a low-k oxide.
[0048] In another aspect, creating the zones around the vias can
further comprise upsizing the vias by 0.9 micron per side.
[0049] In another embodiment, a method for increasing metal density
for selected vias in a semiconductor device having a plurality of
vias can comprise generating a layout database for the
semiconductor device, creating a plurality of zones by upsizing the
plurality of vias, selecting zones of the plurality of zones that
have less than a threshold metal density as being low density
zones, and expanding at least one metal line in each of the low
density zones.
[0050] In another aspect, creating the plurality of zones can
further comprise defining the zones as being no larger than an
order of magnitude of twice the minimum metal feature size for the
semiconductor device.
[0051] In another aspect, expanding a metal layer within a space
enclosed by each of the low density zones can achieve a target
metal density of at least 10 percent within the space.
[0052] In another aspect, creating the plurality of zones can
further comprise sizing the zones to be no greater than twelve
times a minimum pitch between metal lines for the semiconductor
device.
[0053] In another aspect, expanding the at least one metal line can
further comprise expanding the at least one metal line to obtain a
metal coverage of no less than five percent of surface area within
the low density zones.
[0054] In another aspect, the method can be performed for
interlevel dielectric layers of the semiconductor device comprising
a low-k oxide.
[0055] In another embodiment, a semiconductor device can comprise a
first insulating layer, a first metal conductor layer formed over
the first insulating layer, a second insulating layer comprising a
low-k insulating material formed over the first metal conductor, a
second metal conductor layer formed over the second insulating
layer vias formed in the second insulating layer connecting the
first metal conductor layer to the second metal conductor layer,
and a plurality of metal lines, one of the metal lines being
expanded around one of the vias compared to metal lines around
other ones of the vias so that predetermined areas around each of
the vias meets a minimum metal density.
[0056] In another aspect, a low-k insulating material can be an
insulating material having a relative permittivity of less than
about 3.9.
[0057] In another aspect, moisture in the semiconductor device can
be vented by the metal trenches during a heating step of the
semiconductor device.
[0058] In another aspect, the plurality of metal lines can comprise
a metal.
[0059] In another aspect, the predetermined areas can be no larger
than an order of magnitude of twice the minimum metal feature size
of the semiconductor device.
[0060] In another aspect, metal density within the predetermined
areas can be greater than about five percent.
[0061] Process 100 can be performed by executing program logic
instructions on a general purpose computer, such as a workstation
coupled to a mainframe computer, and/or a desktop, laptop, tablet,
or notebook computer. The term "program," as used herein, is
defined as a sequence of instructions designed for execution on a
computer system. A program, or computer program, may include a
subroutine, a function, a procedure, an object method, an object
implementation, an executable application, an applet, a servlet, a
source code, an object code, a shared library/dynamic load library
and/or other sequence of instructions designed for execution on a
computer system.
[0062] Furthermore, those skilled in the art will recognize that
boundaries between the functionality of the above described
processes and methods are merely illustrative. The functionality of
multiple operations may be combined into a single operation, and/or
the functionality of a single operation may be distributed in
additional operations. Moreover, alternative embodiments may
include multiple instances of a particular operation, and the order
of operations may be altered in various other embodiments.
[0063] A computer system processes information according to a
program and produces resultant output information via I/O devices.
A program is a list of instructions such as a particular
application program and/or an operating system. A computer program
is typically stored internally on computer readable storage medium
or transmitted to the computer system via a computer readable
transmission medium. A computer process typically includes an
executing (running) program or portion of a program, current
program values and state information, and the resources used by the
operating system to manage the execution of the process. A parent
process may spawn other, child processes to help perform the
overall functionality of the parent process. Because the parent
process specifically spawns the child processes to perform a
portion of the overall functionality of the parent process, the
functions performed by child processes (and grandchild processes,
etc.) may sometimes be described as being performed by the parent
process.
[0064] Although the disclosure is described herein with reference
to specific embodiments, various modifications and changes can be
made without departing from the scope of the present disclosure as
set forth in the claims below. Accordingly, the specification and
figures are to be regarded in an illustrative rather than a
restrictive sense, and all such modifications are intended to be
included within the scope of the present disclosure. Any benefits,
advantages, or solutions to problems that are described herein with
regard to specific embodiments are not intended to be construed as
a critical, required, or essential feature or element of any or all
the claims.
[0065] The term "coupled," as used herein, is not intended to be
limited to a direct coupling or a mechanical coupling.
[0066] Furthermore, the terms "a" or "an," as used herein, are
defined as one or more than one. Also, the use of introductory
phrases such as "at least one" and "one or more" in the claims
should not be construed to imply that the introduction of another
claim element by the indefinite articles "a" or "an" limits any
particular claim containing such introduced claim element to
disclosures containing only one such element, even when the same
claim includes the introductory phrases "one or more" or "at least
one" and indefinite articles such as "a" or "an." The same holds
true for the use of definite articles.
[0067] Unless stated otherwise, terms such as "first" and "second"
are used to arbitrarily distinguish between the elements such terms
describe. Thus, these terms are not necessarily intended to
indicate temporal or other prioritization of such elements.
* * * * *