Reber; Douglas M.

Patent Applications and Registrations

Patent applications and USPTO patent grants for Reber; Douglas M..The latest application filed is for "method of forming inter-level dielectric structures on semiconductor devices".

Company Profile

4.83.81

Reber; Douglas M. - Austin TX US
Reber; Douglas M - Austin TX
Reber; Douglas M. - St. Ismier FR

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Semiconductor manufacturing using disposable test circuitry within scribe lanes Grant 10,553,508 - Reber , et al. Fe	2020-02-04
Semiconductor package with embedded capacitor and methods of manufacturing same Grant 10,522,615 - Ajuria , et al. Dec	2019-12-31
Method of forming inter-level dielectric structures on semiconductor devices Grant 10,262,893 - Reber , et al.	2019-04-16
Semiconductor device with graphene encapsulated metal and method therefor Grant 10,204,860 - Reber , et al. Feb	2019-02-12
Apparatus and method for placing stressors within an integrated circuit device to manage electromigration failures Grant 10,014,257 - Reber , et al. July 3, 2	2018-07-03
Solar cell powered integrated circuit device and method therefor Grant 10,008,447 - Reber , et al. June 26, 2	2018-06-26
Method for verifying design rule checks Grant 9,934,349 - Bhawnani , et al. April 3, 2	2018-04-03
Method Of Forming Inter-level Dielectric Structures On Semiconductor Devices App 20180047616 - REBER; DOUGLAS M. ; et al.	2018-02-15
Method of forming inter-level dielectric structures on semiconductor devices Grant 9,818,642 - Reber , et al. November 14, 2	2017-11-14
Semiconductor Device With Graphene Encapsulated Metal And Method Therefor App 20170194264 - REBER; DOUGLAS M. ; et al.	2017-07-06
Fuse/resistor utilizing interconnect and vias and method of making Grant 9,685,405 - Shroff , et al. June 20, 2	2017-06-20
Integrated circuit design using pre-marked circuit element object library Grant 9,652,577 - Travis , et al. May 16, 2	2017-05-16
Semiconductor device with graphene encapsulated metal and method therefor Grant 9,640,430 - Reber , et al. May 2, 2	2017-05-02
Semiconductor Package With Embedded Capacitor And Methods Of Manufacturing Same App 20170084682 - AJURIA; SERGIO A. ; et al.	2017-03-23
Semiconductor Device With Graphene Encapsulated Metal And Method Therefor App 20170084484 - REBER; DOUGLAS M. ; et al.	2017-03-23
Semiconductor manufacturing for forming bond pads and seal rings Grant 9,601,354 - Reber , et al. March 21, 2	2017-03-21
Apparatus And Method For Placing Stressors Within An Integrated Circuit Device To Manage Electromigration Failures App 20170069572 - Reber; Douglas M. ; et al.	2017-03-09
Semiconductor package with embedded capacitor and methods of manufacturing same Grant 9,548,266 - Ajuria , et al. January 17, 2	2017-01-17
3D device packaging using through-substrate posts Grant 9,515,006 - Reber , et al. December 6, 2	2016-12-06
3D device packaging using through-substrate pillars Grant 9,508,701 - Reber , et al. November 29, 2	2016-11-29
3D device packaging using through-substrate posts Grant 9,508,702 - Reber , et al. November 29, 2	2016-11-29
Solar Cell Powered Integrated Circuit Device And Method Therefor App 20160343696 - REBER; DOUGLAS M. ; et al.	2016-11-24
Method Of Forming Inter-level Dielectric Structures On Semiconductor Devices App 20160307791 - REBER; DOUGLAS M. ; et al.	2016-10-20
Though-substrate vias (TSVs) and method therefor Grant 9,466,569 - Shroff , et al. October 11, 2	2016-10-11
Method For Verifying Design Rule Checks App 20160283642 - BHAWNANI; INDER MOHAN ; et al.	2016-09-29
Apparatus and method for placing stressors on interconnects within an integrated circuit device to manage electromigration failures Grant 9,455,220 - Shroff , et al. September 27, 2	2016-09-27
Teleconferencing environment having auditory and visual cues Grant 9,445,050 - Travis , et al. September 13, 2	2016-09-13
Capping layer interface interruption for stress migration mitigation Grant 9,443,804 - Shroff , et al. September 13, 2	2016-09-13
Teleconferencing Environment Having Auditory And Visual Cues App 20160142674 - TRAVIS; Edward O. ; et al.	2016-05-19
THOUGH-SUBSTRATE VIAS (TSVs) AND METHOD THEREFOR App 20160133574 - SHROFF; MEHUL D. ; et al.	2016-05-12
Integrated circuit heater for reducing stress in the integrated circuit material and chip leads of the integrated circuit, and for optimizing performance of devices of the integrated circuit Grant 9,318,409 - Reber , et al. April 19, 2	2016-04-19
Integrated Circuit Design Using Pre-Marked Circuit Element Object Library App 20160098510 - Travis; Edward O. ; et al.	2016-04-07
Integrated Circuit Heater For Reducing Stress In The Integrated Circuit Material And Chip Leads Of The Integrated Circit, And For Optimizing Performance Of Devices Of The Integrated Circuit App 20160093549 - Reber; Douglas M. ; et al.	2016-03-31
Semiconductor Manufacturing For Forming Bond Pads And Seal Rings App 20160064294 - REBER; DOUGLAS M. ; et al.	2016-03-03
Semiconductor Package With Embedded Capacitor And Methods Of Manufacturing Same App 20160064324 - Ajuria; Sergio A. ; et al.	2016-03-03
Semiconductor device with embedded heat spreading Grant 9,245,817 - Travis , et al. January 26, 2	2016-01-26
Thin beam deposited fuse Grant 9,236,344 - Reber , et al. January 12, 2	2016-01-12
Semiconductor device having a nanotube layer and method for forming Grant 9,224,692 - Reber December 29, 2	2015-12-29
Apparatus And Method For Placing Stressors Within An Integrated Circuit Device To Manage Electromigration Failures App 20150348898 - Shroff; Mehul D. ; et al.	2015-12-03
Stress migration mitigation utilizing induced stress effects in metal trace of integrated circuit device Grant 9,142,507 - Shroff , et al. September 22, 2	2015-09-22
Method for forming a packaged semiconductor device Grant 9,134,366 - Ajuria , et al. September 15, 2	2015-09-15
Stress Migration Mitigation Utilizing Induced Stress Effects In Metal Trace Of Integrated Circuit Device App 20150249048 - Shroff; Mehul D. ; et al.	2015-09-03
Stress migration mitigation Grant 9,122,829 - Reber , et al. September 1, 2	2015-09-01
Semiconductor device with vias on a bridge connecting two buses Grant 9,122,812 - Reber , et al. September 1, 2	2015-09-01
Semiconductor Device Having A Nanotube Layer And Method For Forming App 20150206843 - REBER; DOUGLAS M.	2015-07-23
Semiconductor Manufacturing Using Disposable Test Circuitry Within Scribe Lanes App 20150200146 - Reber; Douglas M. ; et al.	2015-07-16
Method for forming an electrical connection between metal layers Grant 9,082,824 - Reber , et al. July 14, 2	2015-07-14
Semiconductor Manufacturing Using Design Verification With Markers App 20150178438 - DEMIRCAN; ERTUGRUL ; et al.	2015-06-25
Method and apparatus to improve reliability of vias Grant 9,041,209 - Reber , et al. May 26, 2	2015-05-26
Thin Beam Deposited Fuse App 20150137311 - Reber; Douglas M. ; et al.	2015-05-21
Method for forming an electrical connection between metal layers Grant 9,032,615 - Travis , et al. May 19, 2	2015-05-19
3d Device Packaging Using Through-substrate Pillars App 20150091178 - Reber; Douglas M. ; et al.	2015-04-02
3d Device Packaging Using Through-substrate Posts App 20150091187 - Reber; Douglas M. ; et al.	2015-04-02
3d Device Packaging Using Through-substrate Posts App 20150091160 - Reber; Douglas M.	2015-04-02
Methods and apparatus to improve reliability of isolated vias Grant 8,987,916 - Reber March 24, 2	2015-03-24
Method For Forming A Packaged Semiconductor Device App 20150061709 - Ajuria; Sergio A. ; et al.	2015-03-05
Method for forming an electrical connection between metal layers Grant 8,972,922 - Reber , et al. March 3, 2	2015-03-03
Stress Migration Mitigation App 20150040092 - Reber; Douglas M. ; et al.	2015-02-05
Capping Layer Interface Interruption for Stress Migration Mitigation App 20150035151 - Shroff; Mehul D. ; et al.	2015-02-05
Method for forming an integrated circuit having a programmable fuse Grant 8,946,000 - Reber , et al. February 3, 2	2015-02-03
Method of protecting against via failure and structure therefor Grant 8,941,242 - Shroff , et al. January 27, 2	2015-01-27
Fuse/resistor Utilizing Interconnect And Vias And Method Of Making App 20140353797 - SHROFF; Mehul D. ; et al.	2014-12-04
Method For Forming An Electrical Connection Between Metal Layers App 20140353841 - Reber; Douglas M. ; et al.	2014-12-04
Semiconductor device having a nanotube layer and method for forming Grant 8,883,639 - Reber November 11, 2	2014-11-11
Semiconductor Device With Embedded Heat Spreading App 20140329383 - TRAVIS; EDWARD O. ; et al.	2014-11-06
Semiconductor Device With Vias On A Bridge Connecting Two Buses App 20140258582 - REBER; DOUGLAS M. ; et al.	2014-09-11
Multi-layer process-induced damage tracking and remediation Grant 8,832,624 - Shroff , et al. September 9, 2	2014-09-09
Thin Beam Deposited Fuse App 20140239440 - Reber; Douglas M. ; et al.	2014-08-28
Semiconductor device with embedded heat spreading Grant 8,796,841 - Travis , et al. August 5, 2	2014-08-05
Semiconductor device with vias on a bridge connecting two buses Grant 8,736,071 - Reber , et al. May 27, 2	2014-05-27
Method and apparatus to improve reliability of vias Grant 8,703,507 - Reber April 22, 2	2014-04-22
Method and system for derived layer checking for semiconductor device design Grant 8,707,231 - Reber , et al. April 22, 2	2014-04-22
Techniques for checking computer-aided design layers of a device to reduce the occurrence of missing deck rules Grant 8,694,926 - Reber , et al. April 8, 2	2014-04-08
Method And Apparatus To Improve Reliability Of Vias App 20140091475 - REBER; DOUGLAS M.	2014-04-03
Method For Forming An Electrical Connection Between Metal Layers App 20140094029 - REBER; DOUGLAS M. ; et al.	2014-04-03
Method And System For Derived Layer Checking For Semiconductor Device Design App 20140040839 - Reber; Douglas M. ; et al.	2014-02-06
Method For Forming An Electrical Connection Between Metal Layers App 20140038317 - Travis; Edward O. ; et al.	2014-02-06
Method For Forming An Electrical Connection Between Metal Layers App 20140038319 - Reber; Douglas M. ; et al.	2014-02-06
Method for forming an electrical connection between metal layers Grant 8,640,072 - Reber , et al. January 28, 2	2014-01-28
Techniques For Checking Computer-aided Design Layers Of A Device To Reduce The Occurrence Of Missing Deck Rules App 20130326446 - Reber; Douglas M. ; et al.	2013-12-05
Device matching tool and methods thereof Grant 8,601,430 - Shroff , et al. December 3, 2	2013-12-03
Via placement and electronic circuit design processing method and electronic circuit design utilizing same Grant 8,595,667 - Shroff , et al. November 26, 2	2013-11-26
Semiconductor device with heat dissipation Grant 8,581,390 - Travis , et al. November 12, 2	2013-11-12
Semiconductor Device With Heat Dissipation App 20130264698 - Travis; Edward O. ; et al.	2013-10-10
Semiconductor Device With Embedded Heat Spreading App 20130264700 - TRAVIS; EDWARD O. ; et al.	2013-10-10
Semiconductor Device Having A Nanotube Layer And Method For Forming App 20130187274 - Reber; Douglas M.	2013-07-25
Methods and apparatus to improve reliability of isolated vias Grant 8,486,839 - Reber , et al. July 16, 2	2013-07-16
Method Of Protecting Against Via Failure And Structure Therefor App 20130147051 - SHROFF; MEHUL D. ; et al.	2013-06-13
Methods And Apparatus To Improve Reliability Of Isolated Vias App 20130134595 - REBER; DOUGLAS M.	2013-05-30
Method And Apparatus To Improve Reliability Of Vias App 20130127064 - Reber; Douglas M. ; et al.	2013-05-23
Semiconductor Device With Vias On A Bridge Connecting Two Buses App 20130105986 - REBER; DOUGLAS M. ; et al.	2013-05-02
Methods And Apparatus To Improve Reliability Of Isolated Vias App 20120299190 - REBER; DOUGLAS M. ; et al.	2012-11-29
Method For Forming An Over Pad Metalization (opm) On A Bond Pad App 20120178189 - Reber; Douglas M.	2012-07-12
Semiconductor device having an organic anti-reflective coating (ARC) and method therefor Grant 8,039,389 - Reber , et al. October 18, 2	2011-10-18
Semiconductor Device Having An Organic Anti-reflective Coating (arc) And Method Therefor App 20070141770 - Reber; Douglas M. ; et al.	2007-06-21
Semiconductor device having an organic anti-reflective coating (ARC) and method therefor Grant 7,199,429 - Reber , et al. April 3, 2	2007-04-03
Semiconductor device having an organic anti-reflective coating (ARC) and method therefor Grant 6,972,255 - Reber , et al. December 6, 2	2005-12-06
Semiconductor device having an organic anti-reflective coating (ARC) and method therefor App 20050181596 - Reber, Douglas M. ; et al.	2005-08-18
Semiconductor device having an organic anti-reflective coating (ARC) and method therefor App 20050026338 - Reber, Douglas M. ; et al.	2005-02-03
Method of forming semiconductor device including interconnect barrier layers Grant 6,713,381 - Barr , et al. March 30, 2	2004-03-30
Anti-fuse circuit and method of operation Grant 6,597,234 - Reber , et al. July 22, 2	2003-07-22
Anti-fuse Circuit And Method Of Operation App 20030112055 - Reber, Douglas M. ; et al.	2003-06-19
Intergrated Circuit Having Interconnect To A Substrate And Method Therefor App 20030075806 - Reber, Douglas M.	2003-04-24
Low temperature, high quality silicon dioxide thin films deposited using tetramethylsilane (TMS) for stress control and coverage applications Grant 6,531,193 - Fonash , et al. March 11, 2	2003-03-11
Low temperature, high quality silicon dioxide thin films deposited using tetramethylsilane (TMS) for stress control and coverage applications App 20020094388 - Fonash, Stephen J. ; et al.	2002-07-18
Semiconductor device and method of formation App 20020093098 - Barr, Alexander L. ; et al.	2002-07-18
Semiconductor Device Conductive Bump And Interconnect Barrier App 20020000665 - BARR, ALEXANDER L. ; et al.	2002-01-03
Low temperature, high quality silicon dioxide thin films deposited using tetramethylsilane (TMS) Grant 6,159,559 - Reber , et al. December 12, 2	2000-12-12

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