U.S. patent application number 14/089982 was filed with the patent office on 2014-03-27 for dual metal fill and dual threshold voltage for replacement gate metal devices.
This patent application is currently assigned to International Business Machines Corporation. The applicant listed for this patent is International Business Machines Corporation. Invention is credited to Nathaniel Berliner, James John Demarest, Lisa F. Edge, Balasubramanian S. Haran.
Application Number | 20140084382 14/089982 |
Document ID | / |
Family ID | 48902177 |
Filed Date | 2014-03-27 |
United States Patent
Application |
20140084382 |
Kind Code |
A1 |
Berliner; Nathaniel ; et
al. |
March 27, 2014 |
DUAL METAL FILL AND DUAL THRESHOLD VOLTAGE FOR REPLACEMENT GATE
METAL DEVICES
Abstract
A structure and method for forming a dual metal fill and dual
threshold voltage for replacement gate metal devices is disclosed.
A selective deposition process involving titanium and aluminum is
used to allow formation of two adjacent transistors with different
fill metals and different workfunction metals, enabling different
threshold voltages in the adjacent transistors.
Inventors: |
Berliner; Nathaniel;
(Albany, NY) ; Demarest; James John; (Rensselaer,
NY) ; Edge; Lisa F.; (Watervliet, NY) ; Haran;
Balasubramanian S.; (Watervliet, NY) |
|
Applicant: |
Name |
City |
State |
Country |
Type |
International Business Machines Corporation |
Armonk |
NY |
US |
|
|
Assignee: |
International Business Machines
Corporation
Armonk
NY
|
Family ID: |
48902177 |
Appl. No.: |
14/089982 |
Filed: |
November 26, 2013 |
Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
|
|
13367419 |
Feb 7, 2012 |
|
|
|
14089982 |
|
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Current U.S.
Class: |
257/392 |
Current CPC
Class: |
H01L 21/28088 20130101;
H01L 29/66545 20130101; H01L 29/49 20130101; H01L 21/82345
20130101; H01L 27/088 20130101; H01L 21/823842 20130101 |
Class at
Publication: |
257/392 |
International
Class: |
H01L 29/49 20060101
H01L029/49; H01L 27/088 20060101 H01L027/088 |
Claims
1-13. (canceled)
14. A semiconductor structure comprising: a first field effect
transistor comprising a first gate cavity; a second field effect
transistor comprising a second gate cavity; a first fill metal
disposed in the first gate cavity; and a second fill metal disposed
in the second gate cavity.
15. The semiconductor structure of claim 14, wherein the first fill
metal comprises aluminum.
16. The semiconductor structure of claim 15, wherein the second
fill metal comprises tungsten.
17. The semiconductor structure of claim 15, wherein a titanium
layer is disposed under the first fill metal and is not disposed
under the second fill metal.
18. The semiconductor structure of claim 17, further comprising a
first workfunction metal disposed under the titanium layer, and a
second workfunction metal disposed under the second fill metal.
19. The semiconductor structure of claim 18, wherein the first
workfunction metal comprises titanium nitride.
20. The semiconductor structure of claim 18, wherein the second
workfunction metal is comprised of a material selected from the
group consisting of titanium aluminum nitride and tantalum carbide.
Description
FIELD OF THE INVENTION
[0001] The present invention relates generally to semiconductor
devices and more particularly to integrated circuits including
metal gate MOS transistor devices and fabrication methods for
making the same.
BACKGROUND OF THE INVENTION
[0002] Field effect transistors (FETs) are widely used in the
electronics industry for switching, amplification, filtering, and
other tasks related to both analog and digital electrical signals.
Most common among these are metal-oxide-semiconductor field-effect
transistors (MOSFETs), wherein a gate electrode is energized to
create an electric field in a channel region of a semiconductor
body, by which electrons are allowed to travel through the channel
between a source region and a drain region of the semiconductor
body. The source and drain regions are typically formed by adding
dopants to targeted regions on either side of the channel. A gate
dielectric or gate oxide is formed over the channel, and a gate
electrode or gate contact is formed over the gate dielectric. The
gate dielectric and gate electrode layers are then patterned to
form a gate structure overlying the channel region of the
substrate.
[0003] In operation of the resulting MOS transistor, the threshold
voltage (Vt) is the gate voltage value required to render the
channel conductive by formation of an inversion layer at the
surface of the semiconductor channel. The threshold voltage is
dependent upon, among other things, the workfunction difference
between the gate and the substrate materials. In various circuit
designs, it is desirable to have transistors with different
threshold voltages within the same IC (integrated circuit)
chip.
[0004] The workfunction of a material is a measure of the energy
required to move an electron in the material outside of a material
atom from the Fermi level, and is usually expressed in electron
volts (eV). For CMOS products, it is desirable to provide
predictable, repeatable, and stable threshold voltages (Vt) for the
NMOS and PMOS transistors. To establish Vt values, the
workfunctions of the PMOS and NMOS gate contact and the
corresponding channel materials are independently tuned or adjusted
through gate and channel engineering, respectively.
[0005] The use of different workfunction metals may be used to tune
threshold voltages. However, this technique often requires
additional mask levels, resulting in higher complexity and cost for
fabrication. Furthermore, residual work function metals on
respective devices may cause unacceptable levels of yield and
device variability. Therefore, it is desirable to have an improved
method and structure for achieving multiple threshold voltages
within a chip.
SUMMARY
[0006] In one embodiment, a method for forming two transistors
having different threshold voltages is provided. The method
comprises forming a first gate cavity in a first transistor and a
second gate cavity in a second transistor, depositing a gate
dielectric film in the gate cavity of the first and second
transistors, depositing a first workfunction metal in the gate
cavity of the first and second transistors, depositing a titanium
layer in the gate cavity of the first and second transistors,
removing the titanium layer from the gate cavity of the second
transistor, depositing a first fill metal in the gate cavity of the
first transistor, depositing a second workfunction metal in the
gate cavity of the second transistor, depositing a second fill
metal in the gate cavity of the second transistor, and planarizing
the first and second transistors.
[0007] In another embodiment, a method for forming two transistors
having different threshold voltages is provided. The method
comprises forming a first gate cavity in a first transistor and a
second gate cavity in a second transistor, depositing a gate
dielectric film in the gate cavity of the first and second
transistors, depositing a first workfunction metal in the gate
cavity of the first and second transistors, depositing a titanium
layer in the gate cavity of the first and second transistors,
depositing a hardmask layer in the gate cavity of the first and
second transistors, removing a portion of the hardmask layer from
the gate cavity of the second transistor, removing the titanium
layer from the gate cavity of the second transistor, removing the
hardmask layer from the gate cavity of the first transistor,
depositing a first fill metal in the gate cavity of the first
transistor, depositing a second workfunction metal in the gate
cavity of the second transistor, depositing a second fill metal in
the gate cavity of the second transistor, and planarizing the first
and second transistors.
[0008] In another embodiment, a semiconductor structure is
provided. The semiconductor structure comprises a first field
effect transistor comprising a first gate cavity, a second field
effect transistor comprising a second gate cavity, a first fill
metal disposed in the first gate cavity, and a second fill metal
disposed in the second gate cavity.
BRIEF DESCRIPTION OF THE DRAWINGS
[0009] The structure, operation, and advantages of the present
invention will become further apparent upon consideration of the
following description taken in conjunction with the accompanying
figures (FIGs.). The figures are intended to be illustrative, not
limiting.
[0010] Certain elements in some of the figures may be omitted, or
illustrated not-to-scale, for illustrative clarity. The
cross-sectional views may be in the form of "slices", or
"near-sighted" cross-sectional views, omitting certain background
lines which would otherwise be visible in a "true" cross-sectional
view, for illustrative clarity.
[0011] Often, similar elements may be referred to by similar
numbers in various figures (FIGs) of the drawing, in which case
typically the last two significant digits may be the same, the most
significant digit being the number of the drawing figure (FIG).
[0012] FIG. 1 shows a semiconductor structure 100 at a starting
point for fabrication of an embodiment of the present
invention.
[0013] FIG. 2 shows a semiconductor structure at a subsequent point
in the fabrication process where a gate dielectric film is
deposited.
[0014] FIG. 3 shows a semiconductor structure at a subsequent point
in the fabrication process where a first workfunction metal is
deposited.
[0015] FIG. 4 shows a semiconductor structure at a subsequent point
in the fabrication process where a titanium layer is deposited.
[0016] FIG. 5 shows a semiconductor structure at a subsequent point
in the fabrication process where a hardmask layer is deposited.
[0017] FIG. 6 shows a semiconductor structure at a subsequent point
in the fabrication process where a portion of the hardmask layer is
removed.
[0018] FIG. 7 shows a semiconductor structure at a subsequent point
in the fabrication process where a portion of the titanium layer is
removed.
[0019] FIG. 8 shows a semiconductor structure at a subsequent point
in the fabrication process where the remaining hardmask portion is
removed.
[0020] FIG. 9 shows a semiconductor structure at a subsequent point
in the fabrication process where a first fill metal is
deposited.
[0021] FIG. 10 shows a semiconductor structure at a subsequent
point in the fabrication process where a second workfunction metal
is deposited.
[0022] FIG. 11 shows a semiconductor structure at a subsequent
point in the fabrication process where a second fill metal is
deposited.
[0023] FIG. 12 shows a semiconductor structure at a subsequent
point in the fabrication process after planarization.
[0024] FIG. 13 shows a flowchart indicating process steps in
accordance with an embodiment of the present invention.
[0025] FIG. 14 shows a block diagram of an exemplary design
flow.
DETAILED DESCRIPTION
[0026] FIG. 1 shows a semiconductor structure at a starting point
for fabrication of an embodiment of the present invention. A
silicon layer 102 forms the bottom of the structure. Disposed on
silicon layer 102 is dielectric layer 110. A first gate cavity 106
and second gate cavity 104 are formed within the dielectric layer
110. Spacers 108 form the interior walls of the gate cavity 104 and
gate cavity 106. The spacers 108 may be comprised of nitride.
[0027] FIG. 2 shows a semiconductor structure 200 at a subsequent
point in the fabrication process where gate dielectric film 212 is
deposited in the first gate cavity 206 and second gate cavity 204.
Most any suitable gate dielectric material can be used. In one
embodiment, the gate dielectric film comprises one of hafnium
oxide, silicon oxide, or a compound of the form HfSiOx. As stated
previously, similar elements may be referred to by similar numbers
in various figures of the drawing, in which case typically the last
two significant digits may be the same, the most significant digit
being the number of the drawing figure. Furthermore, for clarity,
some reference numbers may be omitted in certain drawings. For
example, spacer 208 of FIG. 2 is similar to spacer 108 of FIG.
1.
[0028] FIG. 3 shows a semiconductor structure 300 at a subsequent
point in the fabrication process where a first workfunction metal
314 is deposited in the first gate cavity 306 and the second gate
cavity 304. The first workfunction metal 314 may be deposited via
atomic layer deposition. The first workfunction metal may be
comprised of titanium nitride (TiN).
[0029] FIG. 4 shows a semiconductor structure 400 at a subsequent
point in the fabrication process where a titanium layer 416 is
deposited in the first gate cavity 406 and the second gate cavity
404. The titanium layer may be deposited via numerous methods,
including, but not limited to, plasma-enhanced chemical vapor
deposition (PECVD), chemical vapor deposition (CVD), and atomic
layer deposition (ALD).
[0030] FIG. 5 shows a semiconductor structure 500 at a subsequent
point in the fabrication process where a hardmask layer 518 is
deposited onto the semiconductor structure 500, filling the two
gate cavities (compare with 404 and 406 of FIG. 4).
[0031] FIG. 6 shows a semiconductor structure 600 at a subsequent
point in the fabrication process where a portion of the hardmask
layer is removed, exposing gate cavity 604, whereas a portion of
the hardmask layer 618 remains, and fills the other gate cavity.
Industry-standard lithographic and patterning methods may be used
in the application and removal of the hardmask layer.
[0032] FIG. 7 shows a semiconductor structure 700 at a subsequent
point in the fabrication process where a portion of the titanium
layer is removed from gate cavity 704, whereas a portion of the
titanium layer 716 remains, and is disposed within the other gate
cavity. The removed portion of the titanium layer may be removed
from gate cavity 704 via a sputter etch.
[0033] FIG. 8 shows a semiconductor structure 800 at a subsequent
point in the fabrication process where the remaining hardmask
portion (see 718 of FIG. 7) is removed. At this point gate cavity
804 and gate cavity 806 are both exposed. Gate cavity 806 has
titanium layer 816 disposed within it, whereas gate cavity 804 does
not have a corresponding titanium layer.
[0034] FIG. 9 shows a semiconductor structure 900 at a subsequent
point in the fabrication process where a first fill metal 920 is
deposited. The first fill metal may be aluminum, and may be
deposited via methods including, but not limited to, chemical vapor
deposition (CVD), plasma-enhanced chemical vapor deposition
(PECVD), and atomic layer deposition (ALD). The aluminum has
selective deposition properties, and only deposits on titanium
layer 916. Hence, aluminum does not deposit in gate cavity 904. The
titanium layer 916 can serve two purposes. In addition to enabling
the selective deposition, it can also contribute to the threshold
voltage of the transistor.
[0035] FIG. 10 shows a semiconductor structure 1000 at a subsequent
point in the fabrication process where a second workfunction metal
1022 is deposited. In one embodiment, the second workfunction metal
1022 is comprised of titanium aluminum nitride. In another
embodiment, the second workfunction metal 1022 is comprised of
tantalum carbide.
[0036] FIG. 11 shows a semiconductor structure 1100 at a subsequent
point in the fabrication process where a second fill metal 1124 is
deposited. In one embodiment, the second fill metal 1124 is
comprised of tungsten. In other embodiments, the second fill metal
1124 may be comprised a material including, but not limited to,
cobalt, molybdenum, ruthenium, nickel, tungsten, or combinations
thereof.
[0037] FIG. 12 shows a semiconductor structure 1200 in accordance
with an embodiment of the present invention after a planarization
step. The planarization may be performed via a chemical mechanical
polish (CMP). From this point forward, industry-standard
semiconductor fabrication techniques may be used to complete the
fabrication of transistor 1244 and transistor 1246. Transistor 1244
and transistor 1246 have different fill metals. Transistor 1246 has
fill metal 1220 which may be comprised of aluminum. Transistor 1244
has fill metal 1224 which may be comprised of tungsten. Transistor
1246 has a titanium layer 1216 disposed under fill metal 1220,
whereas transistor 1244 does not have a corresponding titanium
layer disposed under fill metal 1224.
[0038] Furthermore, transistor 1244 has a second workfunction metal
1222 disposed under fill metal 1224, whereas transistor 1246 does
not have a corresponding second workfunction metal disposed under
fill metal 1220. The workfunction metals used in transistor 1244
and transistor 1246 may include, but are not limited to, pure
metals, nitrides, carbides, and combinations thereof. Such
workfunction metals may include, but are not limited to, TaC, TiAl,
TiAlN, WN, Ti, Ta, TaN, TaAlC, and TaAlN.
[0039] Since the threshold voltage of a transistor is affected by
both workfunction metals and fill metals, the ability to fabricate
transistors on the same chip with different fill metals and
workfunction metals allows for fabrication of transistors on the
same chip with different threshold voltages. For design purposes,
it is often desirable to have transistors with different threshold
voltages on the same chip. Hence, embodiments of the present
invention provide a way to achieve this goal without the
disadvantages of additional masks or yield-impacting techniques
that leave residual metals, which results in large threshold
voltage variation amongst fabricated devices. Furthermore, while
the example disclosed illustrated use of an embodiment of the
invention with a planar technology such as ETSOI (extremely thin
silicon-on-insulator), embodiments of the present invention are
suitable for other device types, such as "3D" structures such as
FinFETs.
[0040] FIG. 13 shows a flowchart 1350 indicating process steps in
accordance with an embodiment of the present invention. In process
step 1352, gate cavities are formed (see 104 and 106 of FIG. 1). In
process step 1354, a gate dielectric film is deposited (see 212 of
FIG. 2). In process step 1356, a first workfunction metal is
deposited (see 314 of FIG. 3). In process step 1358, a titanium
layer is deposited (see 416 of FIG. 4). In process step 1360, a
portion of the titanium layer is removed (see 716 of FIG. 7). In
process step 1362, a first fill metal is deposited (see 920 of FIG.
9). In process step 1364, a second workfunction metal is deposited
(see 1022 of FIG. 10). In process step 1366, a second fill metal is
deposited (see 1124 of FIG. 11). In process step 1368, the
structure is planarized (see 1200 of FIG. 12).
[0041] FIG. 14 shows a block diagram of an exemplary design flow
1600 used for example, in semiconductor IC logic design,
simulation, test, layout, and manufacture. Design flow 1600
includes processes, machines and/or mechanisms for processing
design structures or devices to generate logically or otherwise
functionally equivalent representations of the design structures
and/or devices described above and shown in FIGS. 1-13. The design
structures processed and/or generated by design flow 1600 may be
encoded on machine-readable transmission or storage media to
include data and/or instructions that when executed or otherwise
processed on a data processing system generate a logically,
structurally, mechanically, or otherwise functionally equivalent
representation of hardware components, circuits, devices, or
systems. Machines include, but are not limited to, any machine used
in an IC design process, such as designing, manufacturing, or
simulating a circuit, component, device, or system. For example,
machines may include: lithography machines, machines and/or
equipment for generating masks (e.g. e-beam writers), computers or
equipment for simulating design structures, any apparatus used in
the manufacturing or test process, or any machines for programming
functionally equivalent representations of the design structures
into any medium (e.g. a machine for programming a programmable gate
array).
[0042] Design flow 1600 may vary depending on the type of
representation being designed. For example, a design flow 1600 for
building an application specific IC (ASIC) may differ from a design
flow 1600 for designing a standard component or from a design flow
1600 for instantiating the design into a programmable array, for
example a programmable gate array (PGA) or a field programmable
gate array (FPGA) offered by Altera.RTM. Inc. or Xilinx.RTM.
Inc.
[0043] FIG. 14 illustrates multiple such design structures
including an input design structure 1620 that is preferably
processed by a design process 1610. Design structure 1620 may be a
logical simulation design structure generated and processed by
design process 1610 to produce a logically equivalent functional
representation of a hardware device. Design structure 1620 may also
or alternatively comprise data and/or program instructions that
when processed by design process 1610, generate a functional
representation of the physical structure of a hardware device.
Whether representing functional and/or structural design features,
design structure 1620 may be generated using electronic
computer-aided design (ECAD) such as implemented by a core
developer/designer. When encoded on a machine-readable data
transmission, gate array, or storage medium, design structure 1620
may be accessed and processed by one or more hardware and/or
software modules within design process 1610 to simulate or
otherwise functionally represent an electronic component, circuit,
electronic or logic module, apparatus, device, or system such as
those shown in FIGS. 1-13. As such, design structure 1620 may
comprise files or other data structures including human and/or
machine-readable source code, compiled structures, and
computer-executable code structures that when processed by a design
or simulation data processing system, functionally simulate or
otherwise represent circuits or other levels of hardware logic
design. Such data structures may include hardware-description
language (HDL) design entities or other data structures conforming
to and/or compatible with lower-level HDL design languages such as
Verilog and VHDL, and/or higher level design languages such as C or
C++.
[0044] Design process 1610 preferably employs and incorporates
hardware and/or software modules for synthesizing, translating, or
otherwise processing a design/simulation functional equivalent of
the components, circuits, devices, or logic structures shown in
FIGS. 1-13 to generate a Netlist 1680 which may contain design
structures such as design structure 1620. Netlist 1680 may
comprise, for example, compiled or otherwise processed data
structures representing a list of wires, discrete components, logic
gates, control circuits, I/O devices, models, etc. that describes
the connections to other elements and circuits in an integrated
circuit design. Netlist 1680 may be synthesized using an iterative
process in which netlist 1680 is resynthesized one or more times
depending on design specifications and parameters for the device.
As with other design structure types described herein, netlist 1680
may be recorded on a machine-readable data storage medium or
programmed into a programmable gate array. The medium may be a
non-volatile storage medium such as a magnetic or optical disk
drive, a programmable gate array, a compact flash, or other flash
memory. Additionally, or in the alternative, the medium may be a
system or cache memory, buffer space, or electrically or optically
conductive devices and materials on which data packets may be
transmitted and intermediately stored via the Internet, or other
networking suitable means.
[0045] Design process 1610 may include using a variety of inputs;
for example, inputs from library elements 1630 which may house a
set of commonly used elements, circuits, and devices, including
models, layouts, and symbolic representations, for a given
manufacturing technology (e.g., different technology nodes, 32 nm,
45 nm, 90 nm, etc.), design specifications 1640, characterization
data 1650, verification data 1660, design rules 1670, and test data
files 1685 (which may include test patterns and other testing
information). Design process 1610 may further include, for example,
standard circuit design processes such as timing analysis,
verification, design rule checking, place and route operations,
etc. One of ordinary skill in the art of integrated circuit design
can appreciate the extent of possible electronic design automation
tools and applications used in design process 1610 without
deviating from the scope and spirit of the invention. The design
structure of the invention is not limited to any specific design
flow.
[0046] Design process 1610 preferably translates an embodiment of
the invention as shown in FIGS. 1-13, along with any additional
integrated circuit design or data (if applicable), into a second
design structure 1690. Design structure 1690 resides on a storage
medium in a data format used for the exchange of layout data of
integrated circuits (e.g. information stored in a GDSII (GDS2),
GL1, OASIS, or any other suitable format for storing such design
structures). Design structure 1690 may comprise information such
as, for example, test data files, design content files,
manufacturing data, layout parameters, wires, levels of metal,
vias, shapes, data for routing through the manufacturing line, and
any other data required by a semiconductor manufacturer to produce
an embodiment of the invention as described above with reference to
FIGS. 1-13. Design structure 1690 may then proceed to a stage 1695
where, for example, design structure 1690: proceeds to tape-out, is
released to manufacturing, is released to a mask house, is sent to
another design house, is sent back to the customer, etc.
[0047] Embodiments of the present invention utilize a selective
deposition process involving titanium and aluminum to allow
formation of two adjacent transistors with different fill metals
and different workfunction metals, enabling different threshold
voltages in the adjacent transistors.
[0048] Although the invention has been shown and described with
respect to a certain preferred embodiment or embodiments, certain
equivalent alterations and modifications will occur to others
skilled in the art upon the reading and understanding of this
specification and the annexed drawings. In particular regard to the
various functions performed by the above described components
(assemblies, devices, circuits, etc.) the terms (including a
reference to a "means") used to describe such components are
intended to correspond, unless otherwise indicated, to any
component which performs the specified function of the described
component (i.e., that is functionally equivalent), even though not
structurally equivalent to the disclosed structure which performs
the function in the herein illustrated exemplary embodiments of the
invention. In addition, while a particular feature of the invention
may have been disclosed with respect to only one of several
embodiments, such feature may be combined with one or more features
of the other embodiments as may be desired and advantageous for any
given or particular application.
* * * * *