U.S. patent application number 13/615526 was filed with the patent office on 2014-03-13 for semiconductor memory array structure.
The applicant listed for this patent is Chin-Piao Chang, Jen-Jui Huang, Jeng-Ping Lin, Shian-Jyh Lin. Invention is credited to Chin-Piao Chang, Jen-Jui Huang, Jeng-Ping Lin, Shian-Jyh Lin.
Application Number | 20140070359 13/615526 |
Document ID | / |
Family ID | 50232423 |
Filed Date | 2014-03-13 |
United States Patent
Application |
20140070359 |
Kind Code |
A1 |
Lin; Shian-Jyh ; et
al. |
March 13, 2014 |
SEMICONDUCTOR MEMORY ARRAY STRUCTURE
Abstract
A memory array includes a rhomboid-shaped AA region surrounded
by a first and second STI structures. The first STI structure
extends along a first direction on the longer sides of the
rhomboid-shaped AA region and has a depth d1. The second STI
structure extends along the second direction on the shorter sides
of the rhomboid-shaped AA region and has two depths: d2 and d3,
wherein d1 and d2 are shallower than d3.
Inventors: |
Lin; Shian-Jyh; (New Taipei
City, TW) ; Lin; Jeng-Ping; (Taoyuan County, TW)
; Chang; Chin-Piao; (New Taipei City, TW) ; Huang;
Jen-Jui; (Taoyuan County, TW) |
|
Applicant: |
Name |
City |
State |
Country |
Type |
Lin; Shian-Jyh
Lin; Jeng-Ping
Chang; Chin-Piao
Huang; Jen-Jui |
New Taipei City
Taoyuan County
New Taipei City
Taoyuan County |
|
TW
TW
TW
TW |
|
|
Family ID: |
50232423 |
Appl. No.: |
13/615526 |
Filed: |
September 13, 2012 |
Current U.S.
Class: |
257/499 ;
257/E27.001 |
Current CPC
Class: |
H01L 21/3081 20130101;
H01L 21/76224 20130101 |
Class at
Publication: |
257/499 ;
257/E27.001 |
International
Class: |
H01L 27/00 20060101
H01L027/00 |
Claims
1. A memory array, comprising: a plurality of rhomboid-shaped
active area (AA) regions in a substrate, each of the
rhomboid-shaped AA regions having a pair of longer sides and a pair
of shorter sides; a first shallow trench isolation (STI) structure
extending along a first direction on the longer sides of the
rhomboid-shaped AA region, wherein the first STI structure has a
depth d1; and a second STI structure extending along a second
direction on the shorter sides of the rhomboid-shaped AA region,
wherein the second STI structure has two depths: d2 and d3, the
depth d3 is the depth of overlapping regions where the first STI
structure intersects the second STI structure, the depths d1, d2
and d3 are different, and the depths d1 and d2 are shallower than
d3.
2. (canceled)
3. The memory array according to claim 1 wherein the second STI
structure has the depth d2 in a sub-region located between the
overlapping regions.
4. The memory array according to claim 1 wherein the depth d1 and
the depth d2 range between 2300.about.2600 angstroms.
5. The memory array according to claim 1 wherein the depth d3
ranges between 2600-2800 angstroms.
6. The memory array according to claim 1 wherein the substrate is a
silicon substrate.
7. The memory array according to claim 1 wherein the first
direction is not perpendicular to the second direction.
Description
BACKGROUND OF THE INVENTION
[0001] 1. Field of the Invention
[0002] The present invention relates to a semiconductor memory
array structure, and more particularly to a memory array having
independent depth-controlled shallow trench isolation, and methods
of manufacturing the same.
[0003] 2. Description of the Prior Art
[0004] As well known in the art, a shallow trench isolation
structure comprises a dielectric material that laterally surrounds
active areas (AA) of a semiconductor substrate comprising a
semiconductor material, which is typically silicon. Typically, the
shallow trench isolation structure is formed by first patterning a
shallow trench that laterally surrounds the active area, followed
by deposition of a dielectric material into the shallow trench and
a subsequent planarization of the deposited dielectric material.
The dielectric material is typically removed from above the active
areas during the planarization step, and the remaining portions of
the dielectric material within the shallow trench constitute the
shallow trench isolation structure.
[0005] Conventionally, the aforesaid shallow trench that laterally
surrounds the active area is formed by using a single lithographic
process and a single dry etching process. That is, only one
photomask (i.e., AA photomask) that defines the AA pattern thereon
is used during the lithographic process, and the shallow trench has
substantially the same depth. However, due to the line shortening
effect and/or other optical interference effects, the AA pattern
transferred to the photoresist or the underlying substrate has an
oval-like shape that has a smaller surface area than the original
pattern that defined on the AA photomask. This adversely affects
the process window and the electric performance of the
semiconductor device fabricated in the AA regions.
SUMMARY OF THE INVENTION
[0006] In one aspect, the present invention provides a memory array
including a plurality of rhomboid-shaped active area (AA) regions
in a substrate, each of the rhomboid-shaped AA regions having a
pair of longer sides and a pair of shorter sides; a first shallow
trench isolation (STI) structure extending along a first direction
on the longer sides of the rhomboid-shaped AA region, wherein the
first STI structure has a depth d1; and a second STI structure
extending along the second direction on the shorter sides of the
rhomboid-shaped AA region, wherein the second STI structure has two
depths: d2 and d3, wherein d1 and d2 are shallower than d3.
[0007] These and other objectives of the present invention will no
doubt become obvious to those of ordinary skill in the art after
reading the following detailed description of the preferred
embodiment that is illustrated in the various figures and
drawings.
BRIEF DESCRIPTION OF THE DRAWINGS
[0008] The accompanying drawings are included to provide a further
understanding of the embodiments, and are incorporated in and
constitute a part of this specification. The drawings illustrate
some of the embodiments and, together with the description, serve
to explain their principles. In the drawings:
[0009] FIG. 1A is a schematic top view of a portion of a memory
array after a patterned first hard mask defining a plurality of
active area (AA) lines are formed on a substrate according to one
embodiment of this invention;
[0010] FIG. 1B and FIG. 2 are cross-sectional views taken along
line I-I' in FIG. 1A;
[0011] FIG. 3A is a schematic top view showing the memory array
after the second STI pattern extending along the second direction
is defined in the photoresist layer;
[0012] FIG. 3B and FIG. 3C are cross-sectional views taken along
line II-II' and III-III' in FIG. 3A respectively;
[0013] FIG. 4A and FIG. 4B are cross-sectional views taken along
line II-II' and III-III' in FIG. 3A respectively, after the
anisotropic dry etching process is performed;
[0014] FIG. 5A, FIG. 5B and FIG. 5C are cross-sectional views taken
along lines I-I', II-II' and III-III' in FIG. 3A respectively,
after the remaining photoresist layer, the ARC layer, and the
second hard mask are removed;
[0015] FIG. 6A, FIG. 6B and FIG. 6C are cross-sectional views taken
along lines I-I', II-II' and III-III' in FIG. 3A respectively,
after STI etching; and
[0016] FIG. 7 shows a top view of the memory array including the
rhomboid-shaped AA regions and the first and second STI structures
with independent depth control.
[0017] It should be noted that all the figures are diagrammatic.
Relative dimensions and proportions of parts of the drawings are
exaggerated or reduced in size, for the sake of clarity and
convenience. The same reference signs are generally used to refer
to corresponding or similar features in modified and different
embodiments.
DETAILED DESCRIPTION
[0018] In the following description, numerous specific details are
given to provide a thorough understanding of the invention. It
will, however, be apparent to one skilled in the art that the
invention may be practiced without these specific details.
Furthermore, some well-known system configurations and process
steps are not disclosed in detail, as these should be well-known to
those skilled in the art.
[0019] Likewise, the drawings showing embodiments of the apparatus
are semi-diagrammatic and not to scale and some dimensions are
exaggerated in the figures for clarity of presentation. Also, where
multiple embodiments are disclosed and described as having some
features in common, like or similar features will usually be
described with like reference numerals for ease of illustration and
description thereof.
[0020] Please refer to FIG. 1A, FIG. 1B and FIG. 2. FIG. 1A is a
schematic top view of a portion of a memory array after a patterned
first hard mask defining a plurality of active area (AA) lines are
formed on a substrate according to one embodiment of this
invention. FIG. 1B and FIG. 2 are cross-sectional views taken along
line I-I' in FIG. 1A. As shown in FIG. 1A and FIG. 1B, first, a
substrate 10 such as a silicon substrate is provided. A silicon
oxide pad layer 12 and a silicon nitride pad layer 14 are deposited
on a main surface 10a of the substrate 10. A patterned first hard
mask 16 such as silicon oxide is formed on the silicon nitride pad
layer 14 by using a first lithographic process. The patterned first
hard mask 16 defines a plurality of parallel AA lines extending
along a first direction. The patterned first hard mask 16 includes
a plurality of line-shaped trench patterns 116 that defines a first
shallow trench isolation (STI). According to the embodiment, the
thickness of the patterned first hard mask 16 may range between
800-1200 angstroms. As can be seen in FIG. 1B, preferably, each of
the trench patterns 116 has a tapered sidewall.
[0021] Subsequently, as shown in FIG. 2, a second hard mask 20 such
as a carbon-containing material and an anti-reflection coating
(ARC) layer 22 such as silicon oxynitride are depositing on the
substrate 10 in a blanket manner. The second hard mask 20 fills the
trenches 116 and covers the patterned first hard mask 16. A
photoresist layer 24 is then coated on the ARC layer 22. According
to the embodiment, the thickness of the second hard mask 20 may
range between 1000-4000 angstroms.
[0022] Please refer to FIG. 3A-3C. FIG. 3A is a schematic top view
showing the memory array after the second STI pattern extending
along the second direction is defined in the photoresist layer.
FIG. 3B and FIG. 3C are cross-sectional views taken along line
II-II' and III-III' in FIG. 3A respectively. As shown in FIG.
3A-3C, a second lithographic process is carried out to form a
plurality of parallel trench patterns 124 extending along a second
direction in the photoresist layer 24. As can be best seen in FIG.
3A, the parallel trench patterns 124 intersect the underlying
trench patterns 116 at the overlapping regions 130 from a top view,
thereby defining a plurality of rhomboid-shaped AA patterns 200.
Each rhomboid-shaped AA pattern 200 includes two opposite longer
sides 200a and two opposite shorter sides 200b. Along the second
direction, a plurality of sub-regions 132 are provided between the
overlapping regions 130 on either shorter side 200b of the
rhomboid-shaped AA pattern 200. According to the embodiment, the
first direction is not perpendicular to the second direction, that
is, an acute angle may exist between the first and second
directions. Along the second direction, a second STI intersecting
the first STI will be formed into the substrate 10 in the
subsequent process steps. In FIG. 3A, the widths of regions 130,
132, 116 and 124 are indicated respectively by w1, w2, w3 and w4,
and the first and second directions are also indicated.
[0023] As shown in FIG. 4A and FIG. 4B, using the patterned
photoresist layer 24 as a dry etching hard mask, an anisotropic dry
etching process is then performed to etch the ARC layer 22, the
second hard mask 20, the first hard mask 16, and a portion of the
silicon nitride pad layer 14 through the trench patterns 124,
thereby forming trench patterns 134 in the second hard mask 20 and
the first hard mask 16. According to the embodiment, the amount of
the silicon nitride pad layer 14 removed from the overlapping
regions 130 is more than that removed from the sub-regions 132. For
example, the silicon nitride pad layer 14 may be completely removed
from the trench patterns 124 to expose the silicon oxide pad layer
12, while in the overlapping regions 130 merely a small portion of
the silicon nitride pad layer 14 is removed. Preferably, each of
the trench patterns 134 has a tapered sidewall. Alternatively,
according to another embodiment, the silicon nitride pad layer 14
may be completely removed from the trench patterns 124 to expose
the silicon oxide pad layer 12 at the area 130. The cross section
of this area 130 is shown in FIG. 4A. For the nitride loss at area
132, it has merely a small amount of loss shown in FIG. 4B.
Preferably, each of the trench patterns 134 has a tapered
sidewall.
[0024] FIG. 5A, FIG. 5B and FIG. 5C are cross-sectional views taken
along lines I-I', II-II' and III-III' in FIG. 3A respectively. As
shown in FIG. 5A, FIG. 5B and FIG. 5C, after the anisotropic dry
etching process is completed, the remaining photoresist layer 24,
the ARC layer 22, and the second hard mask 20 are removed to reveal
the patterned first hard mask 16. The patterned first hard mask 16
in FIG. 5A decides the width of each of the AA regions to be formed
in the substrate 10. As can be best seen in FIG. 5B, the patterned
first hard mask 16 are cut through on both shorter side 200b of the
rhomboid-shaped AA pattern 200. Preferably, each of the trench
patterns 134' on both shorter side 200b of the rhomboid-shaped AA
pattern 200 has a tapered sidewall. The trench patterns 134' decide
the length of the each of the AA regions to be formed in the
substrate 10.
[0025] FIG. 6A, FIG. 6B and FIG. 6C are cross-sectional views taken
along lines I-I', II-II' and III-III' in FIG. 3A respectively. As
shown in FIG. 6A, FIG. 6B and FIG. 6C, using the patterned first
hard mask 16 as a dry etching hard mask, an anisotropic dry etching
process is performed to etch the silicon nitride pad layer 14, the
silicon oxide pad layer 12 and the substrate 10 through the trench
patterns 116 and 134', thereby forming first STI structure 302
extending in the first direction and second STI structure 304
extending along the second direction, and rhomboid-shaped AA
regions 400. According to the embodiment, the first STI structure
302 has a depth d1 (FIG. 6A), the second STI structure 304 has two
depths: d2 and d3 (FIG. 6B), wherein d1 and d2 are shallower than
d3. According to the embodiment, the depth d1 and d2 may range
between 2300.about.2600 angstroms, while the depth d3 may range
between 2600-2800 angstroms. Subsequently, a trench fill material
(not shown) may be filled into the first and second STI structures
302 and 304 to form electric isolation. The width w1 of the
overlapping region 130 and width w4 of the trench pattern 124, as
shown in FIG. 3A, substantially determine the depth d1 and d2 shown
in FIG. 6A and 6B. The depth d1 is not necessarily shallower than
d2.
[0026] FIG. 7 shows a top view of the memory array 1 including a
plurality of rhomboid-shaped AA regions 400 and the first and
second STI structures 302 and 304 surrounding each of the
rhomboid-shaped AA regions 400. As shown in FIG. 7, since the
second STI structure 304 provides a deep trench depth along the
second direction (i.e., word line direction), the electric
isolation between adjacent word lines (WL) can be significantly
improved. The WL-WL coupling effect can be reduced.
[0027] Those skilled in the art will readily observe that numerous
modifications and alterations of the device and method may be made
while retaining the teachings of the invention. Accordingly, the
above disclosure should be construed as limited only by the metes
and bounds of the appended claims.
* * * * *