U.S. patent application number 14/076706 was filed with the patent office on 2014-03-06 for multi-chip module and method of manufacture.
This patent application is currently assigned to Spansion LLC. The applicant listed for this patent is Spansion LLC. Invention is credited to Mohamed Suhaizal Bin Abu-Hassan, Yin Lye FOONG, Cheng Sim Kee, Lay Hong Lee.
Application Number | 20140061895 14/076706 |
Document ID | / |
Family ID | 36677176 |
Filed Date | 2014-03-06 |
United States Patent
Application |
20140061895 |
Kind Code |
A1 |
FOONG; Yin Lye ; et
al. |
March 6, 2014 |
Multi-Chip Module and Method of Manufacture
Abstract
A multi-chip module and a method for manufacturing the
multi-chip module that mitigates wire breakage. A first
semiconductor chip is mounted and wirebonded to a support
substrate. A spacer is coupled to the first semiconductor chip. A
support material is disposed on the spacer and a second
semiconductor chip is positioned on the support material. The
second semiconductor chip is pressed into the support material
squeezing it into a region adjacent the spacer and between the
first and second semiconductor chips. Alternatively, the support
material is disposed on the first semiconductor chip and a die
attach material is disposed on the spacer. The second semiconductor
chip is pressed into the die attach material and the support
material, squeezing a portion of the support material over the
spacer edges. Wirebonds are formed between the support substrate
and the first and second semiconductor chips.
Inventors: |
FOONG; Yin Lye; (Milpitas,
CA) ; Kee; Cheng Sim; (Bayan Lepas, MY) ; Lee;
Lay Hong; (Penang, MY) ; Abu-Hassan; Mohamed Suhaizal
Bin; (Pendang, MY) |
|
Applicant: |
Name |
City |
State |
Country |
Type |
Spansion LLC |
Sunnvyale |
CA |
US |
|
|
Assignee: |
Spansion LLC
Sunnvyale
CA
|
Family ID: |
36677176 |
Appl. No.: |
14/076706 |
Filed: |
November 11, 2013 |
Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
|
|
11125396 |
May 4, 2005 |
8586413 |
|
|
14076706 |
|
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|
Current U.S.
Class: |
257/723 |
Current CPC
Class: |
H01L 2225/0651 20130101;
H01L 2224/48227 20130101; H01L 2924/3025 20130101; H01L 2224/48091
20130101; H01L 2225/06575 20130101; H01L 25/065 20130101; H01L
2924/15311 20130101; H01L 25/0657 20130101; H01L 2224/48091
20130101; H01L 2924/01087 20130101; H01L 2924/09701 20130101; H01L
2924/15184 20130101; H01L 25/50 20130101; H01L 2924/00014 20130101;
H01L 2924/16152 20130101; H01L 2225/06593 20130101 |
Class at
Publication: |
257/723 |
International
Class: |
H01L 25/065 20060101
H01L025/065 |
Claims
1. A multi-chip module, comprising: a support substrate having a
chip receiving area and a plurality of substrate bonding pads; a
first semiconductor chip having a first plurality of chip bonding
pads, the first semiconductor chip mounted to the chip receiving
area; a spacer having first and second opposing edges, the spacer
coupled to the first semiconductor chip; a support material in
contact with the spacer; and a second semiconductor chip having a
second plurality of chip bonding pads, and coupled to the spacer
using a die attach material, wherein a portion of the support
material is positioned between, and in contact with, the first
semiconductor chip and the second semiconductor chip.
2. The multi-chip module of claim 1, wherein the support material
substantially fills the region between the first and second
semiconductor chips.
3. The multi-chip module of claim 1, wherein the support material
is disposed on the spacer.
4. The multi-chip module of claim 1, wherein the die attach
material comprises at least one of silver filled epoxy, silica
filled epoxy blend, or an epoxy film filled with an organic
material.
5. The multi-chip module of claim 1, wherein the spacer comprises
dielectric material or a semiconductor material.
6. The multi-chip module of claim 5, wherein the semiconductor
material is silicon or a third semiconductor chip.
7. The multi-chip module of claim 1, wherein the spacer has a
square shape, a rectangular shape, a round shape, or a triangular
shape.
8. The multi-chip module of claim 1, wherein the support substrate
is a ball grid array (BOA) substrate.
9. The multi-chip module of claim 1, wherein the support substrate
is one of a pin grid array (PGA) substrate, a ceramic substrate, or
a printed circuit board,
10. The multi-chip module of claim 1, wherein the support material
is a thermal conductor and an electric insulator.
11. The multi-chip module of claim 1, wherein the support material
is an epoxy paste.
12. The multi-chip module of claim 11, wherein the epoxy paste
comprises an epoxy material filled with polytetrafluoroethylene, a
nonconductive paste filled with an inorganic material, or a
bismaleimide material filled with polytetrafluoroethylene.
13. The multi-chip module of claim 12, wherein the nonconductive
paste includes silica.
14. The multi-chip module of claim 1, wherein the support material
has a pre-cured shape of a double-Y shape, a dogbone shape, a
circular shape, a triangular shape, a quadrilateral shape, a
pentagonal shape, or another polygonal shape.
15. The multi-chip module of claim 1, further comprising: a first
set of interconnect wires formed to electrically connect one or
more of the first plurality of chip bonding pads to a first portion
of the plurality of substrate bonding pads, and a second set of
interconnect wires formed to electrically connect one or more of
the second plurality of chip bonding pads to a second portion of
the plurality of substrate bonding pads.
16. The multi-chip module of claim 15, further comprising: a
protective covering formed over the second semiconductor chip, the
first semiconductor chip, the support substrate, the first set of
interconnect wires and the second interconnect wires.
17. The multi-chip module of claim 16, wherein the protective
covering includes a lid secured to the support substrate using a
lid attach material.
18. The multichip module of claim 1, wherein the support substrate
comprises a resin.
19. The multi-chip module of claim 18, wherein the resin comprises
one of an epoxy resin, a polyimide resin, a triazine resin, a
phenolic resin or a bismaleimidetriazine (BT) resin.
20. The multi-chip module of claim 1, wherein the support substrate
comprises an epoxy-glass composite, FR-4, or a ceramic.
Description
CROSS REFERENCE TO RELATED APPLICATIONS
[0001] This application is a divisional of U.S. Non-Provisional
Application No. 11/125,396, filed May 4, 2005, to issue as U.S.
Pat. No. 8,586,413, which is incorporated herein by reference in
its entirety.
FIELD OF THE INVENTION
[0002] The present invention relates, in general, to semiconductor
components and, more particularly, to semiconductor components
comprising multi-chip modules.
BACKGROUND OF THE INVENTION
[0003] The desire for faster, cheaper, and more efficient
semiconductor components has motivated semiconductor component
manufacturers to shrink the sizes of the devices fabricated in a
semiconductor chip and place multiple semiconductor chips in a
single package typically referred to as a multi-chip module. The
semiconductor chips in a multi-chip module can be placed either in
a horizontal orientation, i.e., beside each other, or in a vertical
orientation, i.e., vertically stacked on top of each other. In a
conventional vertically stacked multi-chip module, a first
semiconductor chip is attached to a circuit board by adhesive
bonding followed by wirebonding bonding pads located on the
semiconductor chip to corresponding bonding pads located on the
circuit board. A spacer is formed on or attached to the first
semiconductor chip and a second semiconductor chip is attached to
the spacer. Then bonding pads located on the second semiconductor
chip are coupled to corresponding bonding pads located on the
circuit board using, for example, a wirebonding process. The spacer
must be smaller than the first semiconductor chip to accommodate
the wirebonding process. What's more, the spacer is typically
smaller than the second semiconductor chip. A drawback with this
type of structure is that the portions of the second semiconductor
chip that overhang the spacer are pliable or springy. Thus, when
the bonding pads located on the overhanging portion of the second
semiconductor chip are wirebonded to the corresponding bonding pads
located on the circuit board, the pliability of the overhanging
portions of the second semiconductor chip weakens the bonds formed
to bonding pads on the second semiconductor chip. This bond
weakening causes catastrophic device failure.
[0004] Accordingly, it would be advantageous to have a multi-chip
module and a method for manufacturing the multi-chip module that
does not degrade the integrity of the bonds formed to the bonding
pads. It would be of further advantage for the method and structure
to be cost efficient and suitable for integration with a variety of
multi-chip module processes.
SUMMARY OF THE INVENTION
[0005] The present invention satisfies the foregoing need by
providing a multi-chip module and a method for manufacturing the
multi-chip module. In accordance with one embodiment, the present
invention includes providing a support substrate having first and
second major surfaces, wherein the support substrate has a chip
receiving area and a plurality of bonding pads. A first
semiconductor chip is coupled to the chip receiving area, wherein
the first semiconductor chip has a plurality of bonding pads. A
first bonding pad of the first semiconductor chip is coupled to a
first bonding pad of the support substrate. A spacer is coupled to
a portion of the first semiconductor chip. A support material is
disposed on at least one of the spacer or the first semiconductor
chip. A second semiconductor chip is positioned on the support
material, wherein the second semiconductor chip has a first major
surface and a plurality of bonding pads. A first bonding pad of the
second semiconductor chip is coupled to a second bonding pad of the
support substrate.
[0006] In accordance with another embodiment, the present invention
comprises a method for manufacturing a multi-chip module that
includes providing a support substrate having, a first
semiconductor chip mounted to a chip or die receiving area on the
support substrate. The support substrate has a plurality of bonding
pads and the first semiconductor chip has a plurality of bonding
pads. A spacer is coupled to the first semiconductor chip and a
support material is disposed on one of the spacer or the first
semiconductor chip. A semiconductor chip is coupled to the spacer
such that the support material, becomes positioned between the
first semiconductor chip and the second semiconductor chip thereby
providing support for the second semiconductor chip.
[0007] In accordance with yet another embodiment, the present
invention comprises a multi-chip module having a support substrate
that has a chip receiving area and a plurality of bonding pads. A
first semiconductor chip having a plurality of bonding pads is
mounted to the chip receiving area. A spacer having first and
second opposing edges is coupled to the first semiconductor chip. A
support material is in contact with the spacer. A second
semiconductor chip is coupled to the spacer, wherein a portion of
the support material is positioned between the first semiconductor
chip and the second semiconductor chip.
BRIEF DESCRIPTION OF THE DRAWINGS
[0008] The present invention will be better understood from a
reading of the following detailed description, taken in conjunction
with the accompanying drawing figures, in which like reference
numbers designate like elements and in which:
[0009] FIG. 1 is a cross-sectional side view of a multi-chip module
at a beginning stage of manufacture in accordance with an
embodiment of the present invention;
[0010] FIG. 2 is a cross-sectional side view of the multi-chip
module of FIG. 1 at a later stage of manufacture and taken along
section line 2-2 of FIG. 3;
[0011] FIG. 3 is a top view of the multi-chip module of FIG. 2;
[0012] FIG. 4 is a cross-sectional side view of the multi-chip
module of FIGS. 2 and 3 at a later stage of manufacture;
[0013] FIG. 5 is a cross-sectional side view of the multi-chip
module of FIG. 4 at a later stage of manufacture;
[0014] FIG. 6 is a cross-sectional side view of a multi-chip module
at a beginning stage of manufacture in accordance with another
embodiment of the present invention and taken along section line
6-6 of FIG. 7;
[0015] FIG. 7 is a top view of the multi-chip module of FIG. 6;
[0016] FIG. 8 is a cross-sectional side view of the multi-chip
module of FIGS. 6 and 7 at a later stage of manufacture; and
[0017] FIG. 9 is a cross-sectional side view of the multi-chip
module of FIG. 8 at a later stage of manufacture.
DETAILED DESCRIPTION
[0018] Generally, the present invention provides a multi-chip
module and a method for manufacturing the multi-chip module,
wherein the semiconductor chips of the multi-chip module are
vertically stacked. In vertically stacking the semiconductor chips
of a multi-chip module, a spacer is inserted between the
semiconductor chips to allow clearance for the wirebonds. A portion
of the semiconductor chip positioned above the spacer overhangs the
edges of the spacer. The portions of a semiconductor chip
overhanging the spacer are pliable. Although the pliability
increases the fragility of semiconductor chips in general, the
increased fragility is more pronounced in semiconductor chips
having thicknesses of less than about 0.6 millimeters (mm). This
pliability allows the semiconductor chip to vibrate during the
wirebonding process, which breaks the wires being bonded to bonding
pads on the semiconductor chip. In accordance with the present
invention, the vibration is mitigated by forming a support material
under the portion of the second semiconductor chip that overhangs
the spacer. The support material provides additional rigidity to
the semiconductor chip, which decreases the vibrations of the
overhanging portions of the semiconductor chip and improves the
reliability of the wirebond.
[0019] FIG. 1 is cross-sectional side view of a portion of a
multi-chip module 10 at an intermediate stage of manufacture in
accordance with an embodiment of the present invention. What is
shown in FIG. 1 is a Ball Grid Array (BGA) support structure 12
having top and bottom surfaces 14 and 16, respectively. BGA support
substrate 12 is formed from a resin such as an epoxy resin, a
polyimide resin, a triazine resin, or a phenolic resin. Preferably,
the resin material of BGA support substrate 12 is
bisrnaleimidetriazine (BT) resin. Other suitable materials for
support substrate 12 include epoxy-glass composites, FR-4,
ceramics, and the like. It should be understood that substrate 12
is not limited to being a BGA substrate but may also be a Pin Grid
Array (PGA) substrate, a ceramic substrate, a printed circuit
board, or the like. Bonding pads 18A and 18B and bonding pads 20A
and 20B are formed on top surface 14. A plurality of bonding pads
22 are formed on bottom surface 16. Bonding pads 18A, 18B, 20A, and
20B are electrically connected to bonding pads 22B, 22C, 22A, and
22D, respectively, on bottom surface 16 through electrical
interconnects 28, 30, 26, and 32 that extend through BGA support
substrate 12. For the sake of clarity, only four interconnects are
shown as extending through BGA support substrate 12 in FIG. 1.
However, it should be understood that all or nearly all of the
bonding pads on the top surface of a support substrate such as
support substrate are coupled to bonding pads on the bottom surface
of the support substrate. It should be further understood that
bonding pads 18A and 18B are two of a plurality of bonding pads 18
that are formed on top surface 14. Similarly, bonding pads 20A and
20B are two of a plurality of bonding pads 20 that are formed on
top surface 14. (The pluralities of bonding pads 18 and 20 are
further illustrated and discussed with reference to in FIG. 3).
Solder balls 34 are attached to bonding pads 22.
[0020] Still referring to FIG. 1, a die attach material 36 is
dispensed on a semiconductor chip receiving area 38 and a
semiconductor chip or die 40 is placed on die attach material 36.
Semiconductor chip 40 has a bottom surface 42 and a top surface 44.
A plurality of bonding pads 46 is disposed around the periphery of
top surface 44. Bottom surface 42 of a semiconductor chip or die 40
is placed on die attach material 36. Although only bonding pads 46A
and 46B are shown, it should be understood that bonding pads 46A
and 46B are part of plurality of bonding pads 46, which plurality
is further shown and described with reference to FIG. 3. The
combination of substrate 12, semiconductor chip 40, and die attach
material 36 is placed in a curing oven and die attach material 36
is cured. By way of example, die attach material 36 is cured by
heating to a temperature ranging from about 100 degrees Celsius
(.degree. C.) to about 175.degree. C. for a time ranging from about
5 minutes to about 60 minutes. Suitable die attach materials
include silver filled epoxy, silica filled epoxy blend, an epoxy
film filled with an organic material, and the like.
[0021] After curing die attach material 36, a die attach material
48 is disposed on a central portion of top surface 44 and a spacer
50 is placed on die attach material 48. Spacer 50 has top and
bottom surfaces 52 and 54, respectively, and edges 53 and 55.
Spacer 50 may be a dielectric material, a semiconductor material
such as, for example, silicon, another semiconductor chip, or the
like. Although spacer 50 is shown as having a square shape, its
shape is not a limitation of the present invention. For example,
spacer 50 have a rectangular shape, a round shape, a triangular
shape, etc. Die attach material 48 is cured by heating it to a
temperature ranging from about 100.degree. C. to about 175.degree.
C. for a time ranging from about 5 minutes to about 60 minutes.
Suitable die attach materials include silver filled epoxy, silica
filled epoxy blend, an epoxy film filled with an organic material,
and the like.
[0022] Still referring to FIG. 1, bonding pads 46 on semiconductor
chip 40 are electrically connected to corresponding bonding pads 18
on BGA substrate 12 using, for example, a wirebonding process. What
is shown in FIG. 1 is bonding pad 46A coupled to bonding pad 18A by
an interconnect wire 56A and bonding pad 46B coupled to bonding pad
18B by an interconnect wire 56B. Although only two interconnect
wires are shown in FIG. 1, it should be understood that typically
plurality of interconnects 56 comprises more than two interconnect
wires. (The plurality of interconnect wires 56 is further
illustrated and discussed with reference to in FIG. 3).
[0023] Referring now to FIG. 2, a cross-sectional side view of
multi-chip module 10 further along in manufacture is illustrated.
What is shown in FIG. 2 is a support material 60 disposed on
surface 44 of semiconductor chip 40 and a die attach material 62
disposed on surface 52 of spacer 50. Preferably, support material
60 is an epoxy paste that is a thermal conductor and an electrical
insulator. Examples of the epoxy paste comprising support material
60 include an epoxy material filled with polytetrafluoroethylene
sold under the trademark Teflon (Teflon is a trademark of E.I.
DuPont De Demours and Company Corp.), a nonconductive paste (e.g.,
silica) filled with an inorganic material, bismaleimide material
filled with polytetrafluoroethylene sold under the trademark
Teflon, and the like. Suitable materials for die attach material 62
include silver filled epoxy, silica filled epoxy blend, an epoxy
film filled with an organic material, and the like.
[0024] Referring now to FIG. 3, a top view of multi-chip module 10
is shown, wherein the top view illustrates the same stage of
manufacture as that shown in FIG. 2. In other words, FIG. 2 is a
cross-sectional side view taken along section line 2-2 of FIG. 3.
FIG. 3 further illustrates the plurality of bonding pads 18, the
plurality of bonding pads 20, the plurality of bonding pads 46, the
plurality of wire interconnects 56, as well as the individual
bonding pads 18A, 18B, 20A, and 20B and the individual
interconnects 56A and 56B shown in FIG. 2. In addition, FIG. 3
illustrates support material 60 and die attach material 62.
Although support material 60 is shown as having a double-Y or
dogbone shape, this is not a limitation of the present invention.
For example, support material 60 can be formed to have circular
shapes, triangular shapes, quadrilateral shapes, pentagonal shapes,
as well as other polygonal shapes.
[0025] Retelling now to FIG. 4, a cross-sectional side view of
multi-chip module 10 further along in manufacture is illustrated. A
semiconductor chip 64 is placed on die attach material 62. More
particularly, semiconductor chip 64 has a backside 66 that is
placed on die attach material 62 and a front side 68 that has a
plurality of bonding pads 70 formed thereon. Pressure is applied to
semiconductor chip 64 to position it in die attach material 62 and
to squeeze support material 60 in a lateral direction so that it
substantially fills the region between surfaces 44 and 66. In this
region, peripheral portions 65 of semiconductor chip 64 overhang
spacer 50. Support material 60 and die attach material 62 are cured
by being heated to a temperature ranging from about 100.degree. C.
to about 175.degree. C. for a time ranging from about 5 minutes to
about 60 minutes. Because support material 60 substantially fills
the region between surfaces 44 and 66, the peripheral portions 65
of semiconductor chip 64 do not freely overhang edges 53 and 54,
but are supported by support material 60. Thus, peripheral portions
65 do not bounce significantly during a subsequent wirebonding
step. An advantage of placing support material 60 between surfaces
44 and 66 is that it improves the manufacturability and reliability
of wirebonds formed in multi-chip modules,
[0026] A plurality of bonding pads 70 are electrically connected to
corresponding bonding pads of plurality of bonding pads 20 using,
for example, a wirebonding process. More particularly, bonding pad
70A is electrically connected to bonding pad 20A by an interconnect
wire 74A and bonding pad 70B is electrically connected to bonding
pad 20B by an interconnect wire 74B. Interconnect wires 74A and 74B
are two interconnect wires of plurality of interconnect wires
74.
[0027] Referring now to FIG, 5, a protective covering 78 is formed
over semiconductor chip 64, interconnect wires 56 and 74, and 130A
substrate 12. The protective covering illustrated in FIG. 5 is a
glob top material. However, it should be understood that the type
of protective material is not limited to being a glob top material.
For example, protective covering 78 may be a lid or cap.
[0028] FIG. 6 illustrates a multi-chip module 100 in accordance
with another embodiment of the present invention. The beginning
steps in the manufacture of multi chip module 100 are the same as
those for the manufacture of multi-chip module 10.
[0029] Thus, the description of FIG. 6 continues from that of FIG.
1. A support material 102 is disposed on a central portion of
spacer surface 52. Preferably, support material 102 is an epoxy
paste that is thermally conductive and electrical non-conductive,
i.e. it is an electrical insulator. Suitable epoxy pastes for
support material include epoxy material filled with
polytetrafluoroethylene sold under the trademark Teflon,
nonconductive paste (e.g., silica) filled with an inorganic
material, bismaleimide material filled with polytetrafluoroethylene
sold under the trademark Teflon, and the like. Support material 102
also serves as a die attach material.
[0030] Referring now to FIG. 7, a top view of multi-chip module 100
is shown wherein the top view illustrates the same stage of
manufacture as that shown in FIG. 6. In other words, FIG. 6 is a
cross-sectional side view taken along section line 6-6 of FIG. 7.
Like FIG. 3, FIG. 7 further illustrates the plurality of bonding
pads 18, the plurality of bonding pads 20, the plurality of bonding
pads 46, the plurality of wire interconnects 56, as well as the
individual bonding pads 18A, 18B, 20A, and 20B and the individual
interconnects 56A and 56B shown in FIGS. 2 and 6. In addition, FIG.
7 illustrates support material 102. Although support material 102
is shown as having a double-Y or dogbone shape, this is not a
limitation of the present invention. For example, support material
102 can be formed to have circular shapes, triangular shapes,
quadrilateral shapes, pentagonal shapes, and other polygonal
shapes.
[0031] Referring now to FIG. 8, a cross-sectional side view of
multi-chip module 100 further along in manufacture is illustrated.
A semiconductor chip 104 is placed on support material 102. More
particularly, semiconductor chip 104 has a backside 106 that is
placed on support material 102 and a front side 108 that has a
plurality of bonding pads 110 formed thereon. Pressure is applied
to semiconductor chip 104 to position it in support material 102
and to urge support material 102 over edges 53 and 55 of spacer 50
and into the region between surfaces 44 and 106. A portion of
support material 102 remains on spacer 50 and a portion of support
material 102 substantially fills the region between surfaces 44 and
106. Because support material 102 substantially fills the region
between surfaces 44 and 106, the peripheral portions 112 of
semiconductor chip 104 do not overhang freely, but are supported.
Thus, peripheral portions 112 do not significantly during a
subsequent wirebonding step. Support material 102 is cured by being
to a temperature ranging from about 100.degree. C. to about
175.degree. C. for a time ranging from about 5 minutes to about 60
minutes. An advantage of placing support material 102 between
surfaces 44 and 106 is that it improves the manufacturability and
reliability of wirebonds formed in multi-level semiconductor
packaging structures.
[0032] A plurality of bonding pads 110 are electrically connected
to corresponding bonding pads of plurality of bonding pads 20
using, for example, a wirebonding process. More particularly,
bonding pad 110A is electrically connected to bonding pad 20A by an
interconnect wire 114A and bonding pad 110B is electrically
connected to bonding pad 20B by an interconnect wire 114B. For
clarity of description, only two interconnect wires, i.e.,
interconnect wires 114A and 114B, of a plurality of interconnect
wires are shown in FIG. 8.
[0033] Referring now to FIG. 9, a protective covering 116 is formed
over semiconductor chip 104, interconnect wires 56A, 56B, 114A, and
114B, and BGA support substrate 12. Protective covering 116
illustrated in FIG. 9 is a lid secured to BGA support substrate 12
by a lid attach material 118. It should be understood that the type
of protective covering is not limited to being a lid. For example,
protective covering 114 may be a glob top material or other
suitable protective material.
[0034] By now it should be appreciated that a multi-chip module
having vertically stacked semiconductor chips and a method for
manufacturing the multi-chip module been provided. An advantage of
multi-chip modules in accordance with the present invention is that
it provides a means for decreasing vibration or bounce of regions
of a semiconductor chip during a wirebonding process. This improves
the reliability of the wirebonds and decreases catastrophic device
failure. Another advantage of the present invention is that it
increases the variety in the sizes of the semiconductor chips that
can be bonded to a spacer. Because the support material provides
additional support for the semiconductor chip, larger chips can be
mounted to the spacer. In addition, the method is readily
integrable into multi-chip module processing flows in a cost and
time efficient manner.
[0035] Although certain preferred embodiments and methods have been
disclosed herein, it will be apparent from the foregoing disclosure
to those skilled in the art that variations and modifications of
such embodiments and methods may be made without departing from the
spirit and scope of the invention. For example, the support
material may be disposed on the spacer and the first semiconductor
chip. Alternatively, an adhesive film can be used to couple
semiconductor chip 64 to spacer 50 rather than using a die attach
material such as the attach material 48. An advantage of using an
adhesive material is that an adhesive material does not have to be
cured. It is intended that the invention shall be limited only to
the extent required by the appended claims and the rules and
principles of applicable law.
* * * * *