U.S. patent application number 13/593725 was filed with the patent office on 2014-02-27 for using fast anneal to form uniform ni(pt)si(ge) contacts on sige layer.
This patent application is currently assigned to International Business Machines Corporation. The applicant listed for this patent is Joseph S. Newbury, Kenneth Parker Rodbell, Zhen Zhang, Yu Zhu. Invention is credited to Joseph S. Newbury, Kenneth Parker Rodbell, Zhen Zhang, Yu Zhu.
Application Number | 20140057399 13/593725 |
Document ID | / |
Family ID | 50147253 |
Filed Date | 2014-02-27 |
United States Patent
Application |
20140057399 |
Kind Code |
A1 |
Newbury; Joseph S. ; et
al. |
February 27, 2014 |
Using Fast Anneal to Form Uniform Ni(Pt)Si(Ge) Contacts on SiGe
Layer
Abstract
Techniques for forming a smooth silicide without the use of a
cap layer are provided. In one aspect, a cap layer-free method for
forming a silicide is provided. The method includes the following
steps. A semiconductor material selected from: silicon and silicon
germanium is provided. At least one silicide metal is deposited on
the semiconductor material. The semiconductor material and the at
least one silicide metal are annealed at a temperature of from
about 400.degree. C. to about 800.degree. C. for a duration of less
than or equal to about 10 milliseconds to form the silicide. A FET
device and a method for fabricating a FET device are also
provided.
Inventors: |
Newbury; Joseph S.;
(Irvington, NY) ; Rodbell; Kenneth Parker; (Sandy
Hook, CT) ; Zhang; Zhen; (Ossining, NY) ; Zhu;
Yu; (West Harrison, NY) |
|
Applicant: |
Name |
City |
State |
Country |
Type |
Newbury; Joseph S.
Rodbell; Kenneth Parker
Zhang; Zhen
Zhu; Yu |
Irvington
Sandy Hook
Ossining
West Harrison |
NY
CT
NY
NY |
US
US
US
US |
|
|
Assignee: |
International Business Machines
Corporation
Armonk
NY
|
Family ID: |
50147253 |
Appl. No.: |
13/593725 |
Filed: |
August 24, 2012 |
Current U.S.
Class: |
438/158 ;
257/E21.296; 257/E21.409; 438/683 |
Current CPC
Class: |
H01L 21/28518 20130101;
H01L 29/45 20130101; H01L 29/66628 20130101; H01L 29/7848 20130101;
H01L 29/66636 20130101 |
Class at
Publication: |
438/158 ;
438/683; 257/E21.296; 257/E21.409 |
International
Class: |
H01L 21/3205 20060101
H01L021/3205; H01L 21/336 20060101 H01L021/336 |
Claims
1. A cap layer-free method for forming a silicide, the method
comprising the steps of: providing a semiconductor material
selected from the group consisting of: silicon and silicon
germanium; depositing at least one silicide metal on the
semiconductor material; annealing the semiconductor material and
the at least one silicide metal to form the silicide using a one
step anneal which comprises annealing the semiconductor material
and the at least one silicide metal at a temperature of from about
400.degree. C. to about 800.degree. C. for a duration of less than
or equal to about 10 milliseconds; and removing any unreacted metal
after the one step anneal has been performed.
2. The method of claim 1, wherein the semiconductor material
comprises in situ boron doped silicon germanium.
3. The method of claim 2, wherein the semiconductor material
comprises from about 10% germanium to about 50% germanium.
4. The method of claim 1, wherein the semiconductor material
comprises implantation or in situ doped silicon.
5. The method of claim 1, further comprising the step of:
performing a pre-silicide clean of the semiconductor material to
remove native oxide.
6. The method of claim 1, wherein the at least one silicide metal
is selected from the group consisting of: nickel, platinum,
titanium, tantalum, cobalt, tungsten and combinations comprising at
least one of the foregoing metals.
7. The method of claim 1, wherein the at least one silicide metal
comprises nickel-platinum.
8. The method of claim 1, wherein the at least one silicide metal
is deposited on the semiconductor material by evaporation or
sputtering.
9. The method of claim 1, wherein the annealing step is performed
for a duration of from about 1 microsecond to about 10
milliseconds.
10. The method of claim 1, wherein the annealing step is performed
using a flash annealing process.
11. The method of claim 1, wherein the annealing step is performed
using a laser annealing process.
12. The method of claim 1, further comprising the step of:
pre-heating the semiconductor material to a temperature of from
about 150.degree. C. to about 350.degree. C. prior to performing
the annealing step, wherein a bottom side of the semiconductor
material is pre-heated and the annealing is performed on a top of
the semiconductor material.
13. (canceled)
14. The method of claim 1, wherein the unreacted metal is removed
using a wet etching process.
15. A method for fabricating a field-effect transistor (FET)
device, the method comprising the steps of: providing a
silicon-on-insulator (SOI) wafer having a SOI layer over a buried
oxide (BOX); forming at least one active area in the wafer; forming
a gate stack over a portion of the at least one active area which
will serve as a channel of the device; forming source and drain
regions of the device adjacent to the gate stack, wherein the
source and drain regions of the device comprise a semiconductor
material selected from the group consisting of: silicon and silicon
germanium; depositing at least one silicide metal on the wafer;
annealing the semiconductor material and the at least one silicide
metal to form silicide contacts to the source and drain regions of
the device using a one step anneal which comprises annealing the
semiconductor material and the at least one silicide metal at a
temperature of from about 400.degree. C. to about 800.degree. C.
for a duration of less than or equal to about 10 milliseconds; and
removing any unreacted metal after the one step anneal has been
performed.
16. The method of claim 15, wherein the at least one active areas
are formed in the wafer using shallow trench isolation (STI).
17. The method of claim 15, further comprising the step of: forming
spacers on opposite side of the gate stack.
18. The method of claim 15, wherein the semiconductor material
comprises in situ boron doped silicon germanium.
19. The method of claim 18, wherein the semiconductor material
comprises from about 10% germanium to about 50% germanium.
20. The method of claim 15, wherein the semiconductor material
comprises implantation or in situ doped silicon.
21. The method of claim 15, wherein the at least one silicide metal
is selected from the group consisting of: nickel, platinum,
titanium, tantalum, cobalt, tungsten and combinations comprising at
least one of the foregoing metals.
22. The method of claim 15, wherein the annealing step is performed
for a duration of from about 1 microsecond to about 10
milliseconds.
23. The method of claim 15, wherein the annealing step is performed
using a flash annealing process or a laser annealing process.
24. (canceled)
25. The method of claim 15, wherein the unreacted metal is removed
using a wet etching process.
Description
FIELD OF THE INVENTION
[0001] The present invention relates to silicide formation and more
particularly, to techniques for forming a smooth silicide without
the use of a cap layer.
BACKGROUND OF THE INVENTION
[0002] Embedded silicon germanium (SiGe) has recently been used as
the source/drain material to boost channel hole mobility (due to
the stress induced by lattice mismatch). Nickel platinum (NiPt)
silicide is the standard contact metal to the SiGe, however
NiPt--SiGe reaction under normal rapid thermal anneal (RTA) results
in bad interface morphology (silicide spikes).
[0003] Silicide spikes into the SiGe source/drain may cause severe
stress loss or junction leakage. This bad interface morphology
issue becomes even worse when the percentage of germanium (Ge) is
increased.
[0004] Conventional approaches to deal with the problem include
using a silicon (Si) or SiGe cap layer with a lower percentage of
Ge in order to improve the surface morphology. Namely, the cap
layer reacts with the NiPt to form the NiSi, thus avoiding the
interface morphology problem. However, employing a cap layer in a
fabrication process flow increases both production complexity and
cost.
[0005] Therefore, techniques that avoid bad interface morphology in
SiGe source/drain contact formation without introducing the
complexity and cost of using a cap layer would be desirable.
SUMMARY OF THE INVENTION
[0006] The present invention provides techniques for forming a
smooth silicide without the use of a cap layer. In one aspect of
the invention, a cap layer-free method for forming a silicide is
provided. The method includes the following steps. A semiconductor
material selected from: silicon and silicon germanium is provided.
At least one silicide metal is deposited on the semiconductor
material. The semiconductor material and the at least one silicide
metal are annealed at a temperature of from about 400.degree. C. to
about 800.degree. C. for a duration of less than or equal to about
10 milliseconds to form the silicide.
[0007] In another aspect of the invention, a method for fabricating
a field-effect transistor (FET) device is provided. The method
includes the following steps. A silicon-on-insulator (SOI) wafer
having a SOI layer over a buried oxide (BOX) is provided. At least
one active area is formed in the wafer. A gate stack is formed over
a portion of the at least one active area which will serve as a
channel of the device. Source and drain regions of the device are
formed adjacent to the gate stack, wherein the source and drain
regions of the device include a semiconductor material selected
from: silicon and silicon germanium. At least one silicide metal is
deposited on the wafer. The semiconductor material and the at least
one silicide metal are annealed at a temperature of from about
400.degree. C. to about 800.degree. C. for a duration of less than
or equal to about 10 milliseconds to form silicide contacts to the
source and drain regions of the device.
[0008] In yet another aspect of the invention, a FET device is
provided. The FET device includes a SOI wafer having a SOI layer
over a BOX and at least one active area formed in the wafer; a gate
stack over a portion of the at least one active area which serves
as a channel of the device; source and drain regions of the device
adjacent to the gate stack, wherein the source and drain regions of
the device include a semiconductor material selected from: silicon
and silicon germanium; and silicide contacts to the source and
drain regions of the device, wherein an interface is present
between the silicide contacts and the semiconductor material, and
wherein the interface has an interface roughness of less than about
5 nanometers.
[0009] A more complete understanding of the present invention, as
well as further features and advantages of the present invention,
will be obtained by reference to the following detailed description
and drawings.
BRIEF DESCRIPTION OF THE DRAWINGS
[0010] FIG. 1 is a cross-sectional diagram illustrating a silicide
metal having been deposited onto a semiconductor material (e.g.,
silicon or silicon germanium) according to an embodiment of the
present invention;
[0011] FIG. 2 is a cross-sectional diagram illustrating a fast
anneal (e.g., flash anneal or laser anneal) having been used to
react the metal with the semiconductor material to form a silicide
according to an embodiment of the present invention;
[0012] FIG. 3 is a cross-sectional diagram illustrating an optional
step of removing any unreacted metal following the silicide
reaction according to an embodiment of the present invention;
[0013] FIG. 4 is a cross-sectional diagram illustrating a starting
structure for a field-effect transistor (FET) device fabrication
process having a gate stack and source and drain regions formed
adjacent to/on opposite sides of the gate stack according to an
embodiment of the present invention;
[0014] FIG. 5 is a cross-sectional diagram illustrating a silicide
metal(s) having been is blanket deposited onto the wafer covering
the source and drain regions according to an embodiment of the
present invention;
[0015] FIG. 6 is a cross-sectional diagram illustrating a fast
anneal having been used to react the silicide metal(s) with the
semiconductor material in the source and drain regions to form a
silicide according to an embodiment of the present invention;
[0016] FIG. 7 is a cross-sectional diagram illustrating unreacted
silicide metal(s) having been removed from the device to form self
aligned source and drain region contacts according to an embodiment
of the present invention;
[0017] FIG. 8A is a top-down scanning electron micrograph (TDSEM)
image of a SiGe silicide sample prepared using rapid thermal
annealing (and no cap layer) according to an embodiment of the
present invention;
[0018] FIG. 8B is a cross-sectional transmission electron
micrograph (XTEM) image of the SiGe silicide sample prepared using
rapid thermal annealing (and no cap layer) according to an
embodiment of the present invention;
[0019] FIG. 9A is a TDSEM image of a SiGe silicide sample prepared
using flash anneal with a peak temperature of 500.degree. C. (and
no cap layer) according to an embodiment of the present
invention;
[0020] FIG. 9B is a XTEM image of the SiGe silicide sample prepared
using flash anneal with a peak temperature of 500.degree. C. (and
no cap layer) according to an embodiment of the present
invention;
[0021] FIG. 10A is a TDSEM image of a SiGe silicide sample prepared
using flash anneal with a peak temperature of 600.degree. C. (and
no cap layer) according to an embodiment of the present invention;
and
[0022] FIG. 10B is a XTEM image of the SiGe silicide sample
prepared using flash anneal with a peak temperature of 600.degree.
C. (and no cap layer) according to an embodiment of the present
invention.
DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS
[0023] Provided herein are techniques for forming a metal (such as,
but not limited to, nickel platinum (NiPt) silicide) on a silicon
germanium (SiGe) material which avoid interface morphology issues
commonly associated with metal silicide formation on a SiGe
material (see above) without the use of a cap layer, which
advantageously lowers the complexity and cost of the fabrication
process as compared to conventional processes. Namely, in the
present techniques a fast anneal (flash anneal or laser anneal) is
employed rather than a conventional rapid thermal anneal to form
metal silicide on SiGe (with no cap layer). The result (as provided
in detail below) is a very smooth metal silicide.
[0024] An overview of the present techniques will first be provided
by way of reference to FIGS. 1-3, followed by an exemplary
implementation of the present techniques to form source and drain
contacts in an exemplary field-effect transistor (FET) device
illustrated by way of reference to FIGS. 4-7. FIG. 1 is a
cross-sectional diagram illustrating an exemplary starting
semiconductor material 102 for the process. According to an
exemplary embodiment, semiconductor material 102 is a silicon (Si)
or SiGe material. In the exemplary FET fabrication process flow
described below, the starting semiconductor material is an embedded
in-situ boron doped SiGe or implantation or in-situ doped Si
source/drain of the device.
[0025] A pre-silicide clean may be performed on the semiconductor
material 102 (prior to metal deposition, see below) to remove
native oxide. Suitable pre-silicide clean treatments to remove
native oxide include, but are not limited to, hydrofluoric acid
(HF) and reactive pre-clean (RPC).
[0026] Next, as shown in FIG. 1, a silicide metal or metals 104
is/are deposited onto the material. Suitable silicide metals
include, but are not limited to, nickel (Ni), platinum (Pt),
titanium (Ti), tantalum (Ta), cobalt (Co), tungsten (W) and
combinations including at least one of the foregoing metals, such
as nickel platinum (NiPt) and titanium platinum (TiPt). The
metal(s) 104 may be deposited onto the semiconductor material 102
using, e.g., evaporation or sputtering.
[0027] A fast anneal is then used to react the metal(s) 104 with
the semiconductor material 102 to form a silicide 202. See FIG. 2.
Advantageously, it has been found by way of the present techniques
that employing a high temperature, short duration anneal will
result in a very smooth interface (see results described below),
without the need for a capping layer. According to an exemplary
embodiment, during this annealing step the metal/semiconductor
material is heated to a temperature of from about 400.degree. C. to
about 800.degree. C. for a duration of less than or equal to about
10 milliseconds, e.g., from about 1 microsecond to about 10
milliseconds. Such annealing conditions can be achieved using a
flash or laser annealing process. According to an exemplary
embodiment, the semiconductor material is preheated to an initial
temperature of from about 150.degree. C. to about 350.degree. C.
prior to the fast anneal. By way of example only, the semiconductor
material can be heated using a back lamp, e.g., wherein the
back/bottom side of the semiconductor material is heated and the
fast anneal is performed on the top.
[0028] As shown in FIG. 3, any unreacted metal(s) 104 can be
removed using a wet etching process. By way of example only, a
suitable wet etching process for removing unreacted metal includes
(but is not limited to) a soak in H.sub.2O:HCl:HNO.sub.3=4:5:1 for
10 minutes at 40 degrees Celsius (.degree. C.). This step is
optional. Namely, in the case of formation of a self-aligned
silicide process (such as in the case of self-aligned silicide
source and drain contacts, see description of FIGS. 4-7, below), it
is desirable to remove the unreacted metal. However in the case of
a trench silicide process, for example, removal of the unreacted
metal might not be necessary.
[0029] As provided above, use of the present process results in a
very smooth metal silicide interface with the underlying
semiconductor material 102 advantageously without the use of a cap
layer. The smoothness of the interface may be quantified based on
interface roughness. As shown in FIG. 3, the interface between the
silicide and the underlying semiconductor material, at a
microscopic level (as depicted in the magnified view) is not
perfectly smooth. The roughness at the interface (interface
roughness) is made up of a plurality of peaks and valleys.
According to an exemplary embodiment, the interface roughness is
quantified based on an average height h between the peaks and
valleys which according to the present techniques is less than
about 5 nanometers (nm), e.g., from about 0.1 nm to about 5 nm, and
that is considered herein to be a smooth interface. Interface
roughness is further described in U.S. Pat. No. 6,521,515 issued to
Kluth, entitled "Deeply Doped Source/Drains for Reduction of
Silicide/Silicon interface Roughness," the contents of which are
incorporated by reference herein.
[0030] Further, the present teachings achieve this smooth interface
without a cap layer. As described above, with conventional
techniques in order to avoid a rough interface, a silicon (Si) or
SiGe cap layer with a lower percentage of Ge is typically employed.
Use of such a cap layer will result in a non-uniform distribution
of Ge in the semiconductor material beneath the silicide (e.g., a
lower amount of Ge will be present at the top of the semiconductor
material due to the presence of the cap layer). By comparison, with
the present techniques (because no cap layer is used) the
concentration of Ge will be uniform throughout the underlying
semiconductor material 102. Thus, according to an exemplary
embodiment, wherein the semiconductor material contains Ge (e.g.,
SiGe), post-silicide formation the Ge concentration in the
underlying semiconductor material 102 does not vary by more than 3
percent (%) anywhere in the underlying semiconductor material 102
(which is considered herein to be a uniform concentration). Thus,
the Ge concentration of a sample taken from any given first portion
of the present underlying semiconductor material 102 will not vary
by .+-.3% from the Ge concentration taken from any given second
portion of underlying semiconductor material 102. It is notable
that in the above example the concentration of Ge in the silicide
might be uniform or it might not be uniform. Both scenarios are
anticipated by the present techniques. The uniformity of the Ge
concentration in the resulting silicide can be dependent on the
uniformity of the concentration of the (pre-silicide) semiconductor
material. Using the above measure of uniformity, if the SiGe
concentration in the (pre-silicide) semiconductor material 102 does
not vary by more than 3% anywhere in the (pre-silicide)
semiconductor material 102, then a uniform Ge concentration
throughout the silicide can also be achieved wherein a
concentration of germanium in the silicide contacts does not vary
by more than 3 percent anywhere in the silicide contacts (i.e.,
wherein the Ge concentration of a sample taken from any given first
portion of the present silicide will not vary by .+-.3% from the Ge
concentration taken from any given second portion of the silicide).
However, as provided above, both a uniform and a non-uniform
silicide composition are anticipated herein.
[0031] An exemplary implementation of the present techniques to
fabricate source and drain contacts in a FET device is now provided
by way of reference to FIGS. 4-7. It is however notable that the
present techniques are more broadly applicable to any scenario in
which silicide formation is desired on a semiconductor (Si, SiGe,
etc.) material. The example shown in FIGS. 4-7 is thus provided
merely to further illustrate the present techniques. Any of the
above-described materials and/or processes (see description of
FIGS. 1-3) may be employed in this example.
[0032] FIG. 4 is a cross-sectional diagram illustrating a FET
device for which self-aligned contacts will be formed using the
present techniques. By way of example only, as shown in FIG. 4, the
starting platform for the FET fabrication process is an Si layer
over a buried oxide (BOX). This type of wafer configuration is also
referred to as a silicon-on-insulator (SOI) wafer where the
insulator is the BOX. An active area is defined in the wafer using
shallow trench isolation (STI). As known by those of skill in the
art, STI involves patterning trenches in the wafer that, in this
example, extend through the SOI layer, and then filing the trenches
with an insulator material such as an oxide.
[0033] A gate stack 402 is formed over the active area (i.e., over
a portion of the active area which will serve as a channel of the
device). While represented schematically in the figures as a single
block, it is to be understood that gate stack 402 may include a
single or multiple layers of a respective gate material(s).
Suitable gate materials include, but are not limited to, a metal(s)
and/or doped polysilicon. Standard processes may be employed to
fabricate the gate stack 402. For instance, the gate stack
material(s) may be deposited onto the wafer. A hardmask 404 may be
formed on the gate stack materials and used to pattern a gate
line(s) of the device, resulting in gate stack 402.
[0034] An optional gate dielectric 406 may be present between the
gate stack 402 and a portion of the active area that will serve as
a channel of the device. In general a FET includes a source region
and a drain region interconnected by a channel and a gate (in this
case gate stack 402) that regulates electron flow through the
channel. By way of example only, when the gate stack 402 includes
metal(s), then a suitable gate dielectric material includes, but is
not limited to, a high-k dielectric. When the gate stack 402
includes doped poly silicon, a suitable gate dielectric material
includes an oxide, such as silicon dioxide.
[0035] Optional spacers 408 are formed on opposite sides of the
gate stack 402. As shown in FIG. 4, gate spacers are present on
opposite sides of the gate stack 402. According to an exemplary
embodiment, the spacers can be formed from a nitride material, such
as (but not limited to) silicon nitride. Standard techniques are
employed to form the spacers. For example, the spacer material can
be blanket deposited over the structure and then reactive ion
etching (RIE) can be used to form the spacers.
[0036] Source and drain regions 410 are formed adjacent to the gate
stack 402. According to an exemplary embodiment, the source and
drain regions 410 are embedded in situ boron doped SiGe source and
drain regions. The process for forming in situ doped embedded SiGe
source and drain regions by epitaxy are described, for example, in
U.S. Pat. No. 7,176,481 issued to Chen et al., entitled "In Situ
Doped Embedded SiGe Extension and Source/Drain for Enhanced PFET
Performance," the contents of which are incorporated by reference
herein. According to one exemplary embodiment, the source and drain
regions 410 are embedded in situ boron doped SiGe source and drain
regions which contain at least 10 percent (%) germanium (Ge), i.e.,
the embedded in situ boron doped SiGe source and drain regions
contain from about 10% Ge to about 50% Ge, and are doped with boron
to a concentration of from about 1.times.10.sup.10 cm.sup.-3 to
about 3.times.10.sup.21 cm.sup.-3. Given the present teachings, one
of skill in the art would be capable of fabricating embedded in
situ boron doped SiGe having a Ge content and doping concentration
with the above-specified parameters.
[0037] The use of embedded SiGe as the source and drain material is
merely to illustrate the advantages of the present techniques in
forming a silicide to a SiGe material without the use of a cap
layer. The source and drain regions 410 may instead be formed, for
example, from implantation or in situ doped Si. For instance, the
source and drain regions 410 may be formed by implanting a
dopant(s) into the SOI layer adjacent to/on opposite sides of the
gate stack 402. By way of example only, suitable source/drain
dopants include, but are not limited to, silicon (n-type) and
carbon (p-type), wherein the particular dopant employed will depend
on the device being formed (e.g., an n-channel FET or a p-channel
FET, respectively). The implanted dopants can be activated using an
anneal, for example, at a temperature of from about 400.degree. C.
to about 1,300.degree. C. A pre-silicide clean may be performed at
this point in the process to remove any native oxide on the source
and drain regions. This pre-silicide clean process was described in
detail above.
[0038] Next, as shown in FIG. 5, a silicide metal(s) 502 is blanket
deposited onto the wafer covering the source and drain regions 410.
As provided above, suitable silicide metals include, but are not
limited to, Ni, Pt and combinations including at least one of the
foregoing metals, such as NiPt. The silicide metal(s) 502 may be
deposited onto the wafer using, e.g., evaporation or
sputtering.
[0039] In this particular example, a self-aligned silicide (a
salicide) will be formed as source and drain region contacts.
Advantageously, the silicide will form only where the silicide
metal is deposited on exposed semiconductor material, in this case
in the source and drain regions of the device. A metal strip will
be performed later in the process to remove unreacted metal. As
provided above, if a self-aligned silicide (salicide) is not
desired, then the metal strip does not need to be performed (i.e.,
the unreacted metal remains), and thus this step is optional.
[0040] Next, as shown in FIG. 6, according to the present
techniques, a fast anneal is used to react the silicide metal 502
with the semiconductor material in the source and drain regions 410
to form a silicide 602. As described above, it has advantageously
been found by way of the present techniques that employing a high
temperature, short duration anneal will result in a very smooth
interface (see results described below), without the need for a
capping layer. According to an exemplary embodiment, during this
annealing step the silicide metal 502/semiconductor material in the
source and drain regions 410 is heated to a temperature of from
about 400.degree. C. to about 800.degree. C. for a duration of less
than or equal to about 10 milliseconds, e.g., from about 1
microsecond to about 10 milliseconds. Such annealing conditions can
be achieved using a flash or laser annealing process. According to
an exemplary embodiment, the device is preheated to an initial
temperature of from about 150.degree. C. to about 350.degree. C.
prior to the fast anneal.
[0041] It is notable that the amount of silicide formed in this
step is dependent on factors such as the amount of silicide metal
502 present, the annealing conditions, etc. It is desirable that
the semiconductor is not fully consumed and (as shown in FIG. 6)
following the silicide formation a portion of the source and drain
region semiconductor material remains below the silicide 602,
defining an interface between the silicide and the semiconductor
(i.e., a silicide-semiconductor interface). It is within the
capabilities of one of skill in the art to determine, given the
specific annealing conditions and materials taught herein, for
example, how much metal to deposit to achieve this desired result.
As provided above, with the present techniques, the roughness at
this silicide-semiconductor interface (i.e., interface roughness)
is less than about 5 nm, e.g., from about 0.1 nm to about 5 nm,
which is considered herein to be a smooth interface. As also
provided above, the absence of a cap layer in the present
techniques (which reduces production complexity--and thus
production costs) means that the (post-silicide) semiconductor
material underlying the silicide will have a uniform Ge
concentration throughout, e.g., the Ge concentration in the
semiconductor material does not vary by more than 3% anywhere in
the semiconductor material, which is considered herein to be a
uniform concentration. According to an exemplary embodiment, the
silicide may have a uniform or non-uniform Ge concentration (see
above).
[0042] In order to form contacts to only the source and drain
regions of the device, it is desirable in this example to remove
the unreacted metal. As shown in FIG. 7, the unreacted silicide
metal(s) 502 has been removed from the device surfaces. As provided
above, any unreacted silicide metal(s) 502 can be removed using a
wet etching process. By way of example only, a suitable wet etching
process for removing unreacted metal includes (but is not limited
to) a soak in H.sub.2O:HCl:HNO.sub.3=4:5:1 for 10 minutes at
40.degree. C. Again, this step is optional. In the case of a trench
silicide process, for example, removal of the unreacted metal might
not be necessary.
[0043] The result is the silicide 602 which is self-aligned to the
source and drain regions of the device. This silicide 602 serves as
contacts to the source and drain regions of the device.
[0044] As provided above, the present techniques provide a way to
form a silicide in a Ge-containing (or other semiconductor)
substrate without the use of a cap layer (cap layer-free), which
results in a smooth interface between the silicide and the
underlying substrate material. See, for example, FIG. 7. As
described above, the `smoothness` of this interface between the
silicide and the underlying substrate material can be quantified
based on interface roughness. Namely, as provided above, with the
present techniques, the interface roughness is less than about 5
nm, e.g., from about 0.1 nm to about 5 nm, which is considered
herein to be a smooth interface. As also provided above, the
absence of a cap layer in the present techniques (which reduces
production complexity--and thus production costs) means that the
(pos-silicide) semiconductor material underlying the silicide will
have a uniform Ge concentration throughout, e.g., the Ge
concentration in the underlying semiconductor material does not
vary by more than 3% anywhere in the semiconductor material, which
is considered herein to be a uniform concentration. According to an
exemplary embodiment, the silicide may have a uniform or
non-uniform Ge concentration (see above).
[0045] The present techniques are further illustrated by way of
reference to the following non-limiting examples. Samples were
prepared as follows: 45 nm blanket epitaxial in situ boron doped
SiGe layers were grown on counter-doped Si substrate (the sheet
resistance Rs of the substrates.fwdarw..infin.). The SiGe contained
30% Ge. Silicide formation was performed using 6 nm Ni 10% Pt with
3 different anneals (normal RTA--for comparison purposes, flash
anneal with a peak temperature of 500.degree. C. and flash anneal
with a peak temperature of 600.degree. C.). The RTA anneal was
performed at 420.degree. C. for 5 seconds. The flash anneals were
both performed according to the above-described present techniques
(e.g., at the above-stated temperatures for a duration of less than
or equal to about 10 milliseconds). Unreacted metal was removed
from each sample following the silicide formation. None of the
samples used a cap layer.
[0046] Top-down scanning electron micrograph (TDSEM) and
cross-sectional transmission electron micrograph (XTEM) images of
the RTA anneal samples are shown in FIGS. 8A and 8B, respectively.
As shown in FIG. 8A, which shows a top down view of the silicide,
the silicide formed through RTA is very rough. It is notable that
with conventional processes involving RTA, a cap layer would be
employed. The cross-sectional view of the RTA sample shown in FIG.
8B illustrates the rough interface between the silicide and the
underlying semiconductor substrate. The RTA sample had a sheet
resistance Rs of 53 .OMEGA./square.
[0047] TDSEM and XTEM images of the flash anneal samples with a
peak temperature of 500.degree. C. are shown in FIGS. 9A and 9B,
respectively. As shown in FIG. 9A, which shows a top down view of
the silicide, the silicide formed through flash anneal is very
smooth. The cross-sectional view of the flash anneal sample shown
in FIG. 9B illustrates the smooth interface between the silicide
and the underlying semiconductor substrate. The flash anneal with a
peak temperature of 500.degree. C. sample had a sheet resistance Rs
of 52 .OMEGA./square.
[0048] TDSEM and XTEM images of the flash anneal samples with a
peak temperature of 600.degree. C. are shown in FIGS. 10A and 10B,
respectively. As shown in FIG. 10A, which shows a top down view of
the silicide, the silicide formed through flash anneal is very
smooth. The cross-sectional view of the flash anneal sample shown
in FIG. 10B illustrates the smooth interface between the silicide
and the underlying semiconductor substrate. The flash anneal with a
peak temperature of 600.degree. C. sample had a sheet resistance Rs
of 28 .OMEGA./square.
[0049] Although illustrative embodiments of the present invention
have been described herein, it is to be understood that the
invention is not limited to those precise embodiments, and that
various other changes and modifications may be made by one skilled
in the art without departing from the scope of the invention.
* * * * *