U.S. patent application number 13/790004 was filed with the patent office on 2013-10-10 for integration technique using thermal oxide select gate dielectric for select gate and apartial replacement gate for logic.
This patent application is currently assigned to FREESCALE SEMICONDUCTOR INC.. The applicant listed for this patent is Frank K. Baker, JR., Mark D. Hall, Mehul D. Shroff. Invention is credited to Frank K. Baker, JR., Mark D. Hall, Mehul D. Shroff.
Application Number | 20130267074 13/790004 |
Document ID | / |
Family ID | 49292609 |
Filed Date | 2013-10-10 |
United States Patent
Application |
20130267074 |
Kind Code |
A1 |
Hall; Mark D. ; et
al. |
October 10, 2013 |
INTEGRATION TECHNIQUE USING THERMAL OXIDE SELECT GATE DIELECTRIC
FOR SELECT GATE AND APARTIAL REPLACEMENT GATE FOR LOGIC
Abstract
A thermally-grown oxygen-containing layer is formed over a
control gate in an NVM region, and a high-k dielectric layer and
barrier layer are formed in a logic region. A polysilicon layer is
formed over the oxygen-containing layer and barrier layer and is
planarized. A first masking layer is formed over the polysilicon
layer and control gate defining a select gate location laterally
adjacent the control gate. A second masking layer is formed
defining a logic gate location. Exposed portions of the polysilicon
layer are removed such that a select gate remains at the select
gate location and a polysilicon portion remains at the logic gate
location. A dielectric layer is formed around the select and
control gates and polysilicon portion. The polysilicon portion is
removed to result in an opening at the logic gate location which
exposes the barrier layer.
Inventors: |
Hall; Mark D.; (Austin,
TX) ; Shroff; Mehul D.; (Austin, TX) ; Baker,
JR.; Frank K.; (Austin, TX) |
|
Applicant: |
Name |
City |
State |
Country |
Type |
Hall; Mark D.
Shroff; Mehul D.
Baker, JR.; Frank K. |
Austin
Austin
Austin |
TX
TX
TX |
US
US
US |
|
|
Assignee: |
FREESCALE SEMICONDUCTOR
INC.
Austin
TX
|
Family ID: |
49292609 |
Appl. No.: |
13/790004 |
Filed: |
March 8, 2013 |
Related U.S. Patent Documents
|
|
|
|
|
|
Application
Number |
Filing Date |
Patent Number |
|
|
13442142 |
Apr 9, 2012 |
|
|
|
13790004 |
|
|
|
|
Current U.S.
Class: |
438/299 ;
438/595 |
Current CPC
Class: |
H01L 29/42332 20130101;
H01L 29/42328 20130101; H01L 21/82 20130101; H01L 29/42344
20130101; H01L 29/51 20130101; H01L 29/40114 20190801; H01L
29/42348 20130101; H01L 21/28008 20130101; H01L 27/11573 20130101;
H01L 29/7881 20130101; H01L 27/11536 20130101; H01L 27/11526
20130101; H01L 29/66825 20130101; H01L 27/11534 20130101; H01L
29/40117 20190801; H01L 29/66545 20130101; H01L 29/66833
20130101 |
Class at
Publication: |
438/299 ;
438/595 |
International
Class: |
H01L 21/82 20060101
H01L021/82; H01L 21/28 20060101 H01L021/28 |
Claims
1. A method of making a logic transistor in a logic region of a
substrate and a non-volatile memory (NVM) cell in an NVM region of
the substrate, comprising: forming a control gate overlying a
charge storage layer over the substrate in the NVM region; forming
a thermally-grown oxygen-containing dielectric layer on the
substrate and the control gate in the NVM region and on the
substrate in the logic region; removing the thermally-grown
oxygen-containing dielectric layer from the logic region; forming a
high-k gate dielectric layer over the substrate in the logic
region; forming a barrier layer over the high-k gate dielectric
layer in the logic region; forming a polysilicon layer over the
thermally-grown oxygen-containing dielectric layer in the NVM
region and over the barrier layer in the logic region; planarizing
the polysilicon layer; forming a first masking layer over the
polysilicon layer and control gate in the NVM region, wherein the
first masking layer defines a select gate location laterally
adjacent the control gate in the NVM region; forming a second
masking layer over the polysilicon layer in the logic region,
wherein the second masking layer defines a logic gate location in
the logic region; using the first masking layer to remove exposed
portions of the polysilicon layer in the NVM region, wherein a
first portion of the polysilicon layer remains at the select gate
location to form a select gate; using the second masking layer to
remove exposed portions of the polysilicon layer in the logic
region, wherein a second portion of the polysilicon layer remains
at the logic gate location; forming a dielectric layer in the NVM
region and the logic region, wherein the dielectric layer is formed
over the select gate, the control gate, and the second portion of
the polysilicon layer; planarizing the dielectric layer to expose
the second portion of the polysilicon layer; and removing the
second portion of the polysilicon layer to result in an opening at
the logic gate location, wherein the opening exposes the barrier
layer.
2. The method of claim 1, wherein the step of forming the first
masking layer is performed such that: the first masking layer is
directly over the control gate, and a first edge of the first
masking layer extends laterally from the control gate onto the
polysilicon layer to define the select gate location laterally
adjacent the control gate in the NVM region.
3. The method of claim 1, further comprising: forming a protection
layer over the select gate and the control gate in the NVM region,
wherein the protection layer exposes the logic region.
4. The method of claim 1, further comprising: prior to the step of
forming the thermally-grown oxygen-containing dielectric layer,
forming an oxide spacer on a sidewall of the control gate.
5. The method of claim 1, wherein the first masking layer and the
second masking layer are portions of a same patterned masking
layer, and wherein the steps of using the first masking layer to
remove exposed portions of the polysilicon layer in the NVM region
and using the second masking layer to remove exposed portions of
the polysilicon layer in the logic region are performed
simultaneously.
6. The method of claim 1, wherein the barrier layer comprises a
work-function-setting metal.
7. The method of claim 1, wherein the step of forming the control
gate overlying the charge storage layer over the substrate in the
NVM region comprises: forming the charge storage layer over the
substrate in the NVM region and the logic region; forming a second
polysilicon layer over the charge storage layer in the NVM region
and the logic region; and patterning the second polysilicon layer
and the charge storage layer to form the control gate in the NVM
region and to remove the second polysilicon layer and the charge
storage layer from the logic region.
8. The method of claim 1, wherein after the select gate is formed,
a portion of the thermally-grown oxygen-containing dielectric layer
is located between the select gate and the control gate.
9. The method of claim 1, wherein after the steps of using the
first and second masking layers to remove exposed portions of the
polysilicon layer in the NVM region and the logic region, the
method further comprises: forming a first source/drain region in
the substrate laterally adjacent the select gate and a second
source/drain region in the substrate laterally adjacent the control
gate, such that the select gate and the control gate are located
between the first and second source/drain regions; and forming a
third source/drain region in the substrate laterally adjacent a
first sidewall of the second portion of the polysilicon layer and a
fourth source/drain region in the substrate laterally adjacent a
second sidewall of the second portion of the polysilicon layer.
10. The method of claim 9, wherein after the step of using the
first and second masking layers to remove exposed portions of the
polysilicon layer in the NVM region and the logic region, the
method further comprises: forming a first sidewall spacer
surrounding outer sidewalls of the select gate and the control gate
and a second sidewall spacer surrounding the second portion of the
polysilicon layer.
11. The method of claim 1, further comprising: prior to the step of
removing the thermally-grown oxygen-containing dielectric layer
from the logic region, forming a second polysilicon layer over the
thermally-grown oxygen-containing dielectric layer, wherein the
polysilicon layer is formed over the second polysilicon layer, and
wherein the step of removing the thermally-grown oxygen-containing
dielectric layer further comprises removing the second polysilicon
layer from the logic region.
12. The method of claim 11, wherein the steps of forming the high-k
gate dielectric layer and forming the barrier layer comprise:
forming the high-k gate dielectric layer over the second
polysilicon layer in the NVM region and over the substrate in the
logic region; forming the barrier layer over the high-k gate
dielectric layer in the NVM region and in the logic region; and
removing the high-k gate dielectric layer and the barrier layer
from the NVM region.
13. The method of claim 1, wherein the charge storage layer
comprises at least one of nanocrystals or a nitride.
14. The method of claim 3, wherein after the step of removing the
second portion of the polysilicon layer to result in the opening at
the logic gate location, the method further comprises: forming a
logic gate layer over the protection layer in the NVM region and
within the opening on the barrier layer in the logic region; and
planarizing the logic gate layer to result in a logic gate in the
logic gate location, wherein the planarizing removes the protection
layer from the NVM region.
15. A method of making a logic transistor in a logic region of a
substrate and a non-volatile memory (NVM) cell in an NVM region of
the substrate, comprising: forming a control gate overlying a
charge storage layer over the substrate in the NVM region, wherein
the control gate comprises polysilicon; forming an oxide spacer on
a sidewall of the control gate; thermally growing an
oxygen-containing dielectric layer on the substrate in the NVM
region, on the control gate, and on the substrate in the logic
region; removing the oxygen-containing dielectric layer from the
logic region; forming a high-k gate dielectric layer over the
substrate in the logic region; forming a barrier layer over the
high-k gate dielectric layer in the logic region; forming a
polysilicon layer over the oxygen-containing dielectric layer in
the NVM region and over the barrier layer in the logic region;
planarizing the polysilicon layer, wherein the oxygen-containing
dielectric layer comprises a sidewall portion located along a
sidewall of the control gate; forming a first masking layer over
the polysilicon layer and control gate in the NVM region, wherein
the first masking layer defines a select gate location laterally
adjacent the control gate in the NVM region, wherein: the first
masking layer is directly over the control gate, and a first edge
of the first masking layer extends laterally from the control gate
onto the polysilicon layer to define the select gate location
laterally adjacent the control gate in the NVM region; forming a
second masking layer over the polysilicon layer in the logic
region, wherein the second masking layer defines a logic gate
location in the logic region; using the first masking layer to
remove exposed portions of the polysilicon layer in the NVM region,
wherein a first portion of the polysilicon layer remains at the
select gate location to form a select gate; using the second
masking layer to remove exposed portions of the polysilicon layer
in the logic region, wherein a second portion of the polysilicon
layer remains at the logic gate location; forming a dielectric
layer in the NVM region and the logic region, wherein the
dielectric layer is formed over the select gate, the control gate,
and the second portion of the polysilicon layer; planarizing the
dielectric layer to expose the second portion of the polysilicon
layer; forming a protection layer over the select gate and the
control gate in the NVM region, wherein the protection layer
exposes the logic region; removing the second portion of the
polysilicon layer to result in an opening at the logic gate
location, wherein the opening exposes the barrier layer; forming a
logic gate layer over the protection layer in the NVM region and
within the opening on the barrier layer in the logic region; and
planarizing the logic gate layer to result in a logic gate in the
logic gate location, wherein the planarizing removes the protection
layer from the NVM region.
16. The method of claim 15, further comprising: prior to the step
of removing the oxygen-containing dielectric layer from the logic
region, forming a second polysilicon layer over the thermally-grown
oxygen-containing dielectric layer, and wherein the step of
removing the oxygen-containing dielectric layer further comprises
removing the second polysilicon layer from the logic region.
17. The method of claim 16, wherein the steps of forming the high-k
gate dielectric layer and forming the barrier layer comprise:
forming the high-k gate dielectric layer over the second
polysilicon layer in the NVM region and over the substrate in the
logic region; forming the barrier layer over the high-k gate
dielectric layer in the NVM region and in the logic region; and
removing the high-k gate dielectric layer and the barrier layer
from the NVM region.
18. The method of claim 15, wherein after the step of using the
patterned masking layer to remove exposed portions of the
polysilicon layer and prior to the step of forming the protection
layer in the NVM region and the logic region, the method further
comprises: forming a first source/drain region in the substrate
laterally adjacent the select gate and a second source/drain region
in the substrate laterally adjacent the control gate, such that the
select gate and the control gate are located between the first and
second source/drain regions; forming a third source/drain region in
the substrate laterally adjacent a first sidewall of the second
portion of the polysilicon layer and a fourth source/drain region
in the substrate laterally adjacent a second sidewall of the second
portion of the polysilicon layer; and forming a first sidewall
spacer surrounding outer sidewalls of the select gate and the
control gate.
19. The method of claim 15, wherein the barrier layer comprises a
work-function-setting metal.
20. A method of making a logic transistor in a logic region of a
substrate and a non-volatile memory (NVM) cell in an NVM region of
the substrate, comprising: forming a control gate overlying a
charge storage layer over the substrate in the NVM region, wherein
the control gate comprises polysilicon and the charge storage layer
comprises at least one of nanocrystals or a nitride; forming a
thermally-grown oxygen-containing dielectric layer on the substrate
and the control gate in the NVM region and on the substrate in the
logic region; forming a first polysilicon layer over the
thermally-grown oxygen-containing dielectric layer in the NVM
region and the logic region; removing the thermally-grown
oxygen-containing dielectric layer and the first polysilicon layer
from the logic region; forming a high-k gate dielectric layer over
the first polysilicon layer in the NVM region and over the
substrate in the logic region; forming a barrier layer over the
high-k gate dielectric layer in the NVM region and in the logic
region; removing the high-k gate dielectric layer and the barrier
layer from the NVM region; forming a second polysilicon layer over
the first polysilicon layer in the NVM region and over the barrier
layer in the logic region; planarizing the second polysilicon
layer, wherein the thermally-grown oxygen-containing dielectric
layer comprises a sidewall portion located along a sidewall of the
control gate; forming a first masking layer over the polysilicon
layer and control gate in the NVM region, wherein the first masking
layer defines a select gate location laterally adjacent the control
gate in the NVM region, wherein: the first masking layer is
directly over the control gate, and a first edge of the first
masking layer extends laterally from the control gate onto the
second polysilicon layer to define the select gate location
laterally adjacent the control gate in the NVM region; forming a
second masking layer over the second polysilicon layer in the logic
region, wherein the second masking layer defines a logic gate
location in the logic region; using the first masking layer to
remove exposed portions of the second polysilicon layer in the NVM
region, wherein a first portion of the second polysilicon layer
remains at the select gate location to form a select gate; using
the second masking layer to remove exposed portions of the second
polysilicon layer in the logic region, wherein a second portion of
the second polysilicon layer remains at the logic gate location;
forming a dielectric layer in the NVM region and the logic region,
wherein the dielectric layer is formed over the select gate, the
control gate, and the second portion of the second polysilicon
layer; planarizing the dielectric layer to expose the second
portion of the second polysilicon layer; forming a protection layer
over the select gate and the control gate in the NVM region,
wherein the protection layer exposes the logic region; removing the
second portion of the second polysilicon layer to result in an
opening at the logic gate location, wherein the opening exposes the
barrier layer; forming a logic gate layer over the protection layer
in the NVM region and within the opening on the barrier layer in
the logic region; and planarizing the logic gate layer to result in
a logic gate in the logic gate location, wherein the planarizing
removes the protection layer from the NVM region.
Description
CROSS-REFERENCE TO RELATED APPLICATION
[0001] This application is related to U.S. patent application Ser.
No. ______ (Docket Number AC50585TP P01), titled "INTEGRATION
TECHNIQUE USING THERMAL OXIDE SELECT GATE DIELECTRIC FOR SELECT
GATE AND REPLACEMENT GATE FOR LOGIC," naming Mark D. Hall, Mehul D.
Shroff, and Frank K. Baker as inventors, assigned to the current
assignee hereof, and filed on even date herewith.
[0002] This application is continuation-in-part of U.S. patent
application Ser. No. 13/442,142 (Attorney Docket No. AI20026TP),
filed on Apr. 9, 2012, titled "LOGIC TRANSISTOR AND NON-VOLATILE
MEMORY CELL INTEGRATION," naming Mehul D. Shroff and Mark D. Hall
as inventors, and assigned to the current assignee hereof, and
which is hereby incorporated by reference.
BACKGROUND
[0003] 1. Field
[0004] This disclosure relates generally to non-volatile memories,
and more specifically, to integrating non-volatile memories with
logic transistors on the same integrated circuit.
[0005] 2. Related Art
[0006] Many semiconductor devices include, or embed, non-volatile
memory (NVM) transistors with other transistor types on the same
integrated circuit (IC). The manufacturing processes for the
different transistor types may not be the same, requiring that the
processes be integrated. For example, to integrate NVM with CMOS
(complementary metal oxide semiconductor), the CMOS process may be
modified to include the process steps necessary to fabricate the
NVM memory cell and the supporting devices.
[0007] Flash NVM is commonly embedded in, for example,
system-on-a-chip (SoC) integrated circuits having CMOS logic
circuitry. The flash NVM may include a floating gate comprising
polysilicon, or use a charge storage layer comprising nanocrystals
or an ONO (oxide-nitride-oxide) layer. The memory cell may also
include a control gate comprising polysilicon, a metal, or both. In
addition, it may be desirable to use a high-k (where k refers to
the dielectric constant of the material) gate dielectric in the
logic transistor. Integrating the non-volatile memory cell with the
logic transistor having the metal gate and the high-k gate
dielectric on the same integrated circuit may require many
additional process steps.
[0008] What is needed is a process integration methodology to
efficiently embed a NVM cell array with metal gate/high-k
dielectric logic transistors.
BRIEF DESCRIPTION OF THE DRAWINGS
[0009] The present invention is illustrated by way of example and
is not limited by the accompanying figures, in which like
references indicate similar elements. Elements in the figures are
illustrated for simplicity and clarity and have not necessarily
been drawn to scale.
[0010] FIG. 1 is a cross section of a semiconductor device at a
stage in processing according to an embodiment;
[0011] FIG. 2 is a cross section of the semiconductor device of
FIG. 1 at a subsequent stage in processing;
[0012] FIG. 3 is a cross section of the semiconductor device of
FIG. 2 at a subsequent stage in processing;
[0013] FIG. 4 is a portion of the semiconductor device shown in
FIG. 3 in more detail;
[0014] FIG. 5 is a cross section of the semiconductor device of
FIG. 3 at a subsequent stage in processing;
[0015] FIG. 6 is a cross section of the semiconductor device of
FIG. 5 at a subsequent stage in processing;
[0016] FIG. 7 is a cross section of the semiconductor device of
FIG. 6 at a subsequent stage in processing;
[0017] FIG. 8 is a cross section of the semiconductor device of
FIG. 7 at a subsequent stage in processing;
[0018] FIG. 9 is a cross section of the semiconductor device of
FIG. 8 at a subsequent stage in processing;
[0019] FIG. 10 is a cross section of the semiconductor device of
FIG. 9 at a subsequent stage in processing;
[0020] FIG. 11 is a cross section of the semiconductor device of
FIG. 10 at a subsequent stage in processing;
[0021] FIG. 12 is a cross section of the semiconductor device of
FIG. 11 at a subsequent stage in processing;
[0022] FIG. 13 is a cross section of the semiconductor device of
FIG. 12 at a subsequent stage in processing;
[0023] FIG. 14 is a cross section of the semiconductor device of
FIG. 13 at a subsequent stage in processing;
[0024] FIG. 15 is a cross section of the semiconductor device of
FIG. 14 at a subsequent stage in processing;
[0025] FIG. 16 is a cross section of the semiconductor device of
FIG. 15 at a subsequent stage in processing;
[0026] FIG. 17 is a cross section of the semiconductor device of
FIG. 16 at a subsequent stage in processing; and
[0027] FIG. 18 is a cross section of the semiconductor device of
FIG. 17 at a subsequent stage in processing.
DETAILED DESCRIPTION
[0028] In one aspect, an integration of a non-volatile memory (NVM)
cell and a logic transistor efficiently integrates NVM and logic on
a single integrated circuit. This integration utilizes thermal
oxide for the gate dielectric of the select gate and partial
replacement gate to obtain metal gates for the logic. This is
better understood by reference to the drawings and the following
description.
[0029] The semiconductor substrate described herein can be any
semiconductor rsubstrate having a thermally oxidizable top
surface.
[0030] Shown in FIG. 1 is a semiconductor device 10 having a
semiconductor substrate 16, an NVM region 12 in and over a portion
of substrate 16, a logic region 14 in and over a portion of
substrate 16, and a hard mask layer 18 over substrate 16. In and
over the same substrate 16, there may be other regions as well. A
process for forming a single logic transistor and a single NVM cell
will be shown in subsequent figures and are exemplary of other
transistors and memory cells to be formed in those regions. Hard
mask layer 18 may be nitride and may be about 100 Angstroms thick.
Other materials and thicknesses may also be used.
[0031] Shown in FIG. 2 is semiconductor device 10 after removing
hard mask layer 18 from NVM region 12. A mask, not shown, is used
for this etch.
[0032] Shown in FIG. 3 is semiconductor device 10 after depositing
a charge storage layer 20 over NVM region 12 on substrate 16 and
over logic region 14 on hard mask layer 18.
[0033] Shown in FIG. 4 is charge storage layer 20 in more detail.
Charge storage layer 20 has a dielectric layer 22 on substrate 16,
a plurality of nanocrystals 24 on dielectric layer 22 including an
exemplary nanocrystal 28, and a dielectric layer 26 on dielectric
layer 22 and on and around nanocrystals 24. Dielectric layers 22
and 26 are preferably oxide. Dielectric layer 22 is the dielectric
layer through which charge flows to nanocrystals 24 for program as
well as the gate dielectric between nanocrystals 24 and a channel.
Dielectric layer 26 is the dielectric layer through which charge
flows from nanocrystals 24 for erase. Nanocrystals 24 are
preferably silicon in order to be able to withstand a subsequent
thermal oxidation step.
[0034] Shown in FIG. 5 is a semiconductor device after forming a
gate material 30 on charge storage layer 20 in NVM region 12 and
logic region 14. Gate material 30 may have a thickness of about
800-1000 Angstroms. Gate material 30 may be metal which may provide
a benefit over polysilicon. Polysilicon may be used as well. Gate
material 30 may also be a stack of conductive materials that may
include metal and polysilicon.
[0035] Shown in FIG. 6 is semiconductor device 10 after etching
gate material 30 and charge storage layer 20. There need not be any
change to gate material 30 other than patterning it, but the result
is what will be used as a functional structure, control gate 32, in
NVM region 12. Gate material 30, charge storage layer 20, and hard
mask layer 18 are removed from logic region 14 so that a top
surface of substrate 16 will be exposed in logic region 14. The top
portion of substrate 16 is also exposed in NVM region 12 except
where control gate 32 is present.
[0036] Shown in FIG. 7 is semiconductor device 10 after forming
dielectric layer 21 on the exposed portions of NVM region 12 and
logic region 14 and on control gate 32. Dielectric layer 21 on
substrate 16 is thermally grown and may be referenced as a thermal
oxide layer which is an oxide layer grown using heat rather than an
oxide layer that is deposited. Dielectric layer 21 on control gate
is also oxide but is mostly deposited oxide. Thus dielectric layer
21 may be referenced as oxide layer 21. Oxide layer 21 on control
gate 32 is formed by first depositing a conformal oxide layer
followed by an anisotropic etch which forms a sidewall spacer
around control gate 32 and which removes the conformal oxide layer
from substrate 16. A thermal oxidation step is then performed
resulting in oxide layer 21 being grown on substrate 16. This
growing of oxide layer 21 on substrate 16 is at a relatively high
temperature, greater than a temperature which would cause damage to
metal layers if the metal layers had been previously formed. The
result is oxide layer 21 on substrate 16 is high quality and
effective as a gate dielectric for a select gate to be formed.
Oxide layer 21 may be thicker on control gate 32, where it is
nearly all deposited and only slightly grown, than it is on
substrate 16 where it may be only grown. A layer 23 of polysilicon
is formed on oxide layer 21 in NVM region 12 and logic region 14.
Polysilicon layer 23 is thicker than oxide layer 21 but
significantly thinner than the height of control gate 32. Layer 23
functions as a hard mask during processing of logic region 14 and
is particularly important in protecting oxide layer 21 where it is
on substrate 16 and will function as a gate dielectric for the
select gate to be formed.
[0037] Shown in FIG. 8 is semiconductor device 10 after removing
oxide layer 21 and polysilicon layer 23 from logic region 14 and
depositing a high-k dielectric layer 34 and a metal layer 35 that
will function as a work-function-setting layer for a logic
transistor to be formed.
[0038] Shown in FIG. 9 is semiconductor device 10 after removing
high-k dielectric layer 34 and metal layer 35 from NVM region
12.
[0039] Shown in FIG. 10 is semiconductor device 10 after forming a
polysilicon layer 36 which results from depositing a polysilicon
layer that merges with polysilicon layer 23 in NVM region 12 but
simply deposited over metal layer 35 in logic region 14. The result
is that polysilicon layer 36 is thicker in NVM region 12 than it is
over logic region 14.
[0040] Shown in FIG. 11 is semiconductor device 10 with polysilicon
layers 23 and 36 merged into a single layer after performing a
planarization process such as chemical mechanical polishing (CMP)
on layer 36 to leave layer 36 in a planar form having a height
about the same as control gate 32. The CMP process may be preceded
by first depositing a sacrificial layer to support the protrusions
and thereby reduce the likelihood of failures where the protrusions
are.
[0041] Shown in FIG. 12 is semiconductor device 10 after forming
patterned photoresist 38 which has a first portion in NVM region 12
over control gate 32 that has a first sidewall 39 extending away
from a first sidewall 33 of control gate 32 for defining the select
gate. The first portion of patterned photoresist 38 in NVM region
12 has a second sidewall 41 substantially aligned to oxide layer 21
where oxide layer 21 is along a second sidewall 37 of control gate
32. Second sidewall 37 of control gate 32 is opposite first
sidewall 33 of control gate 32. The horizontal thickness of oxide
layer 21 along the sidewalls of control gate 32 is preferably at
least twice the alignment tolerance for the second sidewall 41 of
photoresist 38 in NVM region 12 so that second sidewall 41 of
photoresist 38 in NVM region 12 is neither over control gate 32 nor
over polysilicon layer 36 but only over oxide layer 21 along the
second sidewall 37 of control gate 32. Patterned photoresist 38 has
a second portion in logic region 14 that will be used to define a
gate of a logic transistor.
[0042] Shown in FIG. 13 is semiconductor device 10 after performing
an etch using patterned photoresist 38 as a mask leaving a first
portion of polysilicon layer 36 in NVM portion 12, which is the
select gate and may be referenced as select gate 61, adjacent to
control gate 32 in NVM region 12 and a second portion of
polysilicon layer 36, which may be referenced as dummy gate 63, in
logic region 14. Also removed is the portion of oxide layer 21 that
was not covered by patterned photoresist 38. Oxide layer 21 may
remain over control gate 32. Dummy gate 63 will be replaced by a
metal fill during subsequent processing. In an alternate
embodiment, the steps of patterning the select gate and dummy logic
gate may be done in separate steps.
[0043] Shown in FIG. 14 is semiconductor device 10 after forming
sidewall spacers and performing implants in typical fashion for
forming transistors resulting in a sidewall spacer 40 around the
first portion of polysilicon layer 36 and control gate 32, a
source/drain region 44 in substrate 16 substantially aligned to a
first sidewall of select gate 61, a source/drain region 46
substantially aligned to the second sidewall of control gate 32, a
sidewall spacer 42 around dummy gate 63, a source/drain region 48
substantially aligned to a first sidewall of dummy gate 63, and a
source/drain region 50 substantially aligned to a second sidewall
of dummy gate 63. Subsequent to the source/drain formation, the
gates and source/drain regions may be silicided using conventional
processing. Sidewall spacers 40 and 42 may additionally have a
liner layer between the gate and the spacer. In an alternate
embodiment, source/drain regions 44 and 46 may be formed separately
from source/drain regions 48 and 50.
[0044] Shown in FIG. 15 is semiconductor device 10 after forming an
interlayer dielectric (ILD) 52 by deposition followed by CMP. FIG.
15 thus shows ILD 52 having portions around sidewall spacers 40 and
42. The CMP results in select gate 61, control gate 32 and dummy
gate 63 being exposed. The CMP removes the small gap region that
may form between the top portions of select gate 61 and control
gate 32 during formation of sidewall spacers 40 and 42.
[0045] Shown in FIG. 16 is semiconductor device 10 after forming a
hard mask layer 43 over NVM portion 12 and then removing dummy gate
63. Hard mask layer 43 may comprise silicon nitride. The removal of
dummy gate 63 may be achieved without a mask. Hard mask layer 43
may be formed by a blanket deposition followed by removing the
portion of the blanket deposition over the logic region. The
removal of dummy gate 63 leaves an opening 45 inside sidewall
spacer 42 and the top surface of metal layer 35, which is the
work-function-setting layer, exposed.
[0046] Shown in FIG. 17 is semiconductor device 10 after forming a
gate material 56 that fills opening 45 formed by removing dummy
gate 63 as shown FIG. 16. Gate material 56 may be metal or some
combination of metal and polysilicon.
[0047] Shown in FIG. 18 is semiconductor device 10 after performing
CMP. The result is hard mask layer 43 and gate material 56 are
removed in NVM region 12 and gate material 56 is removed in logic
region 14 over ILD 52. This leaves a logic gate 56 in logic region
14 contained within opening 45 shown in FIG. 16 inside sidewall
spacer 42. This results in a completed NVM cell in NVM region 12
and a completed logic transistor in logic region 14.
[0048] Thus an efficient manner of forming an NVM memory cell and a
logic transistor is achieved in which the gate dielectrics can be
thermally grown or high-k, the gates can be polysilicon or metal,
and the storage layer can be polysilicon or metal nanocrystals. In
an alternate embodiment, the storage layer can be nitride.
[0049] By now it should be apparent there has been disclosed a
method of making a logic transistor in a logic region of a
substrate and a non-volatile memory (NVM) cell in an NVM region of
the substrate. The method includes forming a control gate overlying
a charge storage layer over the substrate in the NVM region. The
method further includes forming a thermally-grown oxygen-containing
dielectric layer on the substrate and the control gate in the NVM
region and on the substrate in the logic region. The method further
includes removing the thermally-grown oxygen-containing dielectric
layer from the logic region. The method further includes forming a
high-k gate dielectric layer over the substrate in the logic
region. The method further includes forming a barrier layer over
the high-k gate dielectric layer in the logic region. The method
further includes forming a polysilicon layer over the
thermally-grown oxygen-containing dielectric layer in the NVM
region and over the barrier layer in the logic region. The method
further includes planarizing the polysilicon layer. The method
further includes forming a first masking layer over the polysilicon
layer and control gate in the NVM region, wherein the first masking
layer defines a select gate location laterally adjacent the control
gate in the NVM region. The method further includes forming a
second masking layer over the polysilicon layer in the logic
region, wherein the second masking layer defines a logic gate
location in the logic region. The method further includes using the
first masking layer to remove exposed portions of the polysilicon
layer in the NVM region, wherein a first portion of the polysilicon
layer remains at the select gate location to form a select gate.
The method further includes using the second masking layer to
remove exposed portions of the polysilicon layer in the logic
region, wherein a second portion of the polysilicon layer remains
at the logic gate location. The method further includes forming a
dielectric layer in the NVM region and the logic region, wherein
the dielectric layer is formed over the select gate, the control
gate, and the second portion of the polysilicon layer. The method
further includes planarizing the dielectric layer to expose the
second portion of the polysilicon layer. The method further
includes removing the second portion of the polysilicon layer to
result in an opening at the logic gate location, wherein the
opening exposes the barrier layer. The method may have a further
characterization by which the step of forming the first masking
layer is performed such that the first masking layer is directly
over the control gate, and a first edge of the first masking layer
extends laterally from the control gate onto the polysilicon layer
to define the select gate location laterally adjacent the control
gate in the NVM region. The method may further include forming a
protection layer over the select gate and the control gate in the
NVM region, wherein the protection layer exposes the logic region.
The method may further include, prior to the step of forming the
thermally-grown oxygen-containing dielectric layer, forming an
oxide spacer on a sidewall of the control gate. The method may have
a further characterization by which the first masking layer and the
second masking layer are portions of a same patterned masking
layer, and wherein the steps of using the first masking layer to
remove exposed portions of the polysilicon layer in the NVM region
and using the second masking layer to remove exposed portions of
the polysilicon layer in the logic region are performed
simultaneously. The method may have a further characterization by
which the barrier layer comprises a work-function-setting metal.
The method may have a further characterization by which wherein the
step of forming the control gate overlying the charge storage layer
over the substrate in the NVM region includes forming the charge
storage layer over the substrate in the NVM region and the logic
region; forming a second polysilicon layer over the charge storage
layer in the NVM region and the logic region; and patterning the
second polysilicon layer and the charge storage layer to form the
control gate in the NVM region and to remove the second polysilicon
layer and the charge storage layer from the logic region. The
method may have a further characterization by which after the
select gate is formed, a portion of the thermally-grown
oxygen-containing dielectric layer is located between the select
gate and the control gate. The method may have a further
characterization by which after the steps of using the first and
second masking layers to remove exposed portions of the polysilicon
layer in the NVM region and the logic region, the method further
includes forming a first source/drain region in the substrate
laterally adjacent the select gate and a second source/drain region
in the substrate laterally adjacent the control gate, such that the
select gate and the control gate are located between the first and
second source/drain regions; and forming a third source/drain
region in the substrate laterally adjacent a first sidewall of the
second portion of the polysilicon layer and a fourth source/drain
region in the substrate laterally adjacent a second sidewall of the
second portion of the polysilicon layer. The method may have a
further characterization by which, after the step of using the
first and second masking layers to remove exposed portions of the
polysilicon layer in the NVM region and the logic region, the
method further includes forming a first sidewall spacer surrounding
outer sidewalls of the select gate and the control gate and a
second sidewall spacer surrounding the second portion of the
polysilicon layer. The method may further include, prior to the
step of removing the thermally-grown oxygen-containing dielectric
layer from the logic region, forming a second polysilicon layer
over the thermally-grown oxygen-containing dielectric layer,
wherein the polysilicon layer is formed over the second polysilicon
layer, and wherein the step of removing the thermally-grown
oxygen-containing dielectric layer further comprises removing the
second polysilicon layer from the logic region. The method may have
a further characterization by which the steps of forming the high-k
gate dielectric layer and forming the barrier layer include forming
the high-k gate dielectric layer over the second polysilicon layer
in the NVM region and over the substrate in the logic region;
forming the barrier layer over the high-k gate dielectric layer in
the NVM region and in the logic region; and removing the high-k
gate dielectric layer and the barrier layer from the NVM region.
The method may have a further characterization by which the charge
storage layer comprises at least one of nanocrystals or a nitride.
The method may have a further characterization by which after the
step of removing the second portion of the polysilicon layer to
result in the opening at the logic gate location, the method
further includes forming a logic gate layer over the protection
layer in the NVM region and within the opening on the barrier layer
in the logic region; and planarizing the logic gate layer to result
in a logic gate in the logic gate location, wherein the planarizing
removes the protection layer from the NVM region.
[0050] Also described is a method of making a logic transistor in a
logic region of a substrate and a non-volatile memory (NVM) cell in
an NVM region of the substrate. The method includes forming a
control gate overlying a charge storage layer over the substrate in
the NVM region, wherein the control gate comprises polysilicon. The
method further includes forming an oxide spacer on a sidewall of
the control gate. The method further includes thermally growing an
oxygen-containing dielectric layer on the substrate in the NVM
region, on the control gate, and on the substrate in the logic
region. The method further includes removing the oxygen-containing
dielectric layer from the logic region. The method further includes
forming a high-k gate dielectric layer over the substrate in the
logic region. The method further includes forming a barrier layer
over the high-k gate dielectric layer in the logic region. The
method further includes forming a polysilicon layer over the
oxygen-containing dielectric layer in the NVM region and over the
barrier layer in the logic region. The method further includes
planarizing the polysilicon layer, wherein the oxygen-containing
dielectric layer comprises a sidewall portion located along a
sidewall of the control gate. The method further includes forming a
first masking layer over the polysilicon layer and control gate in
the NVM region, wherein the first masking layer defines a select
gate location laterally adjacent the control gate in the NVM
region, wherein the first masking layer is directly over the
control gate, and a first edge of the first masking layer extends
laterally from the control gate onto the polysilicon layer to
define the select gate location laterally adjacent the control gate
in the NVM region. The method further includes forming a second
masking layer over the polysilicon layer in the logic region,
wherein the second masking layer defines a logic gate location in
the logic region. The method further includes using the first
masking layer to remove exposed portions of the polysilicon layer
in the NVM region, wherein a first portion of the polysilicon layer
remains at the select gate location to form a select gate. The
method further includes using the second masking layer to remove
exposed portions of the polysilicon layer in the logic region,
wherein a second portion of the polysilicon layer remains at the
logic gate location. The method further includes forming a
dielectric layer in the NVM region and the logic region, wherein
the dielectric layer is formed over the select gate, the control
gate, and the second portion of the polysilicon layer. The method
further includes planarizing the dielectric layer to expose the
second portion of the polysilicon layer. The method further
includes forming a protection layer over the select gate and the
control gate in the NVM region, wherein the protection layer
exposes the logic region. The method further includes removing the
second portion of the polysilicon layer to result in an opening at
the logic gate location, wherein the opening exposes the barrier
layer. The method further includes forming a logic gate layer over
the protection layer in the NVM region and within the opening on
the barrier layer in the logic region. The method further includes
planarizing the logic gate layer to result in a logic gate in the
logic gate location, wherein the planarizing removes the protection
layer from the NVM region. The method may further include prior to
the step of removing the oxygen-containing dielectric layer from
the logic region, forming a second polysilicon layer over the
thermally-grown oxygen-containing dielectric layer, and wherein the
step of removing the oxygen-containing dielectric layer further
comprises removing the second polysilicon layer from the logic
region. The method may have a further characterization by which the
steps of forming the high-k gate dielectric layer and forming the
barrier layer include forming the high-k gate dielectric layer over
the second polysilicon layer in the NVM region and over the
substrate in the logic region; forming the barrier layer over the
high-k gate dielectric layer in the NVM region and in the logic
region; and removing the high-k gate dielectric layer and the
barrier layer from the NVM region. The method may have a further
characterization by which wherein after the step of using the
patterned masking layer to remove exposed portions of the
polysilicon layer and prior to the step of forming the protection
layer in the NVM region and the logic region, the method further
includes forming a first source/drain region in the substrate
laterally adjacent the select gate and a second source/drain region
in the substrate laterally adjacent the control gate, such that the
select gate and the control gate are located between the first and
second source/drain regions; forming a third source/drain region in
the substrate laterally adjacent a first sidewall of the second
portion of the polysilicon layer and a fourth source/drain region
in the substrate laterally adjacent a second sidewall of the second
portion of the polysilicon layer; and forming a first sidewall
spacer surrounding outer sidewalls of the select gate and the
control gate. The method may have a further characterization by
which the barrier layer comprises a work-function-setting
metal.
[0051] Disclosed also is a method of making a logic transistor in a
logic region of a substrate and a non-volatile memory (NVM) cell in
an NVM region of the substrate. The method includes forming a
control gate overlying a charge storage layer over the substrate in
the NVM region, wherein the control gate comprises polysilicon and
the charge storage layer comprises at least one of nanocrystals or
a nitride. The method further includes. The method further includes
forming a thermally-grown oxygen-containing dielectric layer on the
substrate and the control gate in the NVM region and on the
substrate in the logic region. The method further includes forming
a first polysilicon layer over the thermally-grown
oxygen-containing dielectric layer in the NVM region and the logic
region. The method further includes removing the thermally-grown
oxygen-containing dielectric layer and the first polysilicon layer
from the logic region. The method further includes forming a high-k
gate dielectric layer over the first polysilicon layer in the NVM
region and over the substrate in the logic region. The method
further includes forming a barrier layer over the high-k gate
dielectric layer in the NVM region and in the logic region. The
method further includes removing the high-k gate dielectric layer
and the barrier layer from the NVM region; forming a second
polysilicon layer over the first polysilicon layer in the NVM
region and over the barrier layer in the logic region. The method
further includes planarizing the second polysilicon layer, wherein
the thermally-grown oxygen-containing dielectric layer comprises a
sidewall portion located along a sidewall of the control gate. The
method further includes forming a first masking layer over the
polysilicon layer and control gate in the NVM region, wherein the
first masking layer defines a select gate location laterally
adjacent the control gate in the NVM region, wherein the first
masking layer is directly over the control gate, and a first edge
of the first masking layer extends laterally from the control gate
onto the second polysilicon layer to define the select gate
location laterally adjacent the control gate in the NVM region. The
method further includes forming a second masking layer over the
second polysilicon layer in the logic region, wherein the second
masking layer defines a logic gate location in the logic region.
The method further includes using the first masking layer to remove
exposed portions of the second polysilicon layer in the NVM region,
wherein a first portion of the second polysilicon layer remains at
the select gate location to form a select gate. The method further
includes using the second masking layer to remove exposed portions
of the second polysilicon layer in the logic region, wherein a
second portion of the second polysilicon layer remains at the logic
gate location. The method further includes forming a dielectric
layer in the NVM region and the logic region, wherein the
dielectric layer is formed over the select gate, the control gate,
and the second portion of the second polysilicon layer. The method
further includes planarizing the dielectric layer to expose the
second portion of the second polysilicon layer. The method further
includes forming a protection layer over the select gate and the
control gate in the NVM region, wherein the protection layer
exposes the logic region. The method further includes removing the
second portion of the second polysilicon layer to result in an
opening at the logic gate location, wherein the opening exposes the
barrier layer. The method further includes forming a logic gate
layer over the protection layer in the NVM region and within the
opening on the barrier layer in the logic region. The method
further includes planarizing the logic gate layer to result in a
logic gate in the logic gate location, wherein the planarizing
removes the protection layer from the NVM region.
[0052] Although the invention is described herein with reference to
specific embodiments, various modifications and changes can be made
without departing from the scope of the present invention as set
forth in the claims below. For example, the various dimensions may
be different than those described. Accordingly, the specification
and figures are to be regarded in an illustrative rather than a
restrictive sense, and all such modifications are intended to be
included within the scope of the present invention. Any benefits,
advantages, or solutions to problems that are described herein with
regard to specific embodiments are not intended to be construed as
a critical, required, or essential feature or element of any or all
the claims.
[0053] Furthermore, the terms "a" or "an," as used herein, are
defined as one or more than one. Also, the use of introductory
phrases such as "at least one" and "one or more" in the claims
should not be construed to imply that the introduction of another
claim element by the indefinite articles "a" or "an" limits any
particular claim containing such introduced claim element to
inventions containing only one such element, even when the same
claim includes the introductory phrases "one or more" or "at least
one" and indefinite articles such as "a" or "an." The same holds
true for the use of definite articles.
[0054] Unless stated otherwise, terms such as "first" and "second"
are used to arbitrarily distinguish between the elements such terms
describe. Thus, these terms are not necessarily intended to
indicate temporal or other prioritization of such elements.
* * * * *