U.S. patent application number 13/535059 was filed with the patent office on 2013-08-22 for high current, low equivalent series resistance printed circuit board coil for power transfer application.
This patent application is currently assigned to FUTUREWEI TECHNOLOGIES, INC.. The applicant listed for this patent is Jorge Zabaco. Invention is credited to Jorge Zabaco.
Application Number | 20130214890 13/535059 |
Document ID | / |
Family ID | 48981821 |
Filed Date | 2013-08-22 |
United States Patent
Application |
20130214890 |
Kind Code |
A1 |
Zabaco; Jorge |
August 22, 2013 |
High Current, Low Equivalent Series Resistance Printed Circuit
Board Coil for Power Transfer Application
Abstract
A method for fabricating an electric coil on a circuit board
comprising fabricating on the circuit board a first coil layer
comprising a coil trace and a plurality of vias distributed along
the length of the coil trace, and overlaying a second coil layer on
the first coil layer, wherein the vias of the first coil layer join
the first coil layer and the second coil layer.
Inventors: |
Zabaco; Jorge; (San Diego,
CA) |
|
Applicant: |
Name |
City |
State |
Country |
Type |
Zabaco; Jorge |
San Diego |
CA |
US |
|
|
Assignee: |
FUTUREWEI TECHNOLOGIES,
INC.
Plano
TX
|
Family ID: |
48981821 |
Appl. No.: |
13/535059 |
Filed: |
June 27, 2012 |
Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
|
|
61600969 |
Feb 20, 2012 |
|
|
|
Current U.S.
Class: |
336/200 ;
29/602.1 |
Current CPC
Class: |
H01F 2017/002 20130101;
H02J 50/12 20160201; H01F 27/2804 20130101; H01F 17/0013 20130101;
Y10T 29/4902 20150115; H02J 5/005 20130101; H01F 38/14 20130101;
H04B 5/0037 20130101; H01F 2027/2809 20130101; H01F 41/041
20130101; H02J 7/025 20130101 |
Class at
Publication: |
336/200 ;
29/602.1 |
International
Class: |
H05K 3/42 20060101
H05K003/42; H01F 5/00 20060101 H01F005/00; H01F 41/04 20060101
H01F041/04; H04B 5/00 20060101 H04B005/00 |
Claims
1. A method for fabricating an electric coil on a circuit board
comprising: fabricating on the circuit board a first coil layer
comprising a coil trace and a plurality of vias distributed along
the length of the coil trace; and overlaying a second coil layer on
the first coil layer, wherein the vias of the first coil layer join
the first coil layer and the second coil layer.
2. The method of claim 1, wherein the vias are distributed
substantially across the entire coil trace to achieve higher
current capability, lower equivalent series resistance (ESR), or
both for the electric coil.
3. The method of claim 1, wherein the first coil layer and the
second coil layer are overlaid on the circuit board, and wherein
additional circuit components are integrated, overlaid, or both
with the first coil layer and the second coil layer on the circuit
board.
4. The method of claim 1, wherein the second coil layer comprises a
second coil trace and a plurality of second vias.
5. The method of claim 4, wherein the second vias join the second
coil trace to the coil trace, the vias, or both.
6. The method of claim 4 further comprising overlaying a third coil
layer on the second coil layer, wherein the second vias of the
second coil layer join the second coil layer and the third coil
layer.
7. The method of claim 4, wherein the second coil trace mirrors the
coil trace.
8. The method of claim 1 further comprising overlaying one or more
additional coil layers on the first coil layer and the second coil
layer to meet current capability, equivalent series resistance
(ESR), or both requirements for the electric coil.
9. A method for reducing an overall thickness of a multilayer coil
for wireless electrical power transfer, comprising: fabricating a
first coil layer comprising a first winding trace; overlaying and
distributing a plurality of vias across the first coil layer; and
overlaying on the vias a second coil layer comprising a second
winding trace substantially similar to the winding trace, wherein
the spaces between the vias are determined to increase the vias
coverage of the surfaces of the first coil layer and the second
coil layer.
10. The method of claim 9, wherein the vias between the first coil
layer and the second coil layer are distributed substantially
evenly across the surfaces of the first coil layer and the second
coil layer.
11. The method of claim 9 further comprising: overlaying and
distributing a plurality of second vias across the second coil
layer and overlaying on the second vias a third coil layer
comprising a third winding trace substantially similar to the
winding trace, wherein the spaces between the second vias are
reduced to increase the second vias coverage of the surfaces of the
second coil layer and the third coil layer.
12. The method of claim 11, wherein the vias between the first coil
layer and the second coil layer and the second vias between the
second coil layer and the third coil layer are distributed
similarly or differently to increase overall current flow and
series resistance in the multilayer coil.
13. The method of claim 9, wherein the vias are overlaid across
substantially the entire surfaces of the first coil layer and the
second coil layer to increase current flow between the first coil
layer and the second coil layer, reduce equivalent series
resistance (ESR), and increase power transfer in comparison to
overlaying fewer vias at some portions of the surfaces of the first
coil layer and the second coil layer.
14. The method of claim 9, wherein the first coil layer and the
second coil layer have a thickness determined to meet a desired
equivalent series resistance (ESR) for the multilayer coil and to
allow using the multilayer coil for a wireless charging component
in a relatively thin handheld device.
15. The method of claim 9, wherein the vias are fabricated by
patterning the vias on the first coil layer using lithography and
then etching.
16. The method of claim 9, wherein the spaces between the vias are
reduced as much as allowed by the PCB fabrication to increase the
surface coverage of the first coil layer and the second coil layer
by the vias.
17. The method of claim 9, wherein the vias have about the same
size, surface, and dimensions that are designed to determine a
quantity of vias that cover the surfaces of the first coil layer
and the second coil layer.
18. The method of claim 9, wherein at least some of the vias have
different sizes that are determined to increase current flow and
series resistance in the multilayer coil.
19. An apparatus for a multilayer printed circuit board (PCB) coil,
comprising: a first coil layer of a PCB; a plurality of vias
coupled to and distributed to cover substantially the surface of
the first coil layer within the PCB; and a second coil layer of the
PCB and coupled to the vias to cover substantially the surface of
the second coil layer, wherein the vias are positioned between the
first coil layer and the second coil layer and enable substantially
high current and low equivalent series resistance (ESR) for the
multilayer PCB coil.
20. The apparatus of claim 19 further comprising one or more other
circuit components integrated with the first coil layer and the
second coil layer on the PCB.
21. The apparatus of claim 19, wherein the multilayer PCB coil is a
component used in a wireless charging device.
22. The apparatus of claim 19, wherein the multilayer PCB coil is a
component used in a near-field transmission device.
23. The apparatus of claim 19, wherein the vias have a cylindrical
shape and are vertical with respect to the surfaces of the first
coil layer and the second coil layer.
Description
CROSS-REFERENCE TO RELATED APPLICATIONS
[0001] The present application claims the benefit of U.S.
Provisional Patent Application No. 61/600,969 filed Feb. 20, 2012
by Jorge Zabaco and entitled "Clever Implementation of Wireless
Charging Coil Using Standard Printed Circuit Board Technology,"
which is incorporated herein by reference as if reproduced in its
entirety.
STATEMENT REGARDING FEDERALLY SPONSORED RESEARCH OR DEVELOPMENT
[0002] Not applicable.
REFERENCE TO A MICROFICHE APPENDIX
[0003] Not applicable.
BACKGROUND
[0004] An electric coil (or simply a "coil") is formed by winding a
conductor (usually an insulated solid copper wire) around a
non-conductive core to create an inductor. One loop of wire is
referred to as a turn, and a coil consists of one or more turns. In
electronic circuits, electrical connection terminals referred to as
taps are connected to a coil. A completed coil assembly with taps
is often called a winding. Coils are used in different
applications, such as in power transformers and electromagnets.
Coils are also used in inductive charging and resonant inductive
coupling applications, where energy is transferred between two
objects through inductive coupling, e.g., without a conducting
medium between the two objects. In inductive charging, there is a
relatively small gap between two coils, which are located on the
sender and receiver sides of the energy, e.g., within two
respective devices. Inductive charging is considered a
short-distance "wireless" energy transfer, since charging is
achieved without using wires between the two devices. For example,
inductive charging applications include wireless battery charging
devices. Resonant inductive coupling is the near field wireless
transmission of electrical energy between two coils that are tuned
to resonate at the same frequency. Resonant inductive coupling
applications can achieve longer energy transfer distances than
inductive charging applications. For example, resonant inductive
coupling applications include near-field wireless communications,
such as radio-frequency identification (RFID) devices.
SUMMARY
[0005] In an embodiment, the disclosure includes a method for
fabricating an electric coil on a circuit board comprising
fabricating on the circuit board a first coil layer comprising a
coil trace and a plurality of vias distributed along the length of
the coil trace, and overlaying a second coil layer on the first
coil layer, wherein the vias of the first coil layer join the first
coil layer and the second coil layer.
[0006] In another embodiment, the disclosure includes a method for
reducing an overall thickness of a multilayer coil for wireless
electrical power transfer, comprising fabricating a first coil
layer comprising a first winding trace, overlaying and distributing
a plurality of vias across the first coil layer, and overlaying on
the vias a second coil layer comprising a second winding trace
substantially similar to the winding trace, wherein the spaces
between the vias are determined to increase the vias coverage of
the surfaces of the first coil layer and the second coil layer.
[0007] In yet another embodiment, the disclosure includes an
apparatus for a multilayer PCB coil, comprising a first coil layer
of a PCB, a plurality of vias coupled to and distributed to cover
substantially the surface of the first coil layer within the PCB,
and a second coil layer of the PCB and coupled to the vias to cover
substantially the surface of the second coil layer, wherein the
vias are positioned between the first coil layer and the second
coil layer and enable substantially high current and low equivalent
series resistance (ESR) for the multilayer PCB coil.
[0008] These and other features will be more clearly understood
from the following detailed description taken in conjunction with
the accompanying drawings and claims.
BRIEF DESCRIPTION OF THE DRAWINGS
[0009] For a more complete understanding of this disclosure,
reference is now made to the following brief description, taken in
connection with the accompanying drawings and detailed description,
wherein like reference numerals represent like parts.
[0010] FIG. 1 is a top view of a first coil layer of the multicore
design.
[0011] FIG. 2 is a top view of a second coil layer of the multicore
design.
[0012] FIG. 3 is a cross sectional view of an embodiment of a
multicore design of FIG. 2 taken along line 3-3.
[0013] FIG. 4 is a flowchart of an embodiment of a multilayer coil
fabrication method.
[0014] FIG. 5 is a flowchart of another embodiment of a multilayer
coil fabrication method.
[0015] FIG. 6 is a schematic diagram of an embodiment of a handheld
device comprising a multilayer coil design.
DETAILED DESCRIPTION
[0016] It should be understood at the outset that although an
illustrative implementation of one or more embodiments are provided
below, the disclosed systems and/or methods may be implemented
using any number of techniques, whether currently known or in
existence. The disclosure should in no way be limited to the
illustrative implementations, drawings, and techniques illustrated
below, including the exemplary designs and implementations
illustrated and described herein, but may be modified within the
scope of the appended claims along with their full scope of
equivalents.
[0017] Wireless charging coils that are used in wireless charging
components may require relatively high current capabilities and
relatively low ESR. The high current and low ESR increases power
transfer efficiency of the coil. For example, wireless charging
coils may be used in inductive charging components for mobile
devices (e.g., smartphones) and mobile computers (e.g., laptops and
tablets). To meet such requirements, the standard method to
fabricate such coils may be based on using and soldering electric
or conductive wires onto electric circuit boards of the devices.
However, using electric wires to construct charging coils may have
limits on the current capability and low ESR resistance that may be
achieved, e.g., due to the dimensions and materials involved. For
example, to achieve the required high current capabilities and
relatively low ESR resistance for wireless (or inductive) charging,
coils made out of wires may require a minimum thickness that may
not be suitable for some mobile or handheld devices, such as
relatively flat (thinner) smartphones and tablets. A more promising
coil design to increase current capability and reduce ESR may be
based on integrated circuit fabrication methods, such as using PCB
technology and related fabrication processes. Such charging coils
may be used in relatively flat mobile devices that have limits on
device thickness. The PCB may be a non-conductive substrate that
mechanically supports and electrically connects electronic or
electrical components using conductive pathways, tracks, or traces,
e.g., that may be etched from copper sheets laminated onto the
substrate. The PCB may also be coated for protecting the
components, e.g., using wax, silicone rubber, polyurethane,
acrylic, or epoxy.
[0018] Disclosed herein is a fabrication method and apparatus for a
multilayer coil design. The method may comprise fabricating
multiple coil layers on a PCB and joining the coil layers together
using a plurality of vias. The vias may be any structures/material
used as vertical electrical connections between different layers of
conductors in a physical electronic circuit. The electric coil
design may be used for wireless charging application and the method
may use PCB technology and fabrication processes. The method may
enable and facilitate fabrication of thinner coil layers on a PCB,
where the coil traces may be fabricated using available circuit
fabrication processes and may be made thinner than typical electric
wires. This may also allow the integration of the coil design with
other circuit components of a device. The vias that join or link
the coil layers may be distributed along the length of the traces
of the coil layers to enhance the current capability and lower the
ESR of the entire coil design (the multilayer coil), and hence
obtain an effective wireless charging coil. The high current and
low ESR coil may also be suitable for near-field wireless antenna
designs. For example, the coil may be a component of a near-field
wireless antenna design in a RFID device. The method and apparatus
may also be used in other coil applications or devices that require
efficient power transfer and relatively thin design, e.g., since
the multilayer coil may be integrated with other circuit components
and hence allow a more compact design.
[0019] The thinner multilayer coil design may be suitable for
portable devices, such smartphones, tablets, and laptops that have
thinner designs. The coil fabrication method may have reduced cost
since PCB technology is mature and has lower cost in comparison to
other fabrication technologies, for example in comparison to
constructing coil wires and then soldering the coil wires to a PCB
comprising wireless charging circuitry. The electric coil design
may also be easier to manufacture using PCB technology, where a
single PCB may be needed. Using a single PCB may also eliminate the
need to solder the coil to another PCB comprising the wireless
charging circuitry. Further, using a single board, where the coil
and the circuitry may be integrated during fabrication, may be more
reliable than having the two components (the coil and the wireless
charging circuitry) soldered to one another.
[0020] FIGS. 1-3 illustrate an embodiment of a multilayer coil
design 100, which may be fabricated using PCB technology. The
multilayer coil design 100 may comprise a plurality of coil layers
fabricated on a PCB 190. The PCB 190 may be a non-conductive or
semiconductor substrate, e.g., a silicon board. The number of coil
layers may be determined such that to achieve the required current
capability and ESR for the coil application. To achieve relatively
high current capabilities and relatively low ESR for wireless
charging or near-field communication applications, multiple coil
layers may be fabricated and overlaid using PCB technology and
fabrication processes. The coil layers may comprise a first coil
layer 102 positioned on top of the PCB 190 and a second coil layer
104 overlaid on the first coil layer 102. FIG. 1 illustrates a top
view of the first coil layer 102 and FIG. 3 shows a top view of the
second coil layer 104. FIG. 3 shows a cross sectional view of the
multilayer coil design 100 taken along line 3-3 of FIG. 2. The
multilayer coil design 100 may also comprise a plurality of vias
108 positioned between the first coil layer 102 and the second coil
layer 104. The first coil layer 102, the second coil layer 104, and
the vias 108 may be fabricated using lithography, etching, and
deposition processes in any suitable combination.
[0021] The first coil layer 102, the second coil layer 104, and
optionally any additional number of overlaid layers, which may have
substantially similar patterns, may be combined on the PCB 190 into
a coil design that achieves a required current capability and ESR
for an intended application, e.g., a wireless charging or
near-field communications device or component. The first coil layer
102 and the second coil layer 104 may have a substantially similar
pattern that includes a winding trace 106. The winding traces of
the coil layers may be shaped in a coil pattern. Other suitable
patterns that have a winding or coil pattern may also be used. A
coil pattern (or a winding trace pattern) may be designed in a
first layer, e.g., the first coil layer 102, and then copied or
mirrored to a second overlaid layer, e.g., the second coil layer
104, or as many additional overlaid layers as needed to meet
current, ESR, and/or impedance required for the wireless charging
or near-field communication application. Other design criteria may
also be met using the fabrication method and the coil layers
design, such as dimension criteria and/or other electric properties
requirements. The coil layers may be overlaid (on the same PCB) and
combined to form a coil design or a final coil structure that meets
the required criteria. For instance, increasing the number of
layers may increase the power transfer capability of the multilayer
coil design 100. The number and dimensions of the multilayer coil
may also be determined to meet a thickness (height of coil layers)
requirement for thin portable devices (e.g., smartphones or
tablets).
[0022] Specifically, to increase current and reduce ESR in the
multilayer coil design 100, the coil layers may be joined or
otherwise electrically connected using the vias 108, which may be
distributed throughout the coil pattern. The vias 108 may have
cylindrical or other suitable shapes, which may be vertical with
respect to the coil layers (as shown in FIG. 1), extend between
adjacent coil layers, and connect the facing surfaces (the traces
106) of the adjacent coil layers. For instance, the vias 108 may be
shaped as solid circles distributed to cover substantially the coil
pattern (trace 106) of the first coil layer 102, as shown in FIG.
2. A plurality of additional vias 108 may similarly be distributed
across the trace 106 of the second coil layer 104 (as shown in FIG.
3), for instance if a third coil layer (not shown) is overlaid on
the second coil layer 104 to connect the second coil layer 104 and
the third coil layer. The vias 108 may comprise conducting material
that joins (electrically) the different coil layers with each other
and allows current to flow throughout the multiple coil layers. For
instance, the vias 108 may be composed of the same material of the
traces of the coil layers. Increasing the number of vias 108 and
distributing the vias 108 substantially entirely across two
adjacent coil surfaces may increase the current flow between the
two adjacent coil traces 106 and hence reduce ESR for the
multilayer coil design 100, e.g., in comparison to distributing
fewer vias at some portions of the coil surfaces.
[0023] Further, the relatively thin coil pattern at each layer may
reduce the overall series resistance (the ESR) of the multilayer
coil design 100. For example, a coil design comprising two coil
layers with traces of about 25 micrometers thickness may have an
overall series resistance of about 0.35 ohms or less. The coil
traces or layers may have about the same thickness, which may be
determined to meet a desired ESR for the multilayer coil design
100. Using multiple layers of coil, which are coupled to each other
using the vias 108, may also reduce the width of the multilayer
coil design 100, since the coil conducting material (trace
material) may be layered in height (along the thickness of the PCB)
to occupy a smaller area and achieve about the same inductive
property. For example, overlaying a plurality of substantially
similar coil traces reduces the overall width of the coil traces in
the PCB layers in comparison to fabricating only one coil trace
that has substantially the same thickness of one of the overlaid
coil traces. The reduced overall width of the coil design may allow
using the multilayer coil structure in compact devises, such as
handheld devices.
[0024] The coil traces 106 and the vias 108 may be aligned
properly, e.g., during fabrication, to ensure proper joining of the
multiple coil layers. The coil layers may be fabricated and
overlaid on the same board using PCB technology and fabrication
processes that may be repeated as necessary to construct each
layer. Each layer may comprise a coil patterned obtained using
traces (e.g., instead of soldiering wires). The traces 106 may
comprise electrically one or more conductive materials, such as
copper, gold, aluminum, silver, other conductors, or combinations
thereof and may be surrounded by non-conductive material such as
any dielectric material suitable for PCB fabrication. The multiple
layers may also be integrated or overplayed with other circuit
components 180 (e.g., charging or wireless transmission circuitry
components) on the same board. The other circuit components 180 may
be fabricated between or adjacent to the coil layers on the PCB
190.
[0025] In one scenario of the fabrication process, a dielectric may
be first deposited or sputtered on the PCB 190. For each layer, the
trace 106 may be patterned and then etched. The etched patterns may
then be filled with electrically conducting material using
deposition. The coil layers may be fabricated in similar manner,
e.g., using the same patterns, and overlaid accordingly to obtain
an overlay of coil patterns (traces 106). The vias 108 between two
coil layers may be fabricated via deposition, patterning, etching,
and optionally other necessary processes as part of the fabrication
step of one of the coil layers (e.g., the bottom coil layer),
during the fabrication steps of the two adjacent coil layers, as a
separate fabrication step from the coil layers, or combinations
thereof. For instance, the vias 108 may be fabricated by patterning
the vias 108 on the traces 106 using lithography and then etching.
Deposition may be achieved using any vacuum deposition procedures
or technologies. The trace 106 may be patterned using lithography
(e.g., photolithography, electronic beam lithography, or other
lithography technology) or other suitable circuit patterning means
(e.g., imprinting). The patterned structure may be etched, e.g.,
using chemical etching, gas etching, plasma, or other suitable
means. The other circuit components 180 may also be fabricated on
the PCB 190 and integrated with the coil design or structure.
[0026] FIG. 4 illustrates an embodiment of a multilayer coil
fabrication method 400 for obtaining a relatively thin coil design
with high current and low ESR, such as the multilayer coil design
100, using PCB technology. At block 402, a coil layer may be
fabricated comprising a plurality of vias distributed along the
length of the coil layer and/or cover a substantial portion of the
surface of the coil layer, e.g., the coil trace. The vias may be
distributed across the coil pattern or traces and may be positioned
to optimize or improve current flow and series resistance. For
instance, increasing the number of vias on the coil surface and
distributing or arranging the vias proportionally or evenly across
the entire surface may increase current flow and reduce resistance
at the coil layer. The vias may be distributed along the length of
the coil trace to cover about the entire surface except for the
spaces between the vias. The spaces between the vias may be
arranged to be as small as allowed by the fabrication process to
increase the surface coverage of the coil trace by the vias. In an
embodiment, the individual vias may have about the same size,
surface, and/or dimensions, which may determine the quantity of
vias that cover the surface of the coil trace. For example,
increasing the surface of the individual vias may reduce the total
number of vias on the surface of the coil trace. Alternatively,
reducing the surface of the individual vias may increase the total
number of vias on the surface of the coil trace. In another
embodiment, at least some of the vias may have different sizes and
surfaces to optimize or increase current flow and series
resistance.
[0027] At block 404 an additional coil layer may be overlaid on the
coil layer such that the vias of the coil layer join (connect) the
coil layer and the additional coil layer. The additional coil layer
pattern (or trace) may be substantially similar to the coil layer
pattern and the two coil layers may be overlaid to overlap
completely or substantially. The additional coil layer may also
comprise a plurality of additional vias that may join the
additional coil layer to the coil layer, the vias of the coil
layer, or to additional overlaid coil layers. The blocks 402 and
404 may be repeated (indicated by the dashed line arrows in FIG. 4)
as needed to establish as many coil layers required to meet the
current capabilities and series resistance for the entire coil
design.
[0028] FIG. 5 illustrates an embodiment of another multilayer coil
fabrication method 500 for obtaining a relatively thin coil design
with high current and low ESR, such as the multilayer coil design
100. The method 500 may begin at block 502, where a first coil
layer comprising a first winding trace may be fabricated, e.g., on
a PCB, any other circuit board, a silicon substrate, or a
silicon/semiconductor wafer. At block 504, a plurality of vias may
be overlaid and distributed across the first coil layer. The vias
may be distributed to cover substantially the trace surface along
the length of the entire winding trace. At block 506, second coil
layer comprising a second winding trace substantially similar to
the winding trace may be overlaid on the vias. As such, the vias
may couple or join the second coil layer to the first coil
layer.
[0029] At bock 508, the method 500 may determine whether more coil
layers are needed to meet coil design requirements, such as
current, resistance, thickness, size, and/or other electrical and
physical properties. If more coil layers are needed, the method 500
may proceed to block 510. Otherwise, the method 500 may end. At
block 510, a plurality of additional vias may be overlaid and
distributed across the last overlaid coil layer, e.g., the second
coil layer. The additional vias may be distributed on the second
winding trace substantially similar to the vias across the first
winding trace. In some scenarios, the first winding trace and the
second winding trace may be distributed differently across the
corresponding surface (coil layers) to optimize current flow and/or
ESR for the entire multilayer coil design. At block 512, an
additional coil layer comprising an additional winding trace
substantially similar to the winding trace may be overlaid on the
additional vias. As such, the additional vias may couple or join
the additional coil layer to the previously fabricated and overlaid
coil layers to achieve a multilayer coil design with the desired
properties.
[0030] FIG. 6. is a schematic diagram of an embodiment of a
handheld device 600 that may comprise a multilayer coil design,
e.g., the multilayer coil design 100. The handheld device 600 may
be a smartphone that comprises a wireless charging component (not
shown), e.g., a wireless charging circuit that includes the
multilayer coil design and may be used for charging a battery (not
shown) of the smartphone. For example, the handheld device 600 may
be positioned near a charging station comprising an inductive
charging coil, thereby charging the handheld device 600. The
smartphone may be a relatively thin smartphone (in comparison to
smartphone device standards), e.g., may have a thickness of less
than about one centimeter. The smartphone may be configured for
wireless data/voice communications using cellular networks,
Wireless Fidelity (WiFi) networks, or both. In some embodiments,
the smartphone may also comprise a near-field component, e.g., a
radio-frequency identification device that may also include a
multilayer coil design.
[0031] The handheld device 600 may comprise a housing 601, a
microphone 612, a touchscreen 614, a speaker 616, a front (face)
camera 619, one or more volume control buttons 650, and one or more
device function buttons 660. The housing 601 may be a casing that
forms the external surface of the handheld device 600 and provides
protection to the internal components of the handheld device 600,
including the wireless charging component, a battery, antenna
circuits, and other electronic components. The housing 601 may be a
non-conductive casing, such as a plastic casing. The microphone 612
may comprise one or more slots in the housing 601, which may be
coupled to a microphone circuit under the housing 601. The
touchscreen 614 may be configured to display text, video, and
graphics and to receive input from a user by tapping on or touching
the touchscreen 614 on a corresponding point (e.g., a text or
graphic). The speaker 616 may comprise one or more slots (e.g.,
circular or otherwise shaped slots) in the housing 601, which may
be coupled to a speaker circuit under the housing 601. The front
(face) camera 619 may be positioned inside a slot in the housing
601 and may comprise a one or more optical components (e.g., one or
more lenses) coupled to a digital video processing circuit inside
the housing 601. The volume control buttons 650 may be configured
to adjust the volume of the speaker, including increasing,
decreasing, and muting the volume. The device function buttons 660
may comprise a plurality of buttons for implementing different
functions, such as a home menu button, a return button, a phone
list button, a power button, a lock button, and/or other device
function buttons.
[0032] In some embodiments, the handheld device 600 may comprise an
external antenna, such as a metal strip positioned around the sides
of the housing 601. The handheld device 600 may also comprise other
external components (not shown), such as a rear camera, one or more
connection slots for connecting a power cord, a data transfer cord
(e.g., a universal serial bus (USB) cable), or a portable memory
card, or combinations thereof. At least some of the different
internal circuits and components of the handheld device 600 may be
fabricated on the same circuit board, e.g., a PCB. The components
above of the handheld device 600 may be shaped, arranged, and
positioned as shown in FIG. 6 or in any suitable form or
design.
[0033] At least one embodiment is disclosed and variations,
combinations, and/or modifications of the embodiment(s) and/or
features of the embodiment(s) made by a person having ordinary
skill in the art are within the scope of the disclosure.
Alternative embodiments that result from combining, integrating,
and/or omitting features of the embodiment(s) are also within the
scope of the disclosure. Where numerical ranges or limitations are
expressly stated, such express ranges or limitations should be
understood to include iterative ranges or limitations of like
magnitude falling within the expressly stated ranges or limitations
(e.g., from about 1 to about 10 includes, 2, 3, 4, etc.; greater
than 0.10 includes 0.11, 0.12, 0.13, etc.). For example, whenever a
numerical range with a lower limit, R.sub.1, and an upper limit,
R.sub.u, is disclosed, any number falling within the range is
specifically disclosed. In particular, the following numbers within
the range are specifically disclosed:
R=R.sub.1+k*(R.sub.u-R.sub.1), wherein k is a variable ranging from
1 percent to 100 percent with a 1 percent increment, i.e., k is 1
percent, 2 percent, 3 percent, 4 percent, 7 percent, . . . , 70
percent, 71 percent, 72 percent, . . . , 96 percent, 97 percent, 98
percent, 99 percent, or 100 percent. Moreover, any numerical range
defined by two R numbers as defined in the above is also
specifically disclosed. The use of the term about means.+-.10% of
the subsequent number, unless otherwise stated. Use of the term
"optionally" with respect to any element of a claim means that the
element is required, or alternatively, the element is not required,
both alternatives being within the scope of the claim. Use of
broader terms such as comprises, includes, and having should be
understood to provide support for narrower terms such as consisting
of, consisting essentially of, and comprised substantially of.
Accordingly, the scope of protection is not limited by the
description set out above but is defined by the claims that follow,
that scope including all equivalents of the subject matter of the
claims. Each and every claim is incorporated as further disclosure
into the specification and the claims are embodiment(s) of the
present disclosure. The discussion of a reference in the disclosure
is not an admission that it is prior art, especially any reference
that has a publication date after the priority date of this
application. The disclosure of all patents, patent applications,
and publications cited in the disclosure are hereby incorporated by
reference, to the extent that they provide exemplary, procedural,
or other details supplementary to the disclosure.
[0034] While several embodiments have been provided in the present
disclosure, it should be understood that the disclosed systems and
methods might be embodied in many other specific forms without
departing from the spirit or scope of the present disclosure. The
present examples are to be considered as illustrative and not
restrictive, and the intention is not to be limited to the details
given herein. For example, the various elements or components may
be combined or integrated in another system or certain features may
be omitted, or not implemented.
[0035] In addition, techniques, systems, subsystems, and methods
described and illustrated in the various embodiments as discrete or
separate may be combined or integrated with other systems, modules,
techniques, or methods without departing from the scope of the
present disclosure. Other items shown or discussed as coupled or
directly coupled or communicating with each other may be indirectly
coupled or communicating through some interface, device, or
intermediate component whether electrically, mechanically, or
otherwise. Other examples of changes, substitutions, and
alterations are ascertainable by one skilled in the art and could
be made without departing from the spirit and scope disclosed
herein.
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