U.S. patent application number 13/344567 was filed with the patent office on 2013-07-11 for discrete power transistor package having solderless dbc to leadframe attach.
This patent application is currently assigned to IXYS Corporation. The applicant listed for this patent is Kang Rim Choi, Gi-Young Jeun. Invention is credited to Kang Rim Choi, Gi-Young Jeun.
Application Number | 20130175704 13/344567 |
Document ID | / |
Family ID | 47471635 |
Filed Date | 2013-07-11 |
United States Patent
Application |
20130175704 |
Kind Code |
A1 |
Jeun; Gi-Young ; et
al. |
July 11, 2013 |
DISCRETE POWER TRANSISTOR PACKAGE HAVING SOLDERLESS DBC TO
LEADFRAME ATTACH
Abstract
A packaged power transistor device includes a Direct-Bonded
Copper ("DBC") substrate. Contact pads of a first lead are attached
with solderless welds to a metal layer of the DBC substrate. In a
first example, the solderless welds are ultrasonic welds. In a
second example, the solderless welds are laser welds. A single
power transistor realized on a single semiconductor die is attached
to the DBC substrate. In one example, a first bond pad of the die
is wire bonded to a second lead, and a second bond pad of the die
is wire bonded to a third lead. The die, the wire bonds, and the
metal layer of the DBC substrate are covered with an amount of
plastic encapsulant. Lead trimming is performed to separate the
first, second and third leads from the remainder of a leadframe,
the result being the packaged power transistor device.
Inventors: |
Jeun; Gi-Young; (Bucheon-si,
KR) ; Choi; Kang Rim; (Cupertino, CA) |
|
Applicant: |
Name |
City |
State |
Country |
Type |
Jeun; Gi-Young
Choi; Kang Rim |
Bucheon-si
Cupertino |
CA |
KR
US |
|
|
Assignee: |
IXYS Corporation
Milpitas
CA
|
Family ID: |
47471635 |
Appl. No.: |
13/344567 |
Filed: |
January 5, 2012 |
Current U.S.
Class: |
257/777 ;
257/E21.506; 257/E23.116; 438/121 |
Current CPC
Class: |
H01L 2924/181 20130101;
H01L 2224/49111 20130101; H01L 23/4334 20130101; H01L 2224/32245
20130101; H01L 2224/73265 20130101; H01L 2224/48247 20130101; H01L
2224/48472 20130101; H01L 2924/1305 20130101; H01L 2924/13034
20130101; H01L 23/3735 20130101; H01L 21/56 20130101; H01L
2224/0603 20130101; H01L 23/49562 20130101; H01L 2224/73265
20130101; H01L 2224/32245 20130101; H01L 2224/48247 20130101; H01L
2924/00 20130101; H01L 2224/48472 20130101; H01L 2224/48247
20130101; H01L 2924/00 20130101; H01L 2924/13034 20130101; H01L
2924/00014 20130101; H01L 2924/1305 20130101; H01L 2924/00
20130101; H01L 2224/49111 20130101; H01L 2224/48247 20130101; H01L
2924/00 20130101; H01L 2924/181 20130101; H01L 2924/00012 20130101;
H01L 2224/73265 20130101; H01L 2224/32245 20130101; H01L 2224/48247
20130101; H01L 2924/00012 20130101 |
Class at
Publication: |
257/777 ;
438/121; 257/E23.116; 257/E21.506 |
International
Class: |
H01L 23/28 20060101
H01L023/28; H01L 21/60 20060101 H01L021/60 |
Claims
1. A method comprising: attaching a first metal layer of a
direct-bonded copper ("DBC") substrate to at least one lead with a
solderless weld and thereby forming an assembly, wherein the DBC
substrate comprises an insulative layer disposed between the first
metal layer and a second metal layer; attaching one and only one
power semiconductor integrated circuit die to the first metal layer
of the assembly; and incorporating the assembly into a packaged
power integrated circuit device such that the packaged power
integrated circuit device comprises only one semiconductor die.
2. The method of claim 1, wherein the packaged power integrated
circuit device conforms to a TO-247 package outline.
3. The method of claim 1, wherein the attaching involves
ultrasonically welding the DBC substrate to the at least one
lead.
4. The method of claim 3, wherein the welding is carried out by
clamping the DBC substrate and the at least one lead together with
not more than about 0.05 Mpa, and wherein the welding is carried
out using ultrasonic vibrations of an amplitude of less than
approximately 20 micrometers.
5. The method of claim 1, wherein the attaching involves laser
welding the DBC substrate to the at least one lead.
6. The method of claim 1, wherein the first metal layer has a
thickness of at least 0.25 millimeters.
7. A packaged power integrated circuit device comprising: a
direct-bonded copper ("DBC") substrate comprising an insulative
layer disposed between the first metal layer and a second metal
layer; one and only one power semiconductor integrated circuit die
attached to the first metal layer; at least one lead that is
mechanically and electrically coupled to the first metal layer with
a solderless weld; and an amount of encapsulant surrounding the one
and only one power semiconductor integrated circuit die and at
least the first metal layer, and leaving at least a portion of the
second metal layer of the DBC substrate exposed to form a back side
of the packaged power integrated circuit device, and leaving a
portion of the lead exposed, wherein the second metal layer is
electrically insulated from the first metal layer.
8. The packaged power integrated circuit device of claim 7, wherein
the solderless weld is an ultrasonic weld.
9. The packaged power integrated circuit device of claim 8, wherein
the first metal layer has a thickness of at least 0.25
millimeters.
10. The packaged power integrated circuit device of claim 7,
wherein the solderless weld is a laser weld.
11. The packaged power integrated circuit device of claim 7,
wherein the packaged power integrated circuit device conforms to a
TO-247 package outline.
12. The packaged power integrated circuit device of claim 7,
wherein the one and only one power semiconductor integrated circuit
die is taken from the group consisting of: a power rectifier die, a
power regulator die, a silicon controlled rectifier die, a power
bipolar transistor integrated circuit die, a power insulated gate
bipolar transistor circuit die, a power field effect transistor
integrated circuit die.
13. The packaged power integrated circuit device of claim 7,
wherein the packaged power integrated circuit device includes three
leads, and wherein the back side of the packaged power integrated
circuit device is electrically insulated from each of the three
leads.
14. The packaged power integrated circuit device of claim 7,
wherein there is no solder disposed between the first metal layer
of the DBC substrate and the one and only one power semiconductor
integrated circuit die.
15. A packaged power integrated circuit device comprising: a
direct-bonded copper ("DBC") substrate comprising a ceramic layer
and a metal layer disposed on the ceramic layer; one and only one
power semiconductor integrated circuit die attached to the first
metal layer; an amount of encapsulant covering the one and only one
power semiconductor integrated circuit die and at least the first
metal layer; a first lead that is mechanically connected to the
first metal layer with a solderless weld; a second lead that is
wire bonded to the one and only one power semiconductor integrated
circuit die; and a third lead that is wire bonded to the one and
only one power semiconductor integrated circuit die, wherein the
first, second, and third leads extend parallel to one another from
the amount of encapsulant.
16. The packaged power integrated circuit device of claim 15,
wherein the first lead has a first contact pad portion and a second
contact pad portion, wherein the first contact pad portion has an
upper surface that extends in a plane that is substantially
parallel to a plane of an upper surface of the metal layer of the
DBC substrate, wherein the upper surface of the first contact
portion has a pattern of indentations, wherein the second contact
pad portion has an upper surface that extends in the plane that is
substantially parallel to the plane of the upper surface of the
metal layer of the DBC substrate, wherein the upper surface of the
second contact portion has a pattern of indentations.
17. The packaged power integrated circuit device of claim 15,
wherein the first lead has a first contact pad portion and a second
contact pad portion, wherein the first contact pad portion has an
upper surface that extends in a plane that is substantially
parallel to a plane of an upper surface of the metal layer of the
DBC substrate, wherein the upper surface of the first contact
portion has a pattern of mound-shaped protrusions, wherein the
second contact pad portion has an upper surface that extends in the
plane that is substantially parallel to the plane of the upper
surface of the metal layer of the DBC substrate, wherein the upper
surface of the second contact portion has a pattern of mound-shaped
protrusions.
18. The packaged power integrated circuit device of claim 17,
wherein the pattern of mound-shaped protrusions on the first
contact portion is a row, and wherein the pattern of mound-shaped
protrusions on the second contact portion is a row.
Description
TECHNICAL FIELD
[0001] The described embodiments relate to packaged discrete power
transistor devices.
BACKGROUND INFORMATION
[0002] A package known as the TO-247 package is often used to
package a power transistor die. A conventional TO-247 package
includes three parallel extending metal leads, where the center
lead extends from a center metal tab. The leads and the center tab
are stamped from the same thick copper sheet. The power transistor
die is mounted to a top side of the center tab. The center tab and
the die are then overmolded with a plastic encapsulant such that
the three leads extend parallel to one another from the amount of
plastic encapsulant. A backside surface of the metal tab is,
however, left exposed and is not covered with encapsulant. This
backside surface of metal forms the backside of the packaged
device. The backside of the tab is often electrically coupled to
the bottom side of the integrated circuit die. In operation, a high
voltage may be present on the bottom side of the die and the
backside of the package may be fixed to a metal heatsink. For
various reasons including safety reasons, it is undesirable that
the high voltage from the bottom side of the die be present on the
heatsink. Accordingly, insulating pads or washers are sometimes
provided between the backside of the package and the heatsink to
which the package is attached. These insulating pads or washers are
thermally conductive, but prevent the high voltage from the
backside of the package from being coupled to the heatsink.
Alternatively, a thin insulating member can be provided inside the
package between the bottom side of the die and top side of the
metal tab. This thin insulating member is thermally conductive, but
prevents the high voltage from the bottom side of the die from
being coupled to the metal tab that forms the backside of the
package. The package can then be connected to the heatsink without
an intervening insulating pads or washers. These different
structures for providing high voltage isolation are undesirable in
certain circumstances of for various reasons.
[0003] U.S. Pat. No. 6,404,065 discloses a TO-247 outline package
whose backside is electrically insulated from the bottom side of
the die within the package. Rather than having a metal tab that
extends from the center lead of the leadframe, the package involves
a Direct-Bonded Copper ("DBC") substrate. DBC substrates are also
sometimes referred to as Direct Copper Bonded ("DCB") substrates.
In one example, the DBC substrate involves a substrate layer of
ceramic insulator. This ceramic layer is sandwiched between a first
(die-side) layer of copper and a second (back-side) layer of
copper. The first die-side layer of copper is soldered to the
center lead of the leadframe. The die is also die-attached to this
first die-side layer of copper. After overmolding with plastic
encapsulant, the second back-side layer of copper forms the
backside of the package. Due to the insulating ceramic layer of the
DBC substrate, the first and second layers of copper are thermally
coupled to one another but the back-side copper layer is insulated
from the die-side copper layer and the integrated circuit. This DBC
substrate package has been in use for about ten years, and has been
quite successful.
SUMMARY
[0004] A packaged power integrated circuit device includes a
Direct-Bonded Copper ("DBC") substrate. The term "integrated
circuit", as it is used here, does not have to involve multiple
transistors or multiple electrical components integrated together
onto a semiconductor die, but rather the term integrated circuit
encompasses a single discrete power transistor realized by itself
(without other transistors) on a single semiconductor die using
semiconductor processing manufacturing technologies. The DBC
substrate of the packaged power integrated circuit device includes
an insulative substrate layer and at least one metal layer. Contact
pads of a first lead are attached with solderless welds to the
metal layer of the DBC substrate. One and only one power
semiconductor integrated circuit die is attached to the DBC
substrate. In one example, a first bond pad on an upper surface of
the die is wire bonded to a second lead, and a second bond pad on
the upper surface of the die is wire bonded to a third lead. The
integrated circuit die, the wire bonds, and the metal layer of the
DBC substrate are then covered with an amount of a plastic
encapsulant. Lead trimming is then performed to separate the first,
second and third leads from the remainder of a leadframe. The
result is the packaged power integrated circuit device. The
packaged power integrated circuit device may have an outline that
conforms to the TO-247 package outline.
[0005] In one example, the DBC substrate further includes a second
metal layer. The second metal layer is disposed on the opposite
side of the insulative substrate layer from the first metal layer
of the DBC substrate. After encapsulation, the second metal layer
is exposed and is not covered by the plastic encapsulant. At least
a part of the second metal layer forms a part of the backside of
the packaged power integrated circuit device. In the final packaged
power semiconductor integrated circuit package, the second metal
layer is electrically insulated from the first metal layer, and
from each of the three leads of the package.
[0006] In a first example, the solderless weld between the first
metal layer of the DBC substrate and the contact pads of the first
lead is an ultrasonic weld. Each contact pad of the first lead is
ultrasonically welded to the metal layer of the DBC substrate by
clamping the DBC substrate and the contact pad together with not
more than about 0.05 Mpa. Each weld is carried out by applying
ultrasonic energy with a vibration amplitude of less than or equal
to 20 micrometers at an oscillating frequency of approximately 20
kHz for approximately 0.3 seconds. The contact pads of the first
lead are nickel plated copper and are at least 0.25 mm thick (for
example, 0.30 mm thick). In one example, after ultrasonic welding,
the upper surfaces of the contact pads of the first lead bear a
pattern of indentations. Each indentation may have a V-shape such
that the indentations together form a waffle-like structure. The
operation is repeatable and is carried out without metal layer lift
off and without cracking of the insulative substrate layer of the
DBC.
[0007] In a second example, the solderless weld between the first
metal layer of the DBC substrate and the contact pads of the first
lead is a laser weld. The welding is carried out by clamping the
DBC substrate and the contact pads together with not more than
about 0.05 Mpa. Each contact pad is welded to the DBC substrate in
numerous places. At each place, the contact pad is heated to its
molten state using a pulse of 1064 nm laser energy at approximately
4.5 kW average power. In one example, after laser welding, the
upper surface of each contact pad of the first lead bears a row of
mound-shaped protrusions and associated pits.
[0008] Further details and embodiments and techniques are described
in the detailed description below. This summary does not purport to
define the invention. The invention is defined by the claims.
BRIEF DESCRIPTION OF THE DRAWINGS
[0009] The accompanying drawings, where like numerals indicate like
components, illustrate embodiments of the invention.
[0010] FIG. 1 is a perspective diagram of a Direct-Bonded Copper
("DBC") substrate.
[0011] FIG. 2 is a perspective diagram of a leadframe.
[0012] FIG. 3 is a cross-sectional showing the leadframe of FIG. 2
and the DBC substrate of FIG. 1 at the beginning of a package
assembly process.
[0013] FIG. 4 is a cross-sectional diagram showing the leadframe
and the DBC substrate at a subsequent time in the package assembly
process.
[0014] FIG. 5 is a cross-sectional diagram that shows a contact pad
and the DBC substrate both immediately before ultrasonic welding
and immediately after ultrasonic welding.
[0015] FIG. 6 is a cross-sectional diagram that shows a copper lift
off problem associated with a previous nonpublic and non-commercial
attempt to ultrasonically weld a DBC substrate to a leadframe.
[0016] FIG. 7 is a cross-sectional diagram that shows an alumina
cracking problem associated with the previous nonpublic and
non-commercial attempt to ultrasonically weld a DBC substrate to a
leadframe.
[0017] FIG. 8 is a table that sets forth parameters of a ultrasonic
welding process used to attach DBC substrates to leadframe contact
pads in accordance with one novel aspect.
[0018] FIG. 9 is a perspective view of a finished TO-247 packaged
discrete power integrated circuit device, where the DBC substrate
within the package is ultrasonically welded to contact pads of the
center lead (the plastic encapsulant overmolding is not shown).
[0019] FIG. 10 is a diagram of the bottom of the device of FIG. 9
showing the DBC substrate and the bent down extension portion of
the center lead (the encapsulant, the emitter and base leads, and
the associated bond wires are not shown).
[0020] FIG. 11 is a simplified perspective diagram of a finished
TO-247 device, where the DBC substrate is attached to the contact
pads of the center lead with a solderless weld in accordance with
one novel aspect. The first, second and third leads extend parallel
to one another from the amount of encapsulant 34.
[0021] FIG. 12 is a flowchart of a method in accordance with one
novel aspect.
[0022] FIG. 13 is a cross-sectional diagram of a second way that a
DBC substrate can be connected to contact pads with a solderless
weld.
[0023] FIG. 14 is a perspective view of a finished TO-247 packaged
power integrated circuit device, where the DBC substrate is laser
welded to the contact pads of the center lead (the plastic
encapsulant overmolding is not shown).
[0024] FIG. 15 is a table that sets forth parameters of the laser
welding process used to laser weld the DBC substrate to the contact
pads in the structure of FIG. 14.
DETAILED DESCRIPTION
[0025] Reference will now be made in detail to background examples
and some embodiments of the invention, examples of which are
illustrated in the accompanying drawings. In the description and
claims below, when a first object is referred to as being disposed
"over" or "on" a second object, it is to be understood that the
first object can be directly on the second object, or an
intervening object may be present between the first and second
objects. Similarly, terms such as "front", "back", "upper",
"lower", "top", "bottom", "underneath", "underlying" and "down" are
used herein to describe relative orientations between different
parts of the structure being described, and it is to be understood
that the overall structure being described can actually be oriented
in any way in three-dimensional space.
[0026] FIG. 1 is a perspective diagram of a Direct-Bonded Copper
("DBC") substrate 1. DBC substrate 1 involves a substrate layer 2
of an insulative material. Substrate layer 2 is sandwiched between
a first (die-side) layer 3 of metal and a second (back-side) layer
4 of metal. The second back-side metal layer 4 is not seen in the
perspective view of FIG. 1 because it is located underneath the
structure pictured. Arrow 4 indicates that this second back-side
metal layer 4 is disposed on the bottom side of the substrate layer
2 in the perspective shown.
[0027] In one example, substrate layer 2 is a layer of an
insulative material such as an insulative ceramic. In one example,
the insulative ceramic is alumina (Al.sub.2O.sub.3) that is 0.630
mm thick. In one example, first die-side metal layer 3 is a layer
of copper plated and a plating of a thin upper layer of nickel.
Metal layer 3 is at least 0.25 mm thick (for example, 0.30 mm
thick). The nickel plating (optional) is 10 micrometers thick.
Metal layer 3 may be referred to as a die-attach pad. Similarly,
second back-side metal layer 4 is a layer of copper and a plating
of a thin upper layer of nickel. Layer 4 is at least 0.25 mm thick
(for example, 0.30 mm thick). The nickel plating (optional) is 10
micrometers thick.
[0028] In one example, DBC substrate 1 is made by placing a first
sheet of metal on top of the sheet of alumina, and placing a second
sheet of metal under the sheet of alumina. The three sheets are
then pressed together in a high temperature furnace such that the
metal sheets are mechanically pressed and melted down and fixed to
the top and bottom surfaces of the alumina. The outer surfaces of
the metal layers take on the somewhat irregular non-planar surfaces
of the alumina layer. Irregularities of the alumina transfer
through the metal layer sheets. After pressing, the metal sheets
are patterned and etched using standard lithographic and etching
processes. The resulting etched structure is then sectioned into
smaller rectangular pieces. FIG. 1 shows one of these rectangular
pieces. The outer edges of the first die-side metal layer are set
back from the outer edges of substrate layer 2 so that a
later-applied encapsulant will better cover the side edges of the
die-side metal layer. The width of substrate layer 2 is about 14.2
mm and the length of layer substrate 2 is about 17.0 mm.
[0029] FIG. 2 is a perspective diagram of a leadframe 5. Leadframe
5 is stamped from a single sheet of thick copper. The copper of the
sheet is nickel plated. In another example, bare copper is used. A
center portion of leadframe 5 involves a first lead portion 6, a
second lead portion 7, and a third lead portion 8. Extending from
the first lead portion 6 is a bent down extension portion 10 that
terminates in two opposing finger-like contact pads 11 and 12.
Extending from second lead portion 7 is a bonding extension portion
9. Extending from third lead portion 8 is a bonding extension
portion 13.
[0030] FIG. 3 is a cross-sectional diagram showing leadframe 5 and
DBC substrate 1 at the beginning of a package assembly process.
[0031] FIG. 4 is a cross-sectional diagram showing leadframe 5 and
DBC substrate 1 at a subsequent time in the package assembly
process. The leadframe and the DBC substrate are brought together
as illustrated so that each pair of leadframe contact pads makes
contact with a corresponding DBC substrate. Each leadframe contact
pad is then attached with a solderless weld to a corresponding
portion of the first die-side layer of the associated DBC
substrate. In one example, the solderless weld is an ultrasonic
weld. Sinusoidal waveform 44 is a representation of the relative
ultrasonic movement that causes the welding to occur.
[0032] FIG. 5 is a cross-sectional diagram that shows contact pad
12 and the edge of first die-side metal layer 3 in further detail
both immediately before ultrasonic welding and immediately after
ultrasonic welding. As a result of the ultrasonic welding, contact
pad 12 is pressed down into and past the upper surface 45 of first
die-side layer 3 by approximately 0.05 millimeters. In one example,
there is no solder disposed between the upper surface of first
metal layer 3 and contact pad 12. As contact pad 12 is vibrated
back and forth relative to DBC substrate 1 during the ultrasonic
welding process, an amount of metal 14 may pile up at the side edge
15 of contact pad 12 as pictured in the right portion of FIG. 5.
The weld is a solderless weld.
[0033] Previous nonpublic and non-commercial attempts to
ultrasonically weld DBC substrates to leadframes in the TO-247
outline package set forth in U.S. Pat. No. 6,404,065 have been
made. These attempts were, however, considered unsuccessful. Copper
lift off as illustrated in FIG. 6 occurred. The leadframe 16 was
ultrasonically welded to the die-side metal layer 17 but the
ultrasonic energy used caused the die-side metal layer 17 to
separate in places from the ceramic layer 18 of the DBC substrate.
In some cases, the leadframe 19 was ultrasonically welded to the
die-side metal layer 20 but the alumina substrate 21 cracked as
illustrated in FIG. 7 occurred. Reference numerals 41-43 identify
representations of three such cracks.
[0034] FIG. 8 is a table that sets forth parameters of the
ultrasonic welding process used to attach DBC substrates to
leadframe contact pads in accordance with one novel aspect. In one
example, each ultrasonic weld is carried out using 20 kHz
ultrasonic vibrations, having a peak-to-peak vibration amplitude of
less than or equal to approximately 20 micrometers, for 0.25
seconds, under a welding pressure of not more than 0.05 Mpa. When
the parameters of FIG. 8 are used in the ultrasonic welding
process, little or none of the lift off and cracking illustrated in
FIG. 6 and FIG. 7 are seen to occur. After ultrasonic welding of
DBC substrates to the leadframe, a single power integrated circuit
die is attached to the die-side metal layer of each DBC substrate.
The single power integrated circuit die may, for example, be a
power rectifier die, a power regulator die, a silicon controlled
rectifier die, a power bipolar transistor integrated circuit die, a
power insulated gate bipolar transistor circuit die, or a power
field effect transistor integrated circuit die.
[0035] Next, bond pads on the top surfaces of the integrated
circuit dice are wire bonded in conventional fashion to the
corresponding wire bond portions of the corresponding leads of the
leadframe. After wire bonding, each die is overmolded with an
amount of plastic encapsulant in conventional fashion. The
back-side metal layer of each DBC substrate is, however, left at
least partially exposed and is not entirely overmolded. After
encapsulation, conventional lead trimming is performed to cut
individual TO-247 packaged devices from the leadframe. The
wirebonding, the overmolding with encapsulant, and the trimming of
interconnection portions of the leadframe to make the individual
packaged devices are processes known in the art.
[0036] FIG. 9 is a perspective view of one such finished TO-247
packaged device 22 with its plastic encapsulant overmolding not
shown. The upper surfaces of contact pads 11 and 12 have nonplanar
waffle-like indentations and contours 23. The indentations may be
of the shape of intersecting rows and columns of V-shaped trenches.
These indentations and contours 23 are a result of the force
applied by an ultrasonic welding head. During the compressive force
of the ultrasonic welding process, teeth or ridges on the bottom of
the ultrasonic head cut down into the upper surface of the contact
pads, thereby leaving the waffle-like indentations that correspond
to the shape of the teeth or ridges. The type of marks left need
not be waffle-like indentations rather may be nonplanar structures
of another shape depending on the structure of the gripping bottom
surface of the ultrasonic head.
[0037] One and only one power semiconductor integrated circuit die
24 is die-attached to the first die-side metal layer 3 of DBC
substrate 1. In the illustrated example, integrated circuit 24 is a
discrete power bipolar transistor integrated circuit die. The
bottom side of die 24 is the collector electrode 25. Collector
electrode 25 is electrically and mechanically connected to the
upper surface of the first die-side metal layer 3, and through this
layer of metal and through contact pads 11 and 12, and bent down
extension portion 10, to the center lead 6 of the TO-247 packaged
device 22. An emitter contact pad 26 on the upper surface of die 24
is electrically coupled via multiple aluminum bond wires 27-29 to
the lead extension portion 9 of packaged device 22. A base contact
pad 30 on the upper surface of die 24 is electrically coupled via
bond wire 31 to lead extension portion 13 of packaged device 22.
The emitter and base leads 7 and 8 are held in place in the
positions illustrated in FIG. 9 by the plastic encapsulant. The
locations of the ultrasonic welds at the interfaces between the
bottom of contact pads 11 and 12 and the top surface of die-side
metal layer 3 are roughly identified by arrows 32 and 33.
[0038] FIG. 10 is a diagram of the bottom of the device of FIG. 9,
showing the DBC substrate 1 and bent down extension portion 10 of
the center lead. The encapsulant, the emitter and base leads, and
the associated bond wires, are not shown in the simplified diagram
of FIG. 10.
[0039] FIG. 11 is a simplified perspective diagram of the finished
TO-247 device 22. The amount of plastic encapsulant 34 is shown.
This encapsulant 34 covers the die 24, the bond wires 27-29 and 31,
and the upper die-side metal layer 3 of the DBC substrate 1. The
back-side metal layer 4 of DBC substrate 1 is not covered with
encapsulant, but rather is exposed and forms the backside of the
packaged device 22. This back-side metal layer 4 is not shown in
FIG. 11 because it is the bottom side of the device pictured in the
FIG. 11.
[0040] FIG. 12 is a flowchart of a method 100 in accordance with
one novel aspect. A first metal layer of a DBC substrate is
attached to at least one lead with a solderless weld, thereby
forming an assembly (step 101). The solderless weld may be an
ultrasonic weld. The solderless weld may be a laser weld. In one
example, a first of the leads is a lead involving contact pads 11
and 12, bent portion 10, and lead portion 7; a second of the leads
is a lead involving portion 9 and lead portion 6; and a third of
the leads is a lead involving portion 13 and lead portion 8. In
another step (step 102), one and only one power semiconductor
integrated circuit is attached to the first metal layer of the
assembly. The resulting DBC substrate and lead assembly is then
incorporated (step 103) into a packaged power integrated circuit
device. In one example, this incorporation involves wire bonding
the die to the second and third leads, involves encapsulating the
die and DBC/lead assembly, and involves lead trimming to form the
resulting packaged power integrated circuit device. In one example,
the resulting packaged power integrated circuit device conforms to
the TO-247 outline and is the package 22 of FIG. 11.
[0041] FIG. 13 is a diagram of a second way that DBC substrate 1
can be connected to contact pads 11 and 12 with a solderless weld.
Rather than being ultrasonically welded, laser light source device
35 and laser light 36 are used to laser weld contact pads 11 and 12
to the die-side metal layer 3 of DBC substrate 1. Laser light 36
provides localized heating to carry out the weld. The term "laser"
is used here loosely. Energy from a high energy light source
(whether laser light or another type of light) is used to heat
small localized portions of contact pads 11 and 12 and thereby to
weld the contact pads to the underlying metal layer 3. In one
example, there is no intervening solder disposed between the
contact pads 11 and 12 and the underlying metal layer 3. The weld
is a solderless weld.
[0042] FIG. 14 is a perspective view of a finished packed
integrated circuit device 37 without its amount of encapsulant
overmolding. The structure 37 of FIG. 14 is similar to the
structure of FIG. 9, except that in the case of the structure 37 of
FIG. 14 the contact pads 11 and 12 have been laser welded to DBC
substrate 1. The upper surface of each of contact pads 11 and 12 is
has a row of five mound-shaped protrusions and corresponding pits.
Reference numeral 38 identifies the right most such mound-shaped
protrusion and pit structure on the top surface of contact pad 12.
Each mound and pit structure is formed as a result of application
of pulses of laser energy. The pulses of laser energy locally heat
part of a contact pad to a molten state and cause it to fuse to a
part of the upper surface of die-side metal layer 3 of the DBC
substrate. The locations of the laser welds at the interfaces
between the bottom of contact pads 11 and 12 and the top surface of
die-side metal layer 3 are roughly identified by arrows 39 and
40.
[0043] FIG. 15 is a table that sets forth parameters of the laser
welding process used to weld the DBC substrate 1 of FIG. 14 to the
contact pads 11 and 12 of FIG. 14 to make the packaged device of
FIG. 14.
[0044] In one example, the packaged semiconductor device, the DBC
substrate of the packaged semiconductor device, and the leads of
the packaged semiconductor device are as described in U.S. Pat. No.
6,404,065. The packaged semiconductor device may conform to a
package outline, such as the TO-220 outline, the TO-264 outline, or
the SOT-227B outline. For additional information on the packaged
semiconductor device, and for additional detail on its constituent
parts and how to make them, see: U.S. Pat. No. 6,404,065, U.S. Pat.
No. 4,483,810, and U.S. Pat. No. 6,727,585 (the entire subject
matter of each of these three patent documents is incorporated
herein by reference).
[0045] Although certain specific embodiments are described above
for instructional purposes, the teachings of this patent document
have general applicability and are not limited to the specific
embodiments described above. Accordingly, various modifications,
adaptations, and combinations of various features of the described
embodiments can be practiced without departing from the scope of
the invention as set forth in the claims.
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