U.S. patent application number 13/296724 was filed with the patent office on 2013-05-16 for dynamic wordline assist scheme to improve performance tradeoff in sram.
This patent application is currently assigned to International Business Machines Corporation. The applicant listed for this patent is Pankaj Agarwal, Vaibhav V. Prabhu, Krishnan S. Rengarajan. Invention is credited to Pankaj Agarwal, Vaibhav V. Prabhu, Krishnan S. Rengarajan.
Application Number | 20130121065 13/296724 |
Document ID | / |
Family ID | 48094882 |
Filed Date | 2013-05-16 |
United States Patent
Application |
20130121065 |
Kind Code |
A1 |
Agarwal; Pankaj ; et
al. |
May 16, 2013 |
DYNAMIC WORDLINE ASSIST SCHEME TO IMPROVE PERFORMANCE TRADEOFF IN
SRAM
Abstract
A dynamic wordline assist circuit for improving performance of
an SRAM. An SRAM is disclosed that includes a plurality of memory
cells, wherein each memory cell is coupled to a wordline and a pair
of bitlines; and a wordline assist circuit coupled to the wordline,
wherein the wordline assist circuit includes a first input for
activating the wordline assist circuit during a read or write cycle
and includes a second input for deactivating the wordline assist
circuit during the read or write cycle after a delay.
Inventors: |
Agarwal; Pankaj; (Uttar
Pradesh, IN) ; Prabhu; Vaibhav V.; (Bangalore,
IN) ; Rengarajan; Krishnan S.; (Bangalore,
IN) |
|
Applicant: |
Name |
City |
State |
Country |
Type |
Agarwal; Pankaj
Prabhu; Vaibhav V.
Rengarajan; Krishnan S. |
Uttar Pradesh
Bangalore
Bangalore |
|
IN
IN
IN |
|
|
Assignee: |
International Business Machines
Corporation
Armonk
NY
|
Family ID: |
48094882 |
Appl. No.: |
13/296724 |
Filed: |
November 15, 2011 |
Current U.S.
Class: |
365/154 |
Current CPC
Class: |
G11C 8/08 20130101; G11C
11/418 20130101 |
Class at
Publication: |
365/154 |
International
Class: |
G11C 11/00 20060101
G11C011/00 |
Claims
1. A static random access memory (SRAM) device, comprising: a
plurality of memory cells, wherein each memory cell is coupled to a
wordline and a pair of bitlines; and a wordline assist circuit
coupled to the wordline, wherein the wordline assist circuit
includes a first input for activating the wordline assist circuit
during a read or write cycle and includes a second input for
deactivating the wordline assist circuit during the read or write
cycle after a delay.
2. The SRAM device of claim 1, wherein the delay occurs after the
bitlines have partially discharged.
3. The SRAM device of claim 1, wherein the wordline assist circuit
is deactivated during a read cycle by a read timing control circuit
utilized to control read operations on the SRAM device.
4. The SRAM device of claim 1, wherein the wordline assist circuit
is deactivated during a write cycle with a signal derived from a
write timing control circuit utilized to control write operations
on the SRAM device.
5. The SRAM device of claim 4, wherein the signal derived from the
write timing control circuit is based on a delay associated with a
read timing control circuit.
6. The SRAM device of claim 1, wherein the wordline assist circuit
includes a PFET having a gate controlled by a NOR gate and an
inverter, a source coupled to ground, and a drain coupled to the
wordline and a plurality of pulldown legs.
7. The SRAM device of claim 6, further comprising a control block
for converting timing control signals into input signals for the
wordline assist circuit.
8. A wordline assist circuit for enhancing performance of a static
random access memory (SRAM) device, comprising: a control node for
controlling a wordline associated with a plurality of memory cells;
a first input for activating the wordline assist circuit during a
read or write cycle; and a second input for deactivating the
wordline assist circuit during the read or write cycle after a
delay; wherein, upon activation, the wordline assist circuit limits
a supply at the wordline provided by a wordline driver.
9. The wordline assist circuit of claim 8, wherein the delay occurs
after a pair of selected bitlines have partially discharged.
10. The wordline assist circuit of claim 8, wherein the wordline
assist circuit is deactivated during a read cycle by a read timing
control circuit utilized to control read operations on the SRAM
device.
11. The wordline assist circuit of claim 8, wherein the wordline
assist circuit is deactivated during a write cycle with a signal
derived from a write timing control circuit utilized to control
write operations on the SRAM device.
12. The wordline assist circuit of claim 11, wherein the signal
derived from the write timing control circuit is based on a delay
associated with a read timing control circuit.
13. The wordline assist circuit of claim 8, wherein the wordline
assist circuit includes a PFET having a gate controlled by a NOR
device and an inverter, a source coupled to ground, and a drain
coupled to the control node and a plurality of pulldown legs.
14. The wordline assist circuit of claim 13, further comprising a
control block for converting timing control signals into input
signals for the wordline assist circuit.
15. A method for improving performance of a static random access
memory (SRAM) device, comprising: providing an SRAM device with a
plurality of memory cells, wherein each cell is coupled to a
wordline and a pair of bitlines; activating a wordline assist using
a first input during a read or write cycle, wherein the wordline
assist limits a supply at the wordline to improve stability; and
deactivating the wordline assist using a second input during the
read or write cycle after a delay to improve associated reading or
writing performance.
16. The method of claim 15, wherein the delay occurs after the
bitlines have partially discharged.
17. The method of claim 15, wherein the wordline assist is
deactivated during a read cycle by a read timing control circuit
utilized to control read operations on the SRAM device.
18. The method of claim 15, wherein the wordline assist circuit is
deactivated during a write cycle with a signal derived from a write
timing control circuit utilized to control write operations on the
SRAM device.
19. The method of claim 18, wherein the signal derived from the
write timing control circuit is based on a delay associated with a
read timing control circuit.
20. The method of claim 15, wherein the wordline assist is
implemented with a circuit that includes a PFET having a gate
controlled by a NOR gate and an inverter, a source coupled to
ground, and a drain coupled to the wordline and a plurality of
pulldown legs.
Description
BACKGROUND
[0001] The present invention relates to static random-access memory
(SRAM) and more particularly to a wordline stability assist scheme
to improve the tradeoff between cell stability due to read disturb
and writeability.
[0002] The popular 6T SRAM cell, which utilizes six transistors to
store a memory bit and is the industry workhorse today, has always
been a challenge for scaling from one technology to the next.
Designing the memory for an acceptable yield for cell stability and
writeability to the cell has been a challenge under today's
constraints of low voltage operation, very high process variation,
large amount of memory on die, and area efficiency (or cost per
bit). Various techniques have been proposed in the prior art, each
having a tradeoff in one way or the other. Some approaches have
even moved away from the 6T cell at a high cost of area
efficiency.
BRIEF SUMMARY
[0003] Described herein is an enhancement of a wordline stability
assist scheme to improve the tradeoff between cell stability and
readability/writeability.
[0004] In a first aspect, the present invention provides a static
random access memory (SRAM) device, comprising: a plurality of
memory cells, wherein each memory cell is coupled to a wordline and
a pair of bitlines; and a wordline assist circuit coupled to the
wordline, wherein the wordline assist circuit includes a first
input for activating the wordline assist circuit during a read or
write cycle and includes a second input for deactivating the
wordline assist circuit during the read or write cycle after a
delay.
[0005] In a second aspect, the invention provides a wordline assist
circuit for enhancing performance of a static random access memory
(SRAM) device, comprising: a control node for controlling a
wordline associated with a plurality of memory cells; a first input
for activating the wordline assist circuit during a read or write
cycle; and a second input for deactivating the wordline assist
circuit during the read or write cycle after a delay; wherein, upon
activation, the wordline assist circuit limits a supply at the
wordline provided by a wordline driver.
[0006] In a third aspect, the invention provides a method for
improving performance of a static random access memory (SRAM)
device, comprising: providing an SRAM device with a plurality of
memory cells, wherein each cell is coupled to a wordline and a pair
of bitlines; activating a wordline assist during a read or write
cycle, wherein the wordline assist limits a supply at the wordline
to improve stability; and deactivating the wordline assist during
the read or write cycle after a delay to improve associated reading
or writing performance.
BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWINGS
[0007] These and other features of this invention will be more
readily understood from the following detailed description of the
various aspects of the invention taken in conjunction with the
accompanying drawings.
[0008] FIG. 1 depicts a 6T SRAM cell.
[0009] FIG. 2 depicts a schematic of a portion of a 6T SRAM device
having an assist circuit in accordance with an embodiment of the
invention.
[0010] FIG. 3 depicts a timing diagram of a write operation showing
improved performance and stability in accordance with an embodiment
of the present invention.
[0011] FIG. 4 depicts a timing diagram of a read operation showing
improved performance and stability in accordance with an embodiment
of the present invention.
[0012] FIG. 5 depicts a flow chart showing a method for
implementing dynamic wordline assist in accordance with an
embodiment of the present invention.
[0013] The drawings are merely schematic representations, not
intended to portray specific parameters of the invention. The
drawings are intended to depict only typical embodiments of the
invention, and therefore should not be considered as limiting the
scope of the invention. In the drawings, like reference numbering
represents like elements.
DETAILED DESCRIPTION
[0014] FIG. 1 depicts an illustrative 6T SRAM cell 10. Operations
of such cells are well understood in the art and therefore are not
described in detail. In general, a write operation occurs by
placing opposite values on the bit lines, and asserting the
wordline WL, which causes the values to be stored in the cell. A
read operation generally includes precharging both bitlines to a
logical 1, then asserting the word line WL. A sense amplifier
coupled to the bit lines evaluates the result.
[0015] As noted, there tends to be a performance conflict between
stability and readability/writeability in such cells. Techniques
are known to increase stability, which has the adverse affect of
decreasing readability/writeability. Similarly, techniques are
known to increase readability/writeability, which has the adverse
effect of decreasing stability. The present approach utilizes a
dynamic assist circuit coupled to the wordline WL to achieve both
improved stability and readability/writeability. In particular, the
circuit dynamically lowers the wordline WL to improve stability,
but also boosts the wordline WL to negative levels to improve
readability/writeability.
[0016] FIG. 2 shows an SRAM device 12 (in partial detail) having a
dynamic wordline assist circuit 22. In particular, SRAM device 12
includes a wordline driver 14 that activates/deactivates wordline
WL. Cells 10 are arranged in columns and rows, with each column
being coupled to a bit line BL (and its inverse) and selected by a
column select input 18. A sense amplifier 16 is coupled to each
column, and is controlled by timing input 20. For the purposes of
describing illustrative embodiments, much of the SRAM device 12 is
omitted from the illustration. It is recognized that the operation
of an SRAM device is well understood by those skilled in the
art.
[0017] In order to achieve better stability and writeability,
wordline assist circuit 22 is utilized to dynamically alter the
behavior of the wordline WL. Wordline assist circuit 22 generally
includes a NOR gate 30 with three inputs coupled to an inverter 32,
which in turn controls the gate of a PFET 34. The source and drain
of the PFET 34 are coupled to multiple PFET pulldown legs 36 and
ground, respectively. Pulldown legs 36 are in turn coupled to a
control node 35 on the wordline WL. The PFET 34, when activated,
will degrade the high level of the wordline WL by a small voltage
(e.g., 1-50 mV) depending upon the number of pulldown legs 36
turned on.
[0018] The assist circuit 22 as shown includes three inputs,
including: (1) an assist activation input 24; (2) a read control
input 26; and (3) a write control input 28. When the assist circuit
22 is activated, i.e., PFET 34 is turned on, the wordline driver 14
is pulled down, or limited, to increase stability. To improve
performance during both read and write operations, the assist
circuit 22 is turned off, i.e., deactivated, shortly after the
wordline WL is turned on. This can be achieved with the described
circuitry, e.g., by providing an appropriate signal on the read
control 26 and/or write control inputs 28. The slight delay allows
the bitlines BL to discharge some, thus providing relief for cell
stability and improving the readability/writeability margin. The
amount of delay in releasing the wordline assist circuit 22 can be
designed to achieve an optimal amount of stability and
readability/writeability.
[0019] The assist activation input 24 may for example be activated
based on silicon measurements from a calibrating macro (not shown).
These measurements would indicate whether stability assist should
be engaged. Once the decision is made, the assist activation input
24 is turned ON through, e.g., an efuse (the efuse is programmed
once the decision is made, so every time the chip comes on, the
value is downloaded from the efuse). Accordingly, the assist
activation input 24 is a static input. As shown in FIG. 2, it is an
active low signal, i.e., 0, when stability assist is ON and 1 when
stability assist is OFF.
[0020] Note that each of the pulldown legs 36 is controlled by
signals similar to assist activation input 24. Depending on silicon
measurements of the calibration macro, the degree of stability
assist needed can vary from small to large, and correspond to
lowering the wordline WL by small to large amounts respectively.
Correspondingly, one or more of these pulldown legs 36 would be
turned ON. If more are turned ON, the resistance of the pull down
path would decrease, and the WL level will become lower. It is
recognized that the circuitry shown for implementing wordline
assist circuit 22 is an illustrative embodiment for providing the
functionality described herein. Accordingly, other circuits for
performing such functions could likewise be utilized and fall
within the scope of the invention.
[0021] Read and write control inputs 26, 28 are obtained from a
control block 39 in response to timing control circuits 38. The
read and write control inputs 26, 28 cause the assist circuit 22 to
be deactivated (i.e., by inputting a logic 1) a short time after
assist circuit 22 is activated. The delay is obtained from existing
timing signals on the SRAM device 12. Timing control circuits 38
are utilized to generate sense amp enable and write assist controls
for the output and input datapaths respectively. The time to turn
on the sense amplifier 16 is about the time the bitlines have a
sufficiently signal developed. With this signal development (70 mV
at slow corners, much higher at fast corners where stability is a
concern), the cell is out of the danger region for stability, so
the READ signal from timing control circuits 38 can be used as the
read control input 26 to release the stability assist on the
wordline WL. Depending upon the particular implementation, a
typical delay may be on the order of 100-300 ps.
[0022] For the write cycle, write control input 26 can be derived
from the WRITE signal, but delayed to be same as the READ trigger
would be during the READ cycle to protect half selected columns
during a write operation. The WRITE signal too may be used, if the
timing is as good.
[0023] FIG. 3 depicts an illustrative timing diagram of a write
operation showing the behavior of wordline WL 44 and node NT 42
(FIG. 1) after the WL assist is released (i.e., deactivated) at
delay T.sub.D. Traces 44' and 42' depict the behaviors of the
wordline WL and node NT without deactivation of the WL assist. As
can be seen, NT 42 flips sooner relative to NT 42' when the assist
is deactivated. In addition, it can be seen that WL 44 remains
stable.
[0024] FIG. 4 depicts an illustrative timing diagram of a read
operation showing the behavior of wordline WL 52 and bitline BL 54
(see FIG. 1) after the WL assist is released (i.e., deactivated) at
T.sub.D. Traces 52' and 54' depict the behaviors of the wordline WL
and node NT without deactivation of the WL assist. Here again, it
can be seen that BL 54 outperforms BL 54' and WL 52 remains stable
throughout.
[0025] FIG. 5 depicts a flowchart for implementing dynamic wordline
assist for an SRAM device. At S1, a read or write cycle begins, and
at S2 the wordline is activated with wordline assist turned on to
enhance stability. (As noted above, the decision to turn wordline
assist on is typically an on-chip stored decision based on silicon
testing at manufacturing.) At S4 a delay occurs to allow the
bitlines to partially discharge. After the delay, the wordline
assist is deactivated at S4 for the remainder of the cycle. At S5,
the wordline is deactivated and at S6 the current read or write
cycle ends.
[0026] The descriptions of the various embodiments of the present
invention have been presented for purposes of illustration, but are
not intended to be exhaustive or limited to the embodiments
disclosed. Many modifications and variations will be apparent to
those of ordinary skill in the art without departing from the scope
and spirit of the described embodiments. The terminology used
herein was chosen to best explain the principles of the
embodiments, the practical application or technical improvement
over technologies found in the marketplace, or to enable others of
ordinary skill in the art to understand the embodiments disclosed
herein. For example, although generally described with reference to
a 6T SRAM, it is understood that the present invention may be
utilized with other memory variations, including dual port cell
based memory. It is also understood that the features of the
invention may be applied to just read operations, just write
operations, or both operations.
[0027] In addition, as will be appreciated by one skilled in the
art, aspects of the present invention may be embodied as a system,
method or computer program product/netlist. Accordingly, aspects of
the present invention may take the form of an entirely hardware
embodiment, an entirely software embodiment (including firmware,
resident software, micro-code, etc.) or an embodiment combining
software and hardware aspects that may all generally be referred to
herein as a "circuit," "computer" or "system." Furthermore, aspects
of the present invention may take the form of a netlist embodied
and stored in an electronic storage medium and/or computer program
product embodied in one or more computer readable medium(s) having
computer readable program code embodied thereon.
* * * * *