U.S. patent application number 13/617291 was filed with the patent office on 2013-03-28 for etch stop layer for memory cell reliability improvement.
This patent application is currently assigned to SPANSION LLC. The applicant listed for this patent is Kuo-Tung CHANG, Angela HUI, Hiroyuki KINOSHITA, Minh VAN NGO, Hiroyuki OGAWA, Hsiao-Han THIO. Invention is credited to Kuo-Tung CHANG, Angela HUI, Hiroyuki KINOSHITA, Minh VAN NGO, Hiroyuki OGAWA, Hsiao-Han THIO.
Application Number | 20130078795 13/617291 |
Document ID | / |
Family ID | 47190865 |
Filed Date | 2013-03-28 |
United States Patent
Application |
20130078795 |
Kind Code |
A1 |
KINOSHITA; Hiroyuki ; et
al. |
March 28, 2013 |
ETCH STOP LAYER FOR MEMORY CELL RELIABILITY IMPROVEMENT
Abstract
A memory device and a method of making the memory device are
provided. A first dielectric layer is formed on a substrate, a
floating gate is formed on the first dielectric layer, a second
dielectric layer is formed on the floating gate, a control gate is
formed on the second dielectric layer, and at least one film,
including a conformal film, is formed over a surface of the memory
device.
Inventors: |
KINOSHITA; Hiroyuki; (San
Jose, CA) ; HUI; Angela; (Fremont, CA) ; THIO;
Hsiao-Han; (Santa Clara, CA) ; CHANG; Kuo-Tung;
(Saratoga, CA) ; NGO; Minh VAN; (Fremont, CA)
; OGAWA; Hiroyuki; (Sunnyvale, CA) |
|
Applicant: |
Name |
City |
State |
Country |
Type |
KINOSHITA; Hiroyuki
HUI; Angela
THIO; Hsiao-Han
CHANG; Kuo-Tung
NGO; Minh VAN
OGAWA; Hiroyuki |
San Jose
Fremont
Santa Clara
Saratoga
Fremont
Sunnyvale |
CA
CA
CA
CA
CA
CA |
US
US
US
US
US
US |
|
|
Assignee: |
SPANSION LLC
Sunnyvale
CA
ADVANCED MICRO DEVICES, INC.
Sunnyvale
CA
|
Family ID: |
47190865 |
Appl. No.: |
13/617291 |
Filed: |
September 14, 2012 |
Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
|
|
11008240 |
Dec 10, 2004 |
8319266 |
|
|
13617291 |
|
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|
|
Current U.S.
Class: |
438/593 ;
438/761 |
Current CPC
Class: |
H01L 29/7881 20130101;
H01L 29/40114 20190801; H01L 29/66825 20130101; H01L 21/0217
20130101 |
Class at
Publication: |
438/593 ;
438/761 |
International
Class: |
H01L 21/02 20060101
H01L021/02 |
Claims
1. A method of comprising: forming a first dielectric layer on a
substrate of a memory device; forming a floating gate on the first
dielectric layer; forming a second dielectric layer on the floating
gate; forming a control gate on the second dielectric layer; and
forming at least one film over a surface of the control gate, the
at least one film including a conformal film.
2. The method of claim 1, where: the conformal film comprises a
silicon nitride film, and the forming at least one film comprises
using one of a low pressure chemical vapor deposition process to
form the conformal film or an atomic layer deposition process to
form the conformal film.
3. The method of claim 1, where the conformal film has a thickness
ranging from about 100 angstroms to about 700 angstroms.
4. The method of claim 1, where: the forming at least one film
further includes forming a second film over the conformal film, and
the second film comprises a silicon nitride film formed using a
plasma enhanced chemical vapor deposition process.
5. The method of claim 1, further comprising: forming a first
spacer and a second spacer adjacent to the first dielectric layer,
the floating gate, the second dielectric layer, and the control
gate, where the forming at least one film further comprises:
forming a second film over the surface of the control gate, a
surface of the first spacer, a surface of the second spacer, and a
surface of the substrate, and forming the conformal film over the
second film.
6-20. (canceled)
21. The method of claim 1, where the conformal film fills gaps and
crevices along the first dielectric layer, the floating gate, and
the control gate, and where the conformal film fills the gaps and
the crevices to improve memory cell data retention of the memory
device.
22. The method of claim 21, where forming the at least one film
includes: forming a non-conformal film over the conformal film, the
non-conformal film having a non-uniform thickness, and the
conformal film having a substantially uniform thickness.
23. A method comprising: forming a memory cell on a substrate of a
memory device; forming a conformal silicon nitride film over the
memory cell, the conformal silicon nitride film having a
substantially uniform thickness, the conformal silicon nitride film
contacting a portion of the substrate, the conformal silicon
nitride film filling gaps and crevices along the memory cell and
interfaces associated with a first spacer and a second spacer that
are formed on opposite sides of the memory cell, and the conformal
silicon nitride film filling the gaps and the crevices to improve
memory cell data retention of the memory device; and forming a
non-conformal silicon nitride film on the conformal silicon nitride
film, the non-conformal silicon nitride film having a non-uniform
thickness, and a portion of the non-conformal silicon nitride film
formed over a top surface of the memory cell being thicker than
another portion of the non-conformal silicon nitride film formed
adjacent the first spacer and the second spacer.
24. The method of claim 23, where forming the conformal silicon
nitride film includes: depositing the conformal silicon nitride
film using a low pressure chemical vapor deposition (LPCVD) process
or using an atomic layer deposition (ALD) process.
25. The method of claim 23, where forming the non-conformal silicon
nitride film includes: depositing the non-conformal silicon nitride
film over the conformal silicon nitride film using a plasma
enhanced chemical vapor deposition (PECVD) process.
26. The method of claim 23, where the non-conformal silicon nitride
film extends over a source region and a drain region of the
substrate.
27. The method of claim 23, further comprising: forming the first
spacer and the second spacer on the opposite sides of the memory
cell, where forming the conformal silicon nitride film includes:
forming the conformal silicon nitride film over the first spacer
and the second spacer.
28. The method of claim 23, where a thickness of the conformal
silicon nitride film ranges from about 100 angstroms to about 700
angstroms.
29. The method of claim 23, where a thickness of the conformal
silicon nitride film combined with a thickness of the non-conformal
silicon nitride film ranges from about 100 angstroms to about 1000
angstroms.
30. A method comprising: forming a conformal silicon nitride film
over a memory cell formed on a substrate of a memory device, the
conformal silicon nitride film having a substantially uniform
thickness, the conformal silicon nitride film contacting a portion
of the substrate, the conformal silicon nitride film filling gaps
and crevices along the memory cell, and the conformal silicon
nitride film filling the gaps and the crevices to improve memory
cell data retention of the memory device; and forming a
non-conformal silicon nitride film on the conformal first silicon
nitride film, the non-conformal silicon nitride film having a
non-uniform thickness, and a portion of the non-conformal silicon
nitride film formed over a top surface of the memory cell being
thicker than another portion of the non-conformal silicon nitride
film.
31. The method of claim 30, further comprising: forming a first
spacer and a second spacer on the opposite sides of the memory
cell, where forming the conformal silicon nitride film includes:
forming the conformal silicon nitride film over the first spacer
and the second spacer.
32. The method of claim 30, where a thickness of the conformal
silicon nitride film ranges from about 100 angstroms to about 700
angstroms.
33. The method of claim 30, where a thickness of the conformal
silicon nitride film combined with a thickness of the non-conformal
silicon nitride film ranges from about 100 angstroms to about 1000
angstroms.
34. The method of claim 30, where forming the conformal silicon
nitride film includes: depositing the conformal silicon nitride
film using a low pressure chemical vapor deposition (LPCVD) process
or using an atomic layer deposition (ALD) process.
35. The method of claim 30, where forming the non-conformal silicon
nitride film includes: depositing the non-conformal silicon nitride
film over the conformal silicon nitride film using a plasma
enhanced chemical vapor deposition (PECVD) process.
Description
RELATED APPLICATION
[0001] This application is a divisional of U.S. patent application
Ser. No. 11/008,240, filed Dec. 10, 2004, which is incorporated
herein by reference.
TECHNICAL FIELD
[0002] The present invention relates generally to semiconductor
memory devices and, more particularly, to a semiconductor memory
device having an improved reliability.
BACKGROUND ART
[0003] The escalating demands for high density and performance
associated with non-volatile memory devices require small design
features, high reliability and increased manufacturing throughput.
The reduction of design features, however, challenges the
limitations of conventional methodology. For example, the reduction
of design features often creates problems in memory devices, such
as memory cell data retention problems.
DISCLOSURE OF THE INVENTION
[0004] Implementations consistent with the invention provide a
memory cell with improved memory cell data retention by forming one
or more films over the memory cell.
[0005] Additional advantages and other features of the invention
will be set forth in part in the description which follows and in
part will become apparent to those having ordinary skill in the art
upon examination of the following or may be learned from the
practice of the invention. The advantages and features of the
invention may be realized and obtained as particularly pointed out
in the appended claims.
[0006] According to one aspect consistent with the invention, a
method of forming a memory device is provided. The method may
include forming a first dielectric layer on a substrate, forming a
floating gate on the first dielectric layer, forming a second
dielectric layer on the floating gate, forming a control gate on
the second dielectric layer, and forming at least one film over a
surface of the memory device, where a first one of the at least one
film is a conformal film.
[0007] According to another aspect consistent with the invention, a
memory device is provided. The memory device may include a
substrate, a first dielectric layer formed on a portion of the
substrate, a floating gate formed on the first dielectric layer, a
second dielectric layer formed on the floating gate, a control gate
formed on the second dielectric layer, a first spacer and a second
spacer formed on the substrate on opposite sides of the memory
device, and at least one film, which may include a conformal film,
formed over a surface of the control gate, the first spacer, the
second spacer, and the substrate.
[0008] According to a third aspect consistent with the invention, a
memory device is provided. The memory device may include a
substrate, a first dielectric layer formed on a portion of the
substrate, a floating gate formed on the first dielectric layer, a
second dielectric layer formed on the floating gate, a control gate
formed on the second dielectric layer, and at least two films
formed over a surface of the memory device.
[0009] Other advantages and features of the present invention will
become readily apparent to those skilled in this art from the
following detailed description. The embodiments shown and described
provide illustration of the best mode contemplated for carrying out
the invention. The invention is capable of modifications in various
obvious respects, all without departing from the invention.
Accordingly, the drawings are to be regarded as illustrative in
nature, and not as restrictive.
BRIEF DESCRIPTION OF THE DRAWINGS
[0010] Reference is made to the attached drawings, wherein elements
having the same reference number designation may represent like
elements throughout.
[0011] FIG. 1 illustrates an exemplary memory device upon which an
etch stop layer may be formed consistent with an aspect of the
invention;
[0012] FIG. 2 illustrates the exemplary memory device of FIG.1
having a film formed thereover consistent with one implementation
of the invention;
[0013] FIG. 3 illustrates the exemplary memory device of FIG.1
having multiple films formed over the memory device consistent with
one implementation of the invention;
[0014] FIG. 4 illustrates the formation of an interlayer dielectric
(ILD) over the exemplary memory device of FIG. 3 consistent with
the invention;
[0015] FIG. 5 illustrates the exemplary memory device of FIG. 4
having an etched contact hole formed over a source or drain region
of the memory device; and
[0016] FIG. 6 illustrates the exemplary memory device of FIG. 5
having a contact formed within the etched contact hole.
[0017] FIG. 7 illustrates films formed over the exemplary memory
device of FIG. 1 in accordance with another implementation.
BEST MODE FOR CARRYING OUT THE INVENTION
[0018] The following detailed description of the invention refers
to the accompanying drawings. The same reference numbers in
different drawings may identify the same or similar elements. Also,
the following detailed description does not limit the invention.
Instead, the scope of the invention is defined by the appended
claims and their equivalents.
[0019] FIG. 1 illustrates an exemplary memory device 110 consistent
with principles of the invention. Memory device 110 may include a
substrate 105, a first dielectric layer 115, a floating gate 120, a
second dielectric layer 125, a control gate 130, and spacers
140.
[0020] First dielectric layer 115 may be formed on a portion of
substrate 105. First dielectric layer 115 may be, for example, a
gate oxide layer, which may have a thickness ranging from about 70
.ANG. to about 110 .ANG.. Dielectric layer 115 and may include
dielectric materials such as silicon oxide or other types of
dielectric materials and may be referred to as a tunnel oxide
layer. Floating gate 120 may range in thickness from about 400
.ANG. to about 1,200 .ANG. and may include polysilicon, germanium
or other types of materials that may be used to store a charge.
Second dielectric layer 125 may have a thickness ranging from about
100 .ANG. to about 200 .ANG. and may include dielectric materials
such as silicon oxide, an ONO stack, or other types of dielectric
materials. Dielectric layer 115 may function as an inter-gate
dielectric for memory device 110.
[0021] Control gate 130 may range in thickness from about 900 .ANG.
to about 3,000 .ANG. and may include polysilicon, germanium, or
other types of semiconducting materials. Spacers 140 may be formed
on each side of memory device 110 and may include, for example, a
dielectric material. Spacers 140 may function to isolate memory
device 110 from other memory devices and may also function to
facilitate the formation of source and drain regions.
[0022] As shown in FIG. 2, a conformal film 202 (e.g., a film
having a substantially uniform thickness on all surfaces, including
sidewall surfaces) may be formed over a surface of memory device
110. Conformal film 202 may include, for example, silicon nitride.
In some implementations, conformal film 202 may have a thickness of
less than 1,000 .ANG., such as a thickness ranging from about 100
.ANG. to about 700 .ANG.. Conformal film 202 may easily fill gaps
and crevices along the stacked gate structure, including first
dielectric layer 105, floating gate 120, second dielectric layer
125, and control gate 130, and may have a substantially uniform
thickness. Thus, conformal film 202 may fill small gaps and
crevices along the stacked gate structure and spacer 140
interfaces, thereby improving memory cell data retention. Conformal
film 202 may also provide a relatively thick sidewall deposition
along a high aspect ratio gate structure and may protect memory
device 110 during subsequent processing. Conformal film 202 may be
deposited using a low pressure chemical vapor deposition (LPCVD)
process or by using an atomic layer deposition (ALD) process, both
of which are well known in the art. Conformal film 202 may also be
formed using other conventional techniques.
[0023] FIG. 3 illustrates a second film 302 that may be formed over
conformal film 202. Film 302 may include, for example, silicon
nitride, which may be deposited over film 202 using a plasma
enhanced chemical vapor deposition process (PECVD), which is well
known in the art. Film 302 may be a non-conformal film that may
tend to form a thicker film at a top portion 304 of memory device
110 and may form a thinner film along a side portion 306 of memory
device 110.
[0024] When conformal film 202 is deposited using the LPCVD
process, it may be deposited at a temperature of about 650.degree.
C. to about 750.degree. C. When conformal film 202 is deposited
using the ALD process, it may be deposited at a temperature of
about 300.degree. C. to about 500.degree. C. When film 302 is
deposited using the PECVD process, it may be deposited at a
temperature ranging from about 400.degree. C. to about 525.degree.
C. Films 202 and 302 may be formed to a combined thickness
sufficient to act as a good etch stop layer. In some
implementations, the total combined thickness of films 202 and 302
may range from about 100 .ANG. to about 1,000 .ANG..
[0025] FIG. 4 illustrates an interlayer dielectric (ILD) 402 formed
over memory device 110, including films 202 and 302. ILD 402 may be
used to facilitate the formation of a contact formed between layers
of conductors that connects different components of a single one of
memory devices 110, or interconnects different ones of memory
devices 110. ILD 402 may be formed over devices 110 using, for
example, existing deposition processes. ILD 402 may include, for
example, tetraethylorthosilicate (TEOS), or any other dielectric
material. In one exemplary implementation, ILD 402 may include a
boro-phosphorous TEOS (BPTEOS). The thickness of ILD 402 may vary
based on the sizes of memory device 110, or based on other design
or fabrication parameters. In one exemplary embodiment, the
thickness of ILD 402 may range from about 5,000 .ANG. to about
15,000 .ANG.. ILD 402 may be polished back to a planar surface
using, for example, an existing chemical-mechanical polishing (CMP)
process.
[0026] FIG. 5 illustrates a contact hole 502 etched through ILD
402. As illustrated, contact hole 502 may be formed through ILD 402
and films 202 and 302, located on the surface of substrate 105,
down to substrate 105. Contact hole 502 may be etched over a region
504 of memory device 110, which may be, for example, a source
region or a drain region. Films 202 and 302, as described above,
may act to fill small gaps along the stacked gate structure and
spacer 140 interfaces to help improve memory cell data retention.
Films 202 and 302 also act as etch stop layers when forming contact
hole 502. For example, as the etching proceeds through ILD 402, the
start of etching of films 302 and 202 may be detected. The etching
may then be stopped without etching through substrate 105 (e.g., a
source region or drain region). As illustrated in FIG. 5, contact
hole 502 may be formed through ILD 402 and films 302 and 202,
terminating at the surface of substrate 105.
[0027] Contact hole 502 may then be filled with a metal, such as
tungsten or polysilicon, to form a contact 602, as illustrated in
FIG. 6. Contact 602 may be used for interconnecting a group of
memory devices 110, for connecting memory device 110 to an external
terminal, for connecting a source or drain region to another
conductive structure in memory device 110, or for another
purpose.
[0028] In an alternative implementation, instead of first
depositing conformal film 202 and then depositing film 302, as
shown in FIGS. 2 and 3, film 302 may be deposited first and then
film 202 may be deposited over film 302, as illustrated in FIG. 7.
That is, the non-conformal film 302 may be deposited over memory
device 110 followed by deposition of the conformal film 202.
Further, more than two films may be deposited. For example, film
202 may be deposited, as shown in FIG. 2, film 302 may be deposited
next, as shown in FIG. 3, and a second conformal film may be
deposited over film 302.
[0029] In another alternative implementation, only one film maybe
deposited, such as, for example, conformal film 202, as shown in
FIG. 2. In this implementation, conformal film 202 may have a
thickness ranging from about 100 .ANG. to about 1,000 .ANG..
[0030] In the previous descriptions, numerous specific details are
set forth, such as specific materials, structures, chemicals,
processes, etc., in order to provide a thorough understanding of
the present invention. However, the present invention can be
practiced without resorting to the details specifically set forth
herein. In other instances, well known processing structures have
not been described in detail, in order not to unnecessarily obscure
the thrust of the present invention. In practicing the present
invention, conventional photolithographic, etching and deposition
techniques may be employed, and hence, the details of such
techniques have not been set forth herein in detail.
[0031] The foregoing description of embodiments of the present
invention provides illustration and description, but is not
intended to be exhaustive or to limit the invention to the precise
form disclosed. Modifications and variations are possible in light
of the above teachings or may be acquired from practice of the
invention. For example, while series of acts has been described
above, the order of the acts may vary in other implementations
consistent with the present invention.
[0032] The preferred embodiments of the invention and a few
examples of its versatility are shown and described in the present
disclosure. It is to be understood that the invention is capable of
use in various other combinations and environments and is capable
of modifications within the scope of the inventive concept as
expressed herein. No element, act, or instruction used in the
description of the present application should be construed as
critical or essential to the invention unless explicitly described
as such. Also, as used herein, the article "a" is intended to
include one or more items. Where only one item is intended, the
term "one" or similar language is used. The scope of the invention
is defined by the following claims and their equivalents.
* * * * *